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Sheet Multiplexer &decoder

The document contains 5 problems involving the design and implementation of combinational logic circuits using multiplexers, decoders, and other gates. Problem 1 asks to design a 2x4 decoder using NOR gates with an enable input. Problem 2 gives Boolean functions and asks to implement the circuit using a decoder and additional gates. Problem 3 gives Boolean functions and asks to implement them using multiplexers only. Problem 4 asks to implement a full adder using two 4x1 multiplexers. Problem 5 describes the inputs to an 8x1 multiplexer and asks to determine the Boolean function implemented.
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0% found this document useful (0 votes)
40 views7 pages

Sheet Multiplexer &decoder

The document contains 5 problems involving the design and implementation of combinational logic circuits using multiplexers, decoders, and other gates. Problem 1 asks to design a 2x4 decoder using NOR gates with an enable input. Problem 2 gives Boolean functions and asks to implement the circuit using a decoder and additional gates. Problem 3 gives Boolean functions and asks to implement them using multiplexers only. Problem 4 asks to implement a full adder using two 4x1 multiplexers. Problem 5 describes the inputs to an 8x1 multiplexer and asks to determine the Boolean function implemented.
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© © All Rights Reserved
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1

Sheet
Problem I
Design a 2×4 decoder using NOR gates only. Include an enable input.
2
3

Problem II
Design a combinational circuit defined by the following three Boolean
functions:
F1 (A, B, C) = Σ (2, 4, 7)
F2 (A, B, C) = Σ (0, 3)
F3 (A, B, C) = Σ (0, 2, 3, 4, 7)
Implement the circuit using the decoder constructed with NAND gates and
NAND or AND gates connected to the decoder outputs.
DLD – Sheet 8 - Solution 44

Problem III:
Question 2:
Implement the following Boolean expressions with a multiplexer only

a) F (A, B, C, D) = ∑ (0, 1, 3, 4, 8, 9, 15)

A B C D F
0 0 0 0 1 Using 4 selection Lines
F= 1
0 0 0 1 1 0
0 0 1 0 0 1
F= D
0 0 1 1 1 0
0 1 0 0 1
0 1 0 1 0 F= D’ 1
0 1 1 0 0 1
0 1 1 1 0 F= 0 0
1 0 0 0 1 0
1 0 0 1 1 F= 1
0
1 0 1 0 0
F= 0 1 16*1 MUX F
1 0 1 1 0
1 1 0 0 0 1
1 1 0 1 0 F= 0
0
1 1 1 0 0
1 1 1 1 1 F= D 0
0
0
Using 3 selection Lines 0
1 D
C
1
B
A
A
A’
0
8*1 MUX F
1
0
0
A
C
B
A
DLD – Sheet 8 - Solution 5

b) F (X, Y, Z) = ∑ (1, 2, 3, 6, 7)

X Y Z F Z
0 0 0 0 1
F= Z
0 0 1 1 4*1 F
0 MUX
0 1 0 1
0 1 1 1 F= 1 1
1 0 0 0
1 0 1 0 F=0 Y
1 1 0 1 X
1 1 1 1 F= 1

c) F (A, B, C, D) = ∑ (1, 3, 4, 5, 10, 11, 12, 13, 14, 15)

A B C D F
0 0 0 0 0 D
F= D
0 0 0 1 1
D
0 0 1 0 0
F= D 1
0 0 1 1 1
0 1 0 0 1 0
8*1 MUX F
0 1 0 1 1 F= 1
0
0 1 1 0 0 1
0 1 1 1 0 F= 0
1 0 0 0 0 1
1 0 0 1 0 F= 0 1
1 0 1 0 1
F= 1 C
1 0 1 1 1 B
1 1 0 0 1 A
1 1 0 1 1 F= 1
1 1 1 0 1
1 1 1 1 1 F= 1
DLD – Sheet 8 - Solution 6

Problem3:IV
Question
Implement a full adder using two 4*1 multiplexers

Solution

X Y Z C S
0 0 0 0 0
C= 0 S= Z
0 0 1 0 1
0 1 0 0 1
0 1 1 1 C= Z 0 S= Z’
1 0 0 0 1
1 0 1 1 C=Z 0 S= Z’
1 1 0 1 0
1 1 1 1 C= 1 1 S= Z

0 Z
Z Z’
4*1 4*1
Z C Z’ S
MUX MUX
1 Z

Y Y
X X

Problem V
Question 4:
An 8*1 Multiplexer has inputs A, B, C connected to the selection inputs � , � , � ,
respectively. The data inputs � ℎ�� �ℎ � , are as follows:
� =� =� =
� =� =
� =� =
� = ′
Determine the Boolean function that the multiplexer implements
DLD – Sheet 8 - Solution 7

Solution

A B C D F
D
0 0 0 0 0
F= D 0
0 0 0 1 1
0 0 1 0 0 0
0 0 1 1 0 F= 0
1
0 1 0 0 0 8*1 MUX F
0 1 0 1 0 F= 0 D
0 1 1 0 1 1
0 1 1 1 1 F= 1 D’
1 0 0 0 0 0
1 0 0 1 1 F= D
C
1 0 1 0 1
1 0 1 1 1 F= 1 B
A
1 1 0 0 1
1 1 0 1 0 F= D’
1 1 1 0 0
1 1 1 1 0 F= 0

K-Map
CD
AB 00 01 11 10
00 0 1 0 0
01 0 0 1 1
11 1 0 0 0
10 0 1 1 1

′ ′ ′ ′
�= + + + ′ ′

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