Volume 8, Issue 7, July – 2023 International Journal of Innovative Science and Research Technology

ISSN No:-2456-2165

Performance Analysis of Reconfigurable Multiplier

Unit for FIR Filter Design
Jalaja S Pooja M.V
Dept. of VLSI Design and Technology Dept. of Electronics and Communication Engineering
Bangalore Institute of Technology Bangalore Institute of Technology
Bangalore Bangalore

Abstract:- The design of Finite Impulse Response (FIR) Keywords:- Reconfigurable Multiplier, FIR Filter, Dadda,
filter performance is analyzed using Reconfigurable Booth, Wallace, and Shift & Add Multipliers, Resource
multipliers unit (Dadda, Booth, Wallace, and Shift & Add Sharing Principle, Retime SQRT CSLA.
multipliers) and retimed SQRT CSLA block. The FIR
filter is frequently used in digital signal processing I. INTRODUCTION
technique for a variety of applications including speech
processing, loudspeaker equalization, echo cancellation, Infinite Impulse Response (IIR) filters and Finite
noise cancellation, arithmetic computations, and image Impulse Response (FIR) filters are two filters categorized in
processing. In this paper, the FIR filter takes an input digital filters. Linear phase response and inherent stability are
channel and produces multiple output channels by the two highlights of FIR filters are preferred over IIR filters.
multiplying the input samples with corresponding filter The absence of feedback in the equation of FIR filters ensures
coefficients. The reconfigurable nature of the filter allows stability, and their advantage lies in their ability to produce
for flexibility in selecting the type of multiplier based on linear phases. FIR filters find extensive use in speech
specific performance requirements or resource processing, noise cancellation, computer graphics, image
constraints. The specific architecture and processing, telecommunications, and consumer electronics
interconnections of the components, such as multipliers, applications. Multipliers play a tedious role in hardware
adders, and output channels, depend on the chosen blocks for Digital Signal Processing (DSP) and embedded
multiplier type and the desired property of the filter. The applications. The speed of multiplication determines the
nature of the Control signals is to switch between overall processor speed. To achieve high-speed data rates, FIR
different multiplier types and adjust the filter filters are commonly used due to their stability, linear phase
accordingly. To optimize the utilization of resources, a response, and non-feedback nature. FIR filters are stable
resource sharing principle is employed in the proposed because they lack feedback, unlike IIR filters. Additionally,
FIR filter architecture, regardless of the number of their linear phase response makes them highly desirable. The
channels and taps. These techniques ensure efficient novel design approach for an FIR filter, utilizing the enhanced
resource allocation and utilization. The FIR architecture Squirrel search algorithm (ESSA) and a variable latency carry
is restructured by incorporating adders and different skip adder (VL-CSKA) based Booth multiplier. The proposed
multipliers in this design. This approach effectively ESSA algorithm optimizes the filter coefficient (FC) selection
reduces the area occupied by the adders and multiplier by minimizing switching activities, taking into account ripple
blocks, resulting in improved area efficiency and delay. contents, power, and the transition width parameter. This
The structure of the FIR filter has the multipliers optimization ensures that the FIR filter meets the required
arranged in a Multiply-Accumulate (MAC) structure, specifications in the frequency domain [18]. A new multiplier
where the multiplication and accumulation operations are design that outperforms the Array, Vedic, Booth and Wallace
performed, and the delay blocks serve as the major series of multipliers which are the four main categories of
building blocks of the filter. The speed of the multiplier is parallel digital multipliers. The proposed multiplier is an
one the component of FIR filter performance, as it enhanced version based on combination of Wallace and
determines the critical path in the filter structure. As a Dadda multiplier architectures [22]. The simplicity of
result, the proposed architecture power consumption is implementation is another advantage, as FIR calculations can
less compared to existing method [18][19][20][21]. The be performed by looping a single instruction on most DSP
modified FIR filter coding is implemented using, Verilog microprocessors. In FIR filters, the total delay depends on the
Hardware Description Language (HDL). The simulation delay introduced by the adders and multipliers in the filter
and synthesis processes are carried out which allows for architecture, based on the number of taps (N) in the filter.
testing and optimization of the design. The paper Therefore, the design of FIR filters is significantly influenced
introduces a novel approach low power Reconfigurable by the adders and multipliers. For improved performance, it is
multiplier unit to design Finite Impulse Response essential to minimize the delay in the architecture of these
architecture and it shows better efficiency compared to components. FIR filters are commonly used in Digital Signal
existing architecture [9]. Processing (DSP) systems, and they operate by convolving
the input data samples with the desired unit response of the
filter. In this project, a 16-tap filter is designed, where the

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Volume 8, Issue 7, July – 2023 International Journal of Innovative Science and Research Technology
ISSN No:-2456-2165
order of the filter determines the number of multipliers and adders and Truncation Multipliers. This innovative approach
adders required. The filter output is a weighted sum of the effectively reduces the logic size from 2n to n, thereby
current input signals and previous inputs. A power efficient mitigating the size and power consumption concerns. By
design for the Wallace tree multiplier incorporating a power avoiding the use of traditional adders and multipliers, the
efficient 7:3 counter, which is composed of multiplexers and proposed methodology offers a more efficient and streamlined
XOR gates. The partial product reduction is identified as the solution for n-size repeated filters [27]. An implementation of
main contributor to the power consumption in the multiplier. Multichannel FIR (Finite Impulse Response) filter using Time
Tao address this the proposed design utilizes a counter based Division Multiplexing (TDM) the TDM mechanism allows
modular Wallace tree (CBMW) multiplier approach [19]. A for the use of a single multiplier and adder, regardless of the
novel architecture for a low power, low area shift and add number of taps and channels in the filter. By applying the
multiplier the architecture focuses on reducing the power principle of resource sharing and increasing the operating
consumption and area by modifying the conventional design. frequency of the filter, the aim is to optimize the resource
Key modifications involve minimizing the switching activities complexity of the multiplier. To achieve these two schemes
of major blocks within the multiplier such as adder and are implemented Output Product Coding (OPC) and Dual Port
counter [20]. The Radix 8 encoding multiplier utilizes a 4-bit Schematic architectures [1]. The fundamental operation of the
encoding scheme. The Radix-8 Booth multiplier exhibits filter can be achieved by employing either Multiply and
drawbacks in parameters such as delay and speed when Accumulate (MAC) blocks or shift and add algorithms. In the
compared to a Radix-4 Booth multiplier The limitations arise case of MAC, each stage of the filter necessitates an ‘n’ bit
due to the intricate nature of circuit design in the Radix-8 multiplier and an ‘n-1’ bit adder [2]. The Distributed
Booth multiplier [21]. The objective of the project is to Arithmetic (DA) algorithm aims to handle the products of
address the limitations mentioned above by designing a sums in various filtering applications and frequency transfer
reconfigurable multichannel FIR filter that can dynamically function. This algorithm utilizes a Look Up Table (LUT) that
switch between different types of multipliers, such as Dadda, stores the fixed coefficients of the FIR filter. By employing
Booth, Wallace, and Shift & Add. This flexibility allows for LUT based DA Algorithm instead of Multiply and
the selection of the most suitable multiplier type based on Accumulate (MAC) units, several advantages can be achieved
specific application requirements, optimizing the trade-offs including increased efficiency, reduced area usage, improved
between area and speed. The primary focus of the project is to speed, lower Power Consumption and decrease hardware
reduce the area and delay associated with arithmetic units, complexity [3]. The carry By Pass Adder (CBA) is employed
specifically adders and multipliers, to enhance the as a replacement for the conventional adder. By utilizing the
performance of the FIR filter. To achieve this goal, different CBA Adder, the RFIR architecture demonstrates enhanced
multiplier types, including Dadda Multiplier, Booth performance in terms of reduced area, Power consumption
Multiplier, and Shift and Add Multipliers, are explored and and delay [4]. The design Space Encompasses seven hardware
evaluated. Achieving balanced logic utilization and efficiency implementations. Initially the basic architectures of 16 tap
is the primary objective when implementing an architecture direct form (DF) Transposed form (TF), Direct Form 2 (DF2),
utilizing modern FPGAs. Balanced logic utilization refers to Transposed Form 2 (TF2) FIR filters are implemented.
effectively utilizing DSP slices, block RAMs (BRAMs), and Following that a polyphase 16 tap structure using the DF filter
look-up tables (LUTs) in a proportional manner.[23] For fixed referred to as DFPOLY, is implemented. Finally, the DF and
filter coefficients, the option of ROM-based look-up tables TF2 filter structures are pipelined in the polyphase
(LUTs) is employed, while for reconfigurable coefficients, the architecture resulting in the implementations of
option of distributed RAM-based LUTs is utilized [23]. The DFPOLYPIPE and TF2POLYPIPE [5]. In the RNS based
technique known as common subexpression elimination systema collection of moduli is employed to convert the
(CSE) is widely recognized as a popular approach for binary system into the RNS system. This conversion enables
reducing the number of logic operators (LOs) in a digital efficient implementation of arithmetic operations by
filter. This is achieved by eliminating redundant instances of minimizing carry propagation. By breaking down an
the same bit pattern [24]. The VFF-QRRLS-BC algorithm, operation into smaller operations, the RNS system reduces the
based on the QR decomposition (QRD), is a novel approach impact of carry propagation, leading to improved efficiency in
for system identification in the presence of input noise. It arithmetic computations [6]. By primarily concentrating on
incorporates bias compensation and introduces a new variable the development, analysis, and enhancement of Dynamic
forgetting factor scheme, which aims to enhance both the Partial Reconfiguration (DPR) systems, with a specific focus
convergence speed and the steady-state mean squares error of on the dynamic reconfiguration rate achievable on modern
the algorithm [25]. To enhance the efficiency and speed of devices. As a result, a distributed arithmetic (DA)
FIR filters while reducing their latency and hardware implementation that enables efficient implementations with
complexity, focus is placed on the development of high- compact hardware footprints on contemporary FPGA devices
throughput and energy-efficient designs. One approach [7]. An alternative approach for performing calculations using
involves utilizing transposed FIR filters, which naturally have variable partition hybrid type structures, with the aim of
a shorter critical path when compared to their direct form designing an advanced FIR channel. The operation pf
counterparts. Transposed filters achieve this by employing Multiply and Accumulate (MAC) play a crucial role in the
just a multiplier and an adder in their structure [26]. To FIR channel structure, where a coefficient is duplicated and
address the challenges associated with Conventional adders compared with the delayed information test before the results
and multipliers that lead to increased size and power are aggregated [8]. The Vedic Multiplier carry out
consumption in n-sized repeated filters. The XOR-Mux multiplication operations within IPU of the transpose form

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Volume 8, Issue 7, July – 2023 International Journal of Innovative Science and Research Technology
ISSN No:-2456-2165
FIR filter. This specific multiplier is well suited for S[i] = P[i][0] + P[i][1] + P[i][2] (bit-wise addition) C[i]
conducting parallel multiplication of a significant number of = P[i][0] & P[i][1] | P[i][1] & P[i][2] | P[i][0] & P[i][2] (bit-
bits [10]. The Digital Up Converter (DUC) plays a vital role wise carry-out)
in digital front-end (DFE) circuits used in various RF systems
such as communications, sensing, and imagining. Its primary The S[i] represents the sum of the three partial products,
function s to convert one or multiple channels of data from and C[i] represents the carry-out generated from the addition.
baseband to passband signal. This passband signal consists of
modulated carriers at specific radio or intermediate  Intermediate Reduction Layers: In subsequent reduction
frequencies (RF or IF), as defined by the predefined set of layers, the sum and carry-out values obtained from the
frequencies [11]. Adders and Multipliers are significant previous layer are combined in groups of three. This
components in the design of FIR filters due to their impact on process continues until there are no more carry-outs
the overall delay. The total delay of an FIR filter is remaining.
determined by the combined delay introduced by adders and
multipliers within its architecture. The number of adders and S[i] = S[i-1] + S[i] + C[i-1] (bit-wise addition) C[i] =
multipliers present in the filter’s architecture depends on value C[i-1] & S[i-1] (bit-wise carry-out)
depends on N, which represents the number of taps in the N-
tap filter [12]. The DUC technique involves filtering and Here, S[i] represents the sum of the three inputs
converting input signal into higher sampling rate. By (previous sum, current sum, and carry-in), and C[i] represents
employing multiple sampling rates in digital signal the carry-out generated from the addition.
processing, a software defined radio (SDR) can benefit from
increased flexibility. SDR refers to a single device that Final Reduction Layer: The final reduction layer
supports various standards accommodating, different sample combines the remaining sum values and carry-outs to obtain
rates, channel bandwidths, and carrier to noise ratios [13]. the final product. The last reduction layer may not have three
Discrete time (DT) domain circuits are becoming increasingly inputs, depending on the number of bits in the operands.
popular in various architectures, including N-path filters,
sampling mixers and analog FIR/IIR/ FFT filters within this S_final = S[n-2] + S[n-1] + C[n-2] (bit-wise addition)
particular environment. Implementing discrete-time analog
signal processing (DT-ASP) before an ADC brings significant C_final = C[n-2] & S[n-2] (bit-wise carry-out)
advantages such as relaxed requirements for the ADC through
flexible filtering, the potential to improved dynamic range Here, S_final represents the final sum, and C_final
performance, and enhanced robustness in the face of digital represents the final carry-out.
CMOS scaling [14]. As the number of additions and
multiplications increases the computational complexity also  Booth Multiplier
grows. It explores the various implementation techniques for
FIR filters. This FIR filter aims to minimize the number of  Initializations:
arithmetic operations needed for inner product calculations to
be a predetermined value. One such technique involves  Initialize two variables: M (multiplicand) and Q
utilizing a look up table (LUT) design where pre-computed (multiplier).
results are stored simplifying the overall process [15]. The  Initialize an extra bit, Q (-1), initially set to 0.
fundamental of frequency sampling method for designing
Finite Impulse Response in communication systems. It  Iterations:
emphasizes the FIR architecture optimization technique for Repeat the following steps for each group of Radix-4
prototyping and hardware base 2D FIR filter models [16]. digits in the Multiplier.

II. RECONFIGURABLE MULTIPLIER UNIT  Check the pattern formed by the least significant two
Radix-4 digits of Q and Q (-1).
Conventional method of Dadda, Booth, Wallace, and  Based on the pattern, perform a specific operation:
Shift & Add multipliers pseudo code is written below.
 If the pattern is 01, add M to an accumulator.
 Wallace Tree Multiplier  If the pattern is 10, subtract M from the accumulator.
The Wallace tree algorithm combines adjacent partial  If the pattern is 00 or 11, no operation is performed.
products using a series of reduction layers. Here are the
equations used in each reduction layer of the Wallace tree  Right-shift Q and Q (-1) by 2 Radix-4 positions,
algorithm: discarding the least significant Radix-4 digit of Q and
assigning the previous least significant Radix-4 digit of Q
 Initial Reduction Layer: In this layer, adjacent partial to Q (-1).
products are added together in groups of three. The
resulting sum and carry-out are computed as follows:

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ISSN No:-2456-2165
 Final Result: The carry outputs (C) from each level are fed into the
next level to propagate the carries.
 The final result is obtained by considering the
accumulated value in the accumulator after iterating  Final Product Calculation: After the reduction process, the
through all the groups of Radix-4 digits in the multiplier. final product is obtained by adding all the sums from the
reduction tree, taking into account the carries from the last
level:
 Shift and Add Multiplier
Final Product = S [0, N-1] + C[N-1,0] + C[N-1,1] + ... +
 Initialization: C [N-1, M-1]

 Initialize two variables: M (multiplicand) and Q Where N is the number of bits in the multiplicand and M
(multiplier). is the number of bits in the multiplier.
 Initialize a product register, initially set to 0.
III. PROPOSED METHOD
 Iterations:
Repeat the following steps for each bit in the multiplier, Consider the N-tap FIR filter mathematical expression
starting from the least significant bit: or equation is given by below

 If the least significant bit of Q is 1, add the multiplicand M

to the product register.
 Right-shift the product register by 1 bit.

 Final Result:
The final result is obtained from the value stored in the
product register after iterating through all the bits of the
Where x(n) = input value
multiplier.
Y(n) = output value
bi = filter coefficient
 Dadda Multiplier
N = filter order
The Dadda multiplier algorithm involves several
equations to perform partial product generation and reduction.
In above equation Y(n) composed of sum and product
Let's go through the equations step by step:
units. In proposed method retimed CSLA is used to reduce the
carry propagation delay. For multiplier unit novel based
 Partial Product Generation: For each pair of bits (A[i],
reconfigurable multiplier unit used to reduce the power
B[j]), where A is the multiplicand and B is the multiplier:
consumption of design.
 Generate a partial product P[i,j] by multiplying the two
The Square root- Carry select adder block increases the
bits: P[i,j] = A[i] * B[j]
longest path delay of the final output addition. In figure (1)
Group 1 represents 2 bit ripple carry adder similarly group2,
 Partial Product Reduction: The partial products generated group 3, group 4 and group 5 indicate 4 bit, 8 bit, 13 bit and
in step 1 are then reduced using a carry-save adder (CSA) 19 bit ripple carry adder block respectively. The proposed
structure and a reduction tree. The CSA combines three architecture, the C0 block multiplexer is retimed itself to
partial products and produces two outputs: the sum (S) and reduce the critical path delay. In conventional method linear
the carry (C). The reduction tree operates in a cascading CSLA and SQRT CSLA is directly proportional to addition
manner, where the carries from one level are propagated to speed and number of bit length N. In proposed adder retimed
the next level. flipflops are placed to reduce delay for carry propagation.
CSLA consists of large combinational blocks the global
The equations for the reduction tree can be represented retiming is applied for full design and registers is moved
as follows: across each critical path logic structure. In figure (1) the final
addition and carry are selected by multiplexer each cutset
 S [0,0] = P [0,0] introduce delay that breaks the path delay. The same
 S [0,1] = P [0,1] + P [0,2] + C [0,0] procedure is applied to entire CSLA block to reduce final
 S [0,2] = P [0,3] + P [0,4] + C [0,1] critical path.
 S [1,0] = P [1,0] + P [2,0] + C [0,0]
 S [1,1] = P [1,1] + P [2,1] + P [3,0] + C [0,1] + C [1,0]
 S [1,2] = P [1,2] + P [2,2] + P [3,1] + P [4,0] + C [0,2] + C
[1,1]

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Fig 1 Cutset Retime SQRT-CSLA

In a reconfigurable multiplier as shown in figure (2) the

coefficient values and input bits can be dynamically
programmed into different types of multipliers. The idea
behind this reconfigurable multiplier is to improve the
performance of FIR filter output in an efficient way. The
reconfigurable FIR filter with multichannel multiplier data
flow graph is as shown in figure (3). The input values
obtained from the multiplier mux are then directed to an
adder. The adder performs the addition operation on these
inputs. The purpose of this operation may vary depending on
the specific requirements of the system or application. The
output of the adder can be further processed or utilized in
subsequent stages of the system for various purposes the
optimization of resource consumption in a system that
involves multiple filters. Specifically, it suggests reducing the
number of filters by utilizing the programmability of Finite
Impulse Response (FIR) filters. However, reusing the same
filter block for every sample in all 40 filters can introduce a
notable increase in latency. To address this issue, one option
is to increase the clock frequency by a factor of 40. This
increase in clock frequency would allow for faster processing
of the samples, reducing the overall latency of the algorithm. Fig 3 Data Flow Graph of Proposed Filter

IV. RESULTS AND COMAPRISION

The figure (4) show simulation results of Wallace-tree

Multiplier. The coefficients from H(0) to H(15) and inputs
from CH1 to CH8 feed to Dadda, Booth, Wallace, and Shift &
Add multipliers. Based on channel selection multiplier type is
selected using multiplexer. The snapshot of 16-tap FIR Filter
using Booth Multiplier filter is shown in figure (5). The
multiplier mux output is feed to the adder unit to get final
filtered data is illustrated in figure (6). The figure (7) shows,
LUT’s, & Slices from Technological Schematic.

Fig 2 Proposed Reconfigurable Multiplier Unit

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Volume 8, Issue 7, July – 2023 International Journal of Innovative Science and Research Technology
ISSN No:-2456-2165

Fig 6 Simulation Results of 16-tap FIR Filter Final Output

Fig 4 Simulation Results of Wallace-Tree Multiplier Using

Model Sim

Fig 5 Simulation Results of 8bit 16-tap FIR Filter for Shift &
Add Multiplier Using Model Sim FIR Filter Fig 7 LUT’s, & Slices from Technological Schematic

The Table 1 and 2 shows the synthesis report of 16-bit retimed SQRT CSLA and modified 16-bit multiplier design
Summary. It shows the Gate Count, delay, Slices and area comparison with existing method.

Table 1 Delay and Area Count of 16-bit SQRT CSLA Groups

ARCA SQRT CSLA [15] Modified SQRT CSLA
Type
Delay [ps] Area [μm2] Delay [ps] Area [μm2]
Group 1 6 19 4 17
Group 2 10 44 9 38
Group 3 12 74 11 63
Group 4 14 104 12 94
Group 5 16 134 15 102

Table 2 Delay and Area Count of 16-bit Multiplier

Proposed multiplier using modified SQRT CSLA Existing System
Method Name
Slices Gate Overall Delay(ns) Slices Delay (ns)
Wallace-Tree Multiplier [18] 3523 8995 38.02 7474 72.47
Booth Multiplier[21] 1567 8819 12.5 1690 13.993
Shift & Add Multiplier[19] 778 8663 39.238 662 48.812
Dadda Multiplier[20] 2677 8621 2.277 3262 2.64

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Volume 8, Issue 7, July – 2023 International Journal of Innovative Science and Research Technology
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The performance of FIR filter using proposed reconfigurable multiplier unit synthesized using 180nm technology. The power,
area and delay of 8bit 7-tap and 16-Tap FIR filter design performance is compared with existing design [9] is compared in Table
3. As a result, the proposed design shown much better result in terms of area-delay-product and power-delay-product is as shown
in Table 4.

Table 3 180 nm Technology Area, Power and Delay Performance of 8-bit RFIR Design
Architectures Bits and Taps Area [μm2] Power [nW] Dealy [ps]
RFIR–R2–LCSLA [9] 8B and 7T 2,14,781 19,84,548 258
RFIR–R2–LCSLA[9] 8B and 7T 2,14,781 19,84,548 258
RFIR–APC–OMS[9] 8B and 7T 1,92,962 11,40,187 130
Proposed RFIR 8B and 7T 1,98,453 10,32,091 102
Proposed RFIR 8B and16T 1,99,268 10,57,080 114

Table 4 180 nm Technology Area Power Product and Area Delay Product Performance of 8-bit RFIR Design
APP ADP
Architectures Bits and Taps
[μm2 *nW ] [μm2 *ps ]
RFIR–R2–LCSLA[9] 8B and 7T 4,26,24,32,03,988 5,54,13,498
RFIR–R2–LCSLA[9] 8B and 7T 4,26,24,32,03,988 5,54,13,498
RFIR–APC–OMS[9] 8B and 7T 2,20,01,27,63,894 2,50,85,060
Proposed RFIR 8B and 7T 2,04,82,15,55,223 2,02,42,206
Proposed RFIR 8B and16T 2,10,64,22,17,440 2,27,16,552

V. CONCULSION [3]. Pradnya D. Shahare, Samrat S. Thorat. A Review:

FPGA Implementation of Reconfigurable Digital FIR
Advanced multiplication techniques offer to optimize the Filter. International Journal of Science and Research
area and delay utilization to enhance the performance of the (IJSR) ISSN (Online): 2319-7064 Volume 5 Issue 3,
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Shift & Add, Booth, and Dadda, offer varying trade-offs in [4]. Kasarla Satish Reddy, Hosahally Narayangowda
terms of complexity and performance. The proposed structure Suresh. A Low Power VLSI Implementation of
of a reconfigurable multiplier unit for FIR filter Reconfigurable FIR Filter Using Carry Bypass Adder.
implementation provides opportunities for future International Journal of Intelligent Engineering and
developments in digital signal processing. It demonstrates the Systems, Vol.11, No.2, 2018.
novel architecture flexibility and adaptability for filter design [5]. Subhankar Bhattacharjeea, Sanjib Silb Amlan
to process multiple channels of data simultaneously. By Chakrabartic . Evaluation of Power Efficient FIR Filter
focusing on aspects such as filter structure, configurable taps for FPGA Based DSP Applications. International
and performance optimization, the proposed design lays a Conference on Computational Intelligence: Modeling
strong foundation for future advancements. It paves the way Techniques and Applications (CIMTA) 2013.
for further improvements and innovations in the field of [6]. J. Britto pari & S P Joy Vasantha Rani. Reconfigurable
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