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Case Statement

The document discusses case statements in Verilog. It describes how case statements create combinational logic and are easier to read than nested if statements. It also summarizes the syntax of case statements and some common variations including using begin/end blocks, matching multiple values, and using a default case. It discusses issues that can occur if all possibilities are not accounted for in a case statement. It also describes how the unique and priority keywords provide additional information to guide synthesis and act as assertions in simulation.

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30 views10 pages

Case Statement

The document discusses case statements in Verilog. It describes how case statements create combinational logic and are easier to read than nested if statements. It also summarizes the syntax of case statements and some common variations including using begin/end blocks, matching multiple values, and using a default case. It discusses issues that can occur if all possibilities are not accounted for in a case statement. It also describes how the unique and priority keywords provide additional information to guide synthesis and act as assertions in simulation.

Uploaded by

panda pavan
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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case Statement

I case also creates combinatorial logic and is easier to read when if


statements are nested more than three deep or when many checks
are made against the same expression.
I When the case selection item matches the case expression, the
corresponding assignments are made.
case ( c as e_ e xp re ss i on )
case_selection_item1 : case_item_statement1 ;
c a s e _ s e l e c t i o n _ i t e m 2 : begin
case_item_statement2a ;
case_item_statement2b ;
case_item_statement2c ;
end
case_selection_item3 : case_item_statement3 ;
[ default : c a s e _ i t e m _ s t a t e m e n t 5 ;] // optional
endcase
case Statement

I Looks like a completely specified case statement. But, what


happens when sel takes on the value 2’b0X? Is that possible?
What would happen?

module mux4_1 (
input sel ,
input din_0 , din_1 , din_2 , din_3 ;
output logic d_out );
always_comb
case ( sel )
2 ’ b00 : d_out = din_0 ;
2 ’ b01 : d_out = din_1 ;
2 ’ b10 : d_out = din_2 ;
2 ’ b11 : d_out = din_3 ;
endcase
endmodule
case Statatement

I Common variations for case statement


I Verilog has an implied break statement unlike C
always_comb
case ( data_in )
0 : a = 1; // simple match
1 : begin // bracket multiple statements with begin / end
a = 1;
b = 1;
end
2 ,3 ,4 : c = 1; // match multiple values
default : c = 0; // catch other possibilities
endcase
case Statatement
I Not accounting for all possibilities causes problems

// incomplete case , 3 x1 mux


module case2 (
input [7:0] a_in ,
input [7:0] b_in ,
input [7:0] c_in ,
input [1:0] sel ,
output logic [7:0] d_out );

always_comb
case ( sel )
2 ’ b00 : d_out = a_in ;
2 ’ b01 : d_out = b_in ;
2 ’ b10 : d_out = c_in ;
endcase
endmodule

Inferred memory devices in process in routine case2 line 6 in file ’case2.sv’.


===========================================================================
| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST |
===========================================================================
| d_out_reg | Latch | 8 | Y | N | N | N | - | - | - |
===========================================================================
Warning: Netlist for always_comb block contains a latch. (ELAB-974)
case Statatement

I SystemVerilog unique and priority clarify imcompletely specified


case statements.
I Both give information to synthesis to aid optimization.
I Both are assertions (simulation error reporting mechanisms)
I Both imply that there is a case item for all the possible legal values
that case expression might assume.
case Statatement

I Unique is an assertion which implies:


I All legal values of case expression are listed in the case items
I At simulation run time, a match must be found in case items
I At simulation run time, only one match will be found in case items
I Unique guides synthesis
I It indicates that no priority logic is necessary
I This produces parallel decoding which may be smaller/faster
I Unique usage
I Use when each case item is unique and only one match should
occur.
I Using a ”default” case item removes the testing for non-existent
matches, but the uniqueness test remains.
case Statatement
I Incomplete case with unique

// incomplete case , 3 x1 mux


module i nc o mp le t e_ ca se (
input [7:0] a_in ,
input [7:0] b_in ,
input [7:0] c_in ,
input [1:0] sel ,
output logic [7:0] d_out );

always_comb
unique case ( sel )
2 ’ b00 : d_out = a_in ;
2 ’ b01 : d_out = b_in ;
2 ’ b10 : d_out = c_in ;
endcase
endmodule
case Statatement

always_comb
unique case ( sel )
2 ’ b00 : d_out = a_in ;
2 ’ b01 : d_out = b_in ;
2 ’ b10 : d_out = c_in ;
endcase

I In this case, unique case asserts that...


I sel should only take on values of 2’b00, 2’b01, or 2’b10. If any
other values are encountered in simulation, an error will occur.
I The selction items, 2’b00, 2’b01, or 2’b10 are mutually
exclusive, thus only one item should match sel.
I No priority logic is necessary.
case Statatement
I Priority is an assertion which implies:
I All legal values for case expression are listed in case items.
I At least one case item should match case expression.
I If more than one select expression matches the case expression, the
first matching branch must be taken.
I Priority guides synthesis
I All other possibilies for case items are don’t cares and may be used
to simplify logic.
I Priority usage
I Explicitly says that priority is important even though the Verilog case
statement is a priority statement.
I Using a default case item will cause priority requirement to be
dropped since all cases are available to be matched.
I Use of a ”default” also indicates that more than one match in
case item is OK.
I Priority is a bad name. Case is already a priority structure.
case Statatement
I Interrupt priority encoder
always_comb begin
priority case (1 ’ b1 )
irq0 : irq = 4 ’ b0001 ; // Highest Priority
irq1 : irq = 4 ’ b0010 ;
irq2 : irq = 4 ’ b0100 ;
irq3 : irq = 4 ’ b1000 ; // Lowest Priority
endcase
end

I priority indicates:
I One of the case items must be true.
I More than one interrupt request is legal.
I If multiple requests occur, evaluate them in order.

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