Programs

Appendix C
Revision 1.0
Version 21.10
Appendix Objective
In this appendix, you
● Identify the features of programs for verification code

2 © Cadence Design Systems, Inc. All rights reserved.

Programs
IEEE 1800-2012 24 program memtest (
output wire [7:0] data;
output bit [4:0] addr;
output bit read, write);
● A program is very similar to a module, but intended for ...
initial begin
testbench code.
...
▪ Allows separation of design and test. end
▪ Is executed in a separate time region to avoid design/test endprogram : memtest
races.
o Programs execute in the Reactive region.
module top;
o Modules execute in the Active region.
wire [7:0] data;
● Program blocks have special features and restrictions wire [4:0] address;
for testbench use. wire read, write;

● In particular, a program cannot instantiate hierarchy. memtest test (.*);

memory mem8x32 (.*);
▪ Programs are leaf elements.
▪ Must be instantiated in a module. endmodule : top

3 © Cadence Design Systems, Inc. All rights reserved.

Program Construct Restrictions
Allowed: Not Allowed:
● Local data declarations ● always blocks
▪ Variables
● Declaration or instantiation of:
▪ User-defined types
▪ Interface
▪ Classes
▪ Module
● initial and final blocks ▪ Primitive
● generate blocks ▪ Program

● Task and function declarations ● Anything specific to modules

▪ Parameter overrides (defparams)
▪ Only visible in program block
▪ specify blocks
● Continuous assignments ▪ specparam declarations
● Clocking blocks
● Concurrent assertions
● Functional coverage groups (covergroups)

4 © Cadence Design Systems, Inc. All rights reserved.

Example: Program Access Restrictions
program test1 (output reg t1);
● Only programs can access these program
bit [3:0] addr;
declarations: ...
▪ Signals (including ports) endprogram : test1
▪ Subroutines
program test2 (output reg t2);
● Hierarchical references from one program to wire [3:0] save;
another are legal. // good program access
assign save = top.t1.addr;
● A program can access any design declarations,
...
including: endprogram : test2
▪ Signals
▪ Subroutines module top;
o Executed in reactive region wire top_a, temp_a;
dut d1 (top_a);
test1 t1 (top_a);
test2 t2 (top_a);  Error
// illegal program access
assign temp_a = t1.addr[3];
endmodule: top

5 © Cadence Design Systems, Inc. All rights reserved.

Program Block Scheduling
Preponed
Previous time slot

Active

Active regions iteratively execute

Inactive module and interface code until
steady-state is achieved
NBA

Observed

Reactive

Reactive regions iteratively execute

Re-inactive program code until
steady state is achieved
Re-NBA

Postponed
6 © Cadence Design Systems, Inc. All rights reserved. To next time slot
Program Block: $exit System Task
● You can call $exit only from a program. program test1;
● Terminates all processes in the current program. ...
▪ Initial blocks and their subprocesses.
initial begin
...
▪ Not continuous assignments.
if (timeout_error)
▪ Not tasks called from other programs. $exit();
● Also called implicitly after all initial blocks in a program ...
are complete. endprogram : test1
▪ In other words, they have executed their last statement.
● $finish is called when all program blocks have exited.
p1 p2
▪ Either explicitly through $exit or normally (implicit $exit).

exit

exit
finish

7 © Cadence Design Systems, Inc. All rights reserved.

Implicitly Instantiated/Anonymous Programs
● Programs can be nested in modules/interfaces. module test(...);
● Nested programs without ports need not be program p1;
instantiated. ...
▪ Each is implicitly instantiated once. endprogram
program p2;
▪ Instance name is the same as definition name.
...
● Top-level programs can also be implicitly endprogram
instantiated.
...
● Anonymous programs are unnamed. endmodule : top
▪ Declared in compilation unit scope or package only.
▪ Contain declarations only (a restricted subset) – no package program_decls;
processes. program;
▪ Declarations follow program rules. task do_stuff;
...
endtask
endprogram
endpackage

8 © Cadence Design Systems, Inc. All rights reserved.