Drill 4 Soquiat Marc Hendri

MAPUA UNIVERSITY
SCHOOL OF EE-ECE-CpE
User-Defined Primitives
DRILL 4
NAME: Marc Hendri Soquiat

STUDENT NUMBER: 2021103916
TERMINAL NUMBER:
DATE OF PERFORMANCE: 06/28/2023
DATE OF SUBMISSION: 06/28/2023
Mark Jayson Sutayco

PROFESSOR
I. DISCUSSION
The logic gates used in HDL descriptions with keywords and, or, etc. are defined by
the system and are referred to as system primitives. The user can create additional
primitives by defining them in a tabular form. These types of circuits are referred to
as user-defined primitives (UDPs). One way of specifying a digital circuit in tabular
from is by means of a truth table.
General rules for defining a UDP:

• Starts with the keyword primitive, and ends with the keyword
endprimitive
• The keyword primitive should be followed by an identifier, a list of
ports, and followed by a semicolon (;)
• Order in which they are listed in the input declaration must conform to
the order in which they are given values in the table that follows.
• The table inside your primitive should be enclosed within the keywords
table and endtable.
• The values of inputs are listed in order, ending with a colon (:). The
output is always the last entry in a row and is followed by a semicolon
(;)
• Port lists should contain any number of inputs but only a single output.
There are two types of behaviour that can be defined in UDP.
1. Combinational UDP
• This table specifies the various input combinations and their
corresponding output values. Any combination that is not specified is
an x for the output.
2. Sequential UDP
• The internal state is described using a 1-bit register.
• It uses the current value of the register and the input values to
determine the next value of the register.
2
• Its model requires that its output be declared as reg data type, and
that column be added to the truth table to describe the next state.
So the columns are organized as: inputs: state:
next state
The state of a sequential UDP can be initialized by using an initial statement

that has one procedural assignment statement. This is of the form: initial
reg_name = 0, 1 or x ;
The following is the summary of table entries.
Symbol Meaning
0 logic 0
1 logic 1
x unknown
? any of 0, 1, or x
b any of 0 or 1
- no change
(AB) value change from A to B
* same as (??)
r same as (01)
f same as (10)
p any of (01), (0x), (x1)
n any of (10), (1x), (x0)
II. Drill Exercises

NOTE: Include the screenshot of the output and the timing diagram
A. Create a UDP description of a 3-bit majority circuit.

3
We can consider that the output of this circuit is 1 if the input vector has two
or more 1’s. The program below shows a synthesis of a majority circuit with the
corresponding test bench. Note that the declaration input A, B, C matters because
this is how Verilog will determine which input belongs to which column. Copy the
code then simulate.
primitive Majority3 ( Z, A, B, C ) ; input

A, B, C ;
output Z ; table
// A B C Z
0 0 ? : 0;
0 ? 0 : 0;
? 0 0 : 0;
1 1 ? : 1;
1 ? 1 : 1;
? 1 1 : 1;
endtable
endprimitive
module testprimitive1;
reg A, B, C;
wire X;
Majority3 (X,A,B,C);
initial begin
A=1'b0;B=1'b0;C=1'b0;
$display(" A B C X");
$monitor(" %b %b %b %b",A,B,C,X);
#2 A=1'b0; B=1'b0; C=1'b0;
#2 A=1'b0; B=1'b0; C=1'b1;
#2 A=1'b0; B=1'b1; C=1'b0;
#2 A=1'b0; B=1'b1; C=1'b1;
4
#2 A=1'b1; B=1'b0; C=1'b0;
#2 A=1'b1; B=1'b0; C=1'b1;
#2 A=1'b1; B=1'b1; C=1'b0;
#2 A=1'b1; B=1'b1; C=1'b1;
#2 $finish;
end endmodule
B. Create a UDP description of a positive-edge triggered T flip-flop.
The table below shows an example of sequential UDP. Simulate the program;
save it as drill4_2.vl
primitive T_FF(F, clk, T);

input clk, T; output
F;
reg F;
initial F=0;
table
// CLK T : F(STATE) : F(NEXT)
(01) ? : x : 0 ;
(01) 0 : 0 : 0 ; (01)
0 : 1 : 1 ; (01)
1 : 0 : 1 ; (01) 1
: 1 : 0 ; (10) ? :
x : 0 ; (10) 0 : 0
: 0 ; (10) 0 : 1
: 1 ; (10) 1 : 0 :
0 ;
(10) 1 : 1 : 1 ;
endtable
endprimitive
module pri;
5
reg x, clk;
wire y;
T_FF TF(y, clk, x);
initial begin x=0;

clk=0;
end
always #1 clk=!clk;
initial begin
x=0; #4
x=1;
repeat(8)
#8 x=~x; end
initial begin
$display(" TIME clk T Q");
$monitor($time,,," %b %b %b ",clk, x, y);
#16 $finish; end
endmodule
III. Programming Exercise (Choose 1)

NOTE: Include the screenshot of the output and the timing diagram
1. Design a combinational UDP of 8x1 demultiplexer. Save as

exercise4_1.vl.
2. Design a combinational UDP of a binary subtractor.
IV. Review Questions

1. Can you implement UDP for circuits with multiple outputs? If yes, how?
6
Yes, you can implement UDP for circuits with multiple outputs. To do
this, you must define the outputs as separate output ports in the
primitive module declaration. While you can define the behavior of
each output based on the inputs and any internal logic inside the
primitive.
2. Why do you need to declare the output of sequential UDPs as reg?
If we declare the outputs as reg, it signals that the output is a
registered value that can store information. The output will maintain
its value until it is updated by a clock edge or a specific triggering
condition.
3. What type of table is being placed inside the program to create a
sequential UDP? Can you display the other tables using the created
UDP? If yes, how?
A look up table or a state table. Yes, you can display other tables using
the created UDP by providing more specific information about the
program and the UDP implementation. The tables used in the UDP
would typically be defined within the program code or provided as
input to the program. By accessing or modifying the code or input data,
you can view and manipulate the contents of those tables.
4. Explain the entry below:
//Clk Clr Data : Q(state) : Q(next)
(?0) 1 b : 0 : - ;
The entry provided above describes the behavior of a sequential circuit
element inside of one row of a table. This entry suggests that when the
clock signal doesn't matter (?0), and the clear signal is active, the
output signal is in the state 0, and the next state of the output signal is
not defined or don't-care.
7
INTERPRETATION OF RESULTS
In this experiment, we focus on User-Defined Primitives. These are
additional primitives added to the system by the users. In this activity, we are
tasked to choose one programming exercise. The choices were creating a
combinational UDP of 8x1 demultiplexer or a combinational UDP of a binary
subtractor. I choose the combinational UDP of a binary subtractor. After coding,
you can see in the provided screenshots in the folder the output of the program
(truth table) together with the timing diagram. In the truth table, A, B, and Bin are
the input of the operation providing with 8 different combinations. Diff is the
difference output with consideration of the borrow input (Bin). Lastly, Bout
represents the borrow output. It indicates whether a borrow occurred during the
operation.
8
RESULTS AND CONCLUSION
In this experiment, we learned about User-Defined Primitives and its
guidelines and types of behavior it can define. We learned that a UDP starts with a
keyword primitive and ends with the keyword endprimitive. The table inside the
primitive should be defined by the table keywords and ends with an endtable
keyword. These are just some of the rules in using UDP. For the programing exercise
done in this laboratory experiment, we utilize defining the Combinational behavior
of a circuit. In a combinational UDP, various input combinations are specified with
correspondence to their outputs as per observed in the finished activity. Overall,
the logic gates used in HDL are already defined in the system, it is within the user
that they add other primitives in the system.

Drill 4 Soquiat Marc Hendri

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MAPUA UNIVERSITY

NAME: Marc Hendri Soquiat

Mark Jayson Sutayco

General rules for defining a UDP:

There are two types of behaviour that can be defined in UDP.

The state of a sequential UDP can be initialized by using an initial statement

The following is the summary of table entries.

II. Drill Exercises

A. Create a UDP description of a 3-bit majority circuit.

primitive Majority3 ( Z, A, B, C ) ; input

B. Create a UDP description of a positive-edge triggered T flip-flop.

primitive T_FF(F, clk, T);

T_FF TF(y, clk, x);

initial begin x=0;

III. Programming Exercise (Choose 1)

1. Design a combinational UDP of 8x1 demultiplexer. Save as

IV. Review Questions

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