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Setting standards in VLSI Design

Final Test
Time: 3 Hrs Total Marks: 100
Part – A
Marks: 40
Digital (12 Marks)
1. The clock frequency applied to the digital circuit shown in the figure below is 1 kHz. If the initial state
of the output of the flip-flop is 0, then what is the frequency of the output waveform ‘Q’? --(4M)

2. Implement 16 ×4 RAM using 4×4 RAM chips. -- (3M)

3. Draw a Moore model FSM for a sequential circuit whose output will get toggled when it detects ‘101’
pattern in the input stream. (The overlapping sequence is allowed) -- (5M)

Verilog (12 Marks)

4. What is the logic that gets synthesized when conditional operators in a single continuous assignment
are nested? -- (4M)

input sel1,sel2,sel3,in1,in2,in3,in4;
output out1;
assign out1 = (sel1 == 1’b1) ? in1 :
(sel2 == 1’b1) ? in2 :
(sel3 == 1’b1) ? in3 : in4;

5. Given the following Verilog code, what value of "a" is displayed? -- (3M)

always @(clk)
begin
a = 0;
$display(a);
a<=1;
$strobe(a);
end

6. Write RTL code to design an odd parity detector for a 4-bit data using task construct. -- (5M)

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Setting standards in VLSI Design

Verification (16 Marks)

7. Write a code to generate unique elements in an array without using a unique keyword in the constraint?
-- (4M)

8. Predict the output of the following code. -- (4M)

class packet;
static int ID = 0;
int aid = 0;
function new();
ID++;
aid++;
$display("ID = %0d \t aid = %0d",ID,aid);
endfunction
endclass : packet
class generator;
task start();
packet pkt_h = new();
$display("%0d",pkt_h);
endtask : start
endclass : generator

module sp_test();
generator gen[4];
initial
begin
foreach (gen[i])
begin
gen[i] = new;
$display(gen[i]);
end
gen[0].start();
gen[1].start();
repeat(10)
gen[2].start();
gen[3].start();
end
endmodule

9. In UVM how to get config_db inside a component & an object? -- (4M)

10. Write an assertion to the following condition:

When the positive edge of signal “a” is detected, in the next cycle check signal “b” has to
be high continuously until signal “c” goes low. -- (4M)

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Setting standards in VLSI Design

Part – B
Marks: 40
Digital (12 Marks)
11. Design positive edge triggered D flip-flop using tristate buffers and inverters. --(5 M)

12. Design a four-bit barrel shifter that rotates the bits by 0, 1, 2, or 3-bit positions as determined
by the valuation of two control signals S1 and S0 using a 4:1 multiplexer. --(7M)

Verilog (12 Marks)

13. Write RTL code for a 10-bit Ripple carry Adder using Full adder instances by implementing the
“generate loop” construct. --(7 M)

14. Draw the waveform for the following : --(5M)

reg clk,d,q;

always@(negedge clk)
begin
q <= @(posedge clk) d;
end

initial
begin
clk = 0;
d = 1;
while(1)
#10 clk = ~clk ;
end

always@(posedge clk)
d = ~d ;

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Setting standards in VLSI Design

Verification (16 Marks)

15. Calculate the total coverage from the following snippet?

module test();
class coverage;
bit [3:0] a;
covergroup exe;
option.per_instance=1;
coverpoint a;
endgroup

function new();
exe=new();
endfunction
endclass
coverage c_h;

intial begin
for (int i=0; i<3;i++) begin
c_h =new();
c_h.a=i; end
end
endmodule -- (4M)

16. For the following test bench architecture write a code to set agent [0] as passive and agent [1] and
agent [2] as active with the help of a configuration object. --(7M)
Note: Show the required configuration class definitions

17. Explain the UVM factory registration process for the UVM object and UVM components with an
example. What is the necessity of a UVM factory? -- (5M)

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Setting standards in VLSI Design

Part – C (Basic Electronics, CMOS, Networks, FPGA, STA)

Marks: 20
18. For the following specifications, check the circuit for any violations & fix them if any. -- (5M)

19. Design CMOS circuit for 3-input NAND gate. -- (5M)

20. Write any five Ideal Characteristics of an Op-Amp. -- (5M)
21. Explain the operation of the Bridge rectifier with relevant equations and diagrams. -- (5M)

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