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Lec2 Example

The document describes the implementation of basic logic gates in VHDL including AND, OR, XOR, NOR, NAND and XNOR gates. It shows the entity declaration and two architectures for each gate - one using a process to implement the logic based on truth tables, and one assigning the output directly to the logic operation.

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Miller 87
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16 views6 pages

Lec2 Example

The document describes the implementation of basic logic gates in VHDL including AND, OR, XOR, NOR, NAND and XNOR gates. It shows the entity declaration and two architectures for each gate - one using a process to implement the logic based on truth tables, and one assigning the output directly to the logic operation.

Uploaded by

Miller 87
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Example_1// AND gate

library ieee;
use ieee.std_logic_1164.all;

entity AND_ent is
port( x: in std_logic;
y: in std_logic;
F: out std_logic
);
end AND_ent;

architecture behav1 of AND_ent is


begin

process(x, y)
begin
-- compare to truth table
if ((x='1') and (y='1')) then
F <= '1';
else
F <= '0';
end if;
end process;

end behav1;
--------------------------------------------
architecture behav2 of AND_ent is
begin
F <= x and y;
end behav2;
Example_2// OR gate

library ieee;
use ieee.std_logic_1164.all;

entity OR_ent is
port( x: in std_logic;
y: in std_logic;
F: out std_logic
);
end OR_ent;

architecture OR_arch of OR_ent is


begin

process(x, y)
begin
-- compare to truth table
if ((x='0') and (y='0')) then
F <= '0';
else
F <= '1';
end if;
end process;
end OR_arch;
-------------------------------------------------------------------------
architecture OR_beh of OR_ent is
begin
F <= x or y;
end OR_beh;

Example_3//X OR gate
library ieee;
use ieee.std_logic_1164.all;

entity XOR_ent is
port( x: in std_logic;
y: in std_logic;
F: out std_logic
);
end XOR_ent;

architecture behv1 of XOR_ent is


begin

process(x, y)
begin
-- compare to truth table
if (x/=y) then
F <= '1';
else
F <= '0';
end if;
end process;

end behv1;

architecture behv2 of XOR_ent is


begin

F <= x xor y;

end behv2;

Example_4//NOR gate
library ieee;
use ieee.std_logic_1164.all;

entity NOR_ent is
port( x: in std_logic;
y: in std_logic;
F: out std_logic
);
end NOR_ent;

architecture behv1 of NOR_ent is


begin

process(x, y)
begin
-- compare to truth table
if (x='0' and y='0') then
F <= '1';
else
F <= '0';
end if;
end process;

end behv1;

architecture behv2 of NOR_ent is


begin

F <= x nor y;

end behv2;

Example_5//NAND gate
library ieee;
use ieee.std_logic_1164.all;

entity NAND_ent is
port( x: in std_logic;
y: in std_logic;
F: out std_logic
);
end NAND_ent;

architecture behv1 of NAND_ent is


begin

process(x, y)
begin
-- compare to truth table
if (x='1' and y='1') then
F <= '0';
else
F <= '1';
end if;
end process;

end behv1;

architecture behv2 of NAND_ent is


begin

F <= x nand y;

end behv2;

Example_6//XNOR gate
library ieee;
use ieee.std_logic_1164.all;

--------------------------------------

entity XNOR_ent is
port( x: in std_logic;
y: in std_logic;
F: out std_logic
);
end XNOR_ent;

---------------------------------------

architecture behv1 of XNOR_ent is


begin

process(x, y)
begin
-- compare to truth table
if (x/=y) then
F <= '0';
else
F <= '1';
end if;
end process;

end behv1;

architecture behv2 of XNOR_ent is


begin

F <= x xnor y;

end behv2;

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