consider the following statements: Operating Regions of SCR

specific features of BJT are Reverse Blocking Mode

1. Very small on-state resistance 1. Reverse bias is applied across anode
11. Presence of a second breakdown · and cathode, and SCR does not let the
111. Infinite input resistance current flow.
IV. Good performance in parallel operation
A l ... )
(A) I, II, Ill and IV (B) I, II and Ill
y
(C) 111 and IV (D) I and II p+
When compared with BJT, MOSFET have J1: RB
a lesser turn-off time, enabling them to
operate at high operating frequencies. n-
What is the reason that can be attributed
to that property?
(A) High input impedance of the MOSFET -- p
G
(B) Positive temperature coefficient of
the MOSFETs n+
(C) The absence of minority storage charge
in the MOSFETs !
(D) Smaller leakage current of MOSFETs
Fig. 1.52 Reverse Blocking Mode
Silicon Controlled Rectifier (SCR)
1. SCR is the oldest power electronic device 2. J 2 : FB but J 1 and J 3 : RB.
and has the highest power handling 3 . During reverse bias J 1 and J 3 block the
capability. flow of current.
2. It has 4 layers Of.J>!lell. ?'~c--:ta.. 4. J 1 has a drift layer (n-) on one side so
3. It can be turned ON by a control signal, it can block more reverse voltage' as
but cannot be turned OFF by a control compared to J 3 •
signal. 5. The reverse blocking capability of SCR
, Properties depends more on J, as com pared to J •
3
a) Semi controlled switch
Forward Blocking Mode
b) Btr;1olar and unidirection~l switch
1. SCR is forward biased (YAK > O) but curre nt
c) SOA, 1 st and 2nd gua....d.@Dt -
does not flow through SCR.
d) Minority carrier device
e) Available UQ to 10kY and 3 kY
AL.+) 1 1 IV

f) §__
.._
y
_u_it_a...;;b..:.:le::_:_:
fo:..:.r,-.:. h
:..:.:i.g:
gh~power
- and low f re -
quency application . p+
G
.r:::--+------. Cathode
K
p
n-
Gate W v
J2:_B8-)
-- p ov
p
G J3: FB f) V
Buffer
p' layer n+
- "D
A
Anode !
Fig. 1 51 (A) ST
. • icon Controlled Rectifier (SCR)
(B) Symbol of SCR
Fig. 1.53 Forward Blocking Mode

~ ¼ia-Mi'Gi•IHfus41. ,• wd tii\ib 1
 Role of Gate Current
2. J 1 and J 3 : FB but J 2 : RB. A
3. J is ~ gonsible.Jor blocking forwarq
2
y
voltage acro_s_s_S_CR. p+
4. Generally, SCR is designed such that its J1
forward blocking capability is the same as n-
reverse blocking capability (Symmetrical
SCR). EB EB EBEB EBEB
5. If forward voltage is increased abov~
J2 eeeeeee
tb!L.f9rward breakover vqitg.gg,__.J 2 break~ - p
down and SCR starts to conduct. G J3 n+
'
Forward Conduction Mode !
1. Once SCR starts to conduct, i.e., charges K
start to flow through SCR depletion layer Fig. 1.55 SCR w ithout Gate Current
gets removed .
1. We assume SCR is operating in fo rwa1
2. If the depletion layer _getuemoveJ;L_tj, e.n
1) blocking mode.
the voltage across SCR reduces. ( l
3. In this condition, all 3 junctions are 2. Now, if we apply gate current, then v.
forward biased, and the current th rough wish to know h ow does t he devic
the SCR is decided by an external operate.
circuit. 3. Before applying any gat e current, J 1 ari
4. SCR contains 2 BJT (pnp and npn) and B
J 3 are FB but J 2 is R_
when both BJT are ON (Saturation), then 4. Since J 3 is FB, e- enters from t he n• regio
SCR turns ON. to the p-region (majority carrier flow
where they become m inority charg
carriers.
5. Now, the electric field across J 2 sweep
these charge carriers (e-) into the dri1
layer, where they again become th
major_ i ty carrier.
6. Now, J 1 is forward biased so the m ajorit
carrier e- diffuses to the anode.
7. This way a small current exists betweer
anode and cathode called leakagE
current.
pf SC!l,_ 8. Now, when a positive voltage is applied
Fig. 1.54 Characteristics
between gate and cathode.
A

Holes
p'
t----,r----+-'e'------1 J ,
Already
Present

[operating Mode ll~WW

Reverse blocking RB FB RB

Forward blocking FB RB FB
K
Forward condition FB FB FB
Fig. 1.56 SCR with Gate current
 of J 3 , e- crossover A
9. oue to forward biasing
J from n• to p region. IA
3
10. Since n• is heavily doped, while p p•
is moderately doped, all e- cannot J,
recombine with holes so remaining e- are
n- n-
swept by E-field into n- layer.
J2 J2
11. These e- then cross J, (FB) and reach the
G
p p
anode.
IG J3
12. The charge carrier crossing the depletion
n•
layer reduce depletion width.
13. By application of gate pulse, more no.
of e- can reach the anode, and hence
now battery between anode and cathode
(B)
supplies more holes to compensate
these e-. Fig. 1.57 (A) SCR (B) Two Transistor Model of SCR
14. These holes cross J, and then E-field 1. By KCL
sweeps these holes into the gate region
IA+ lg = IK
(p), so the total number of holes increases
as holes from the gate and anode come For a BJT
into the gate region . le = alE + 1cao
15. To compensate for these holes more e- lcao: reverse saturation current of CB
are injected by the cathode layer into the junction
gate layer, so a regenerative process is A
set up.
16. Gate pulse must not be removed until the
anode current becomes equal to latching
after which this regenerative process will
continue.

Two Transistor Model

A

n Fig. 1.58 Circuit Diagram of Two Transistor Model

2. For Q,

p p 1c, = a,fA + 1cao

G For Q2
1c2 = a2IK + 1cao2

lc2 = 1a, = a2IK + 1ca02

le, = a,tA + 1cao,
K
le, + 1a, = IE, = IA
(A)
IA = a,tA + a 2 (1A + 19 ) + lceo, + 1ceo2
 II
circuit
Example 20: The SCR in the
40mA. A gateshOiir
a2/ ha s a lat ch ing cu rre nt of
I = g
SCR. The rna .Pu~i
A 1- a1 -a 2 of 50 µs is ap pli ed to the XifTlu
in O to en su re suc ces sful firin ~
va lue of R
By ap ply ing lg, la increases h
the SCR is _ _ _
3. For Si tra ns isto r, a
is ver y low bu t as IA
idly. SCR
increases a bu ild s up rap
a

+
IOOV

200mH

IE
Fig. 1.59 Graph bet wee n a and
increases and SCR
4. As approaches 1, IA
istance state,
goes int o the negative res
R gets triggered
wh ich is un sta ble , so SC So lut ion :
int o an ON sta te.
40mA = 100 + 100 (1 - e
-Yo,4)
increase, ( 1- a, - ai)
5. As /A increase, (a, + a 2 ) R 50 0
ses again.
decrease, hence IA increa
00
1 0
= ~ + 200mA(1 - e- · %.4 )
ses and fol low ing 40 mA
6. As lg is ap plie d 182 increa
le is established.
the po siti ve fee db ack cyc R = 6.0 6k0 .
le2 f -- + lc2 f -- + le, f -- + la
f
itch ing circuit i
Example 21: A thy ris tor sw

l lt
ers are fille d wit h
shown in the figure. The
thy ris tor is rated fc
a lat chi ng cur ren t of 10 mA
wit hin 5µs . Design the val
and is sw itch ed o
ue of res ista nc e R'.
7. Aft er SCR is ON, all lay
a sm all voltage
charge carriers. So SCR has IOmA
tio n increases,
drop. As , charge con cen tra
R ~ecrease then
co nd uc tivi ty (cr) increase,
(IR) decreases.
t: O.I H
Latching an d holding curren
above wh ich an
1. The mi nim um cu rrent 100V
sta te is cal led
SCR is lat ch ed int o the ON
as the lat ch ing cur ren t.
rre nt in SCR
a) Once the anode cu
t, the ga te
reaches the lat ch ing cur ren
pu lse can be removed. (A) 100k0.
es con t rol on ce
b) The gat e ter mi nal los (B) 20 k0
SCR is ON. (C) 30 k0
ode cu rre nt be low
2. The value of the an (D) 40 k0
cal led as the
which SCR tur ns OFF is
ho ldi ng cu rre nt. Solution:
an od e cu rrent
a) To t urn off a SCR, the SC R:O N
t he ho ldi ng
mu st be red uc ed below
di
cu rre nt. L- = 100
dt
3. IL = (1.3 to 3)/H

): ◄=1fiit4'i ---- . . ...,; ;..& :.1, 1-- .._. ..... .....

i
 i = 100 x t = 5 mA at 5~1sec 120
5mA = - t
0.1 0.3
/R = 10- 5 = 5mA 5mA
t = - - = 12.5 µsec
Example 22: Latching curr ent for an 400
SCR,
inserted in betw een a de voltage so_u Swi tchi ng cha rac teri stic s of SCR:
~ce of
2oov and the load is 100mA. The minimum
width of gate puls e curr ent required to
turn
on this SCR in cas e the load con sist
s of
R = 20 n in seri es with L = 0.2 H is _
_ µs .

ON state drop ,,, 1V

across SCR

0.2H
\
j

200V
I !
!
l , ,
\ -- Y
0.91A ......... ~ 1 • '
20n G tU
0.11A .....- .•
I i
. j
t l
~ ,rr ~
.
q I
l ' t gr ,
• 1 '

Solution:
Fig. 1.60 Swit chin g Characteristics of
SCR
i(t)= 2i ; ( 1-e-Yr )=o .1
Delay tim e (td):
10 ( 1- e-Yr ) = 0.1 1. It is the tim e bet wee n the inst
ant whe n
the gate cur ren t rea che s 90% of max
imu m
t = -tln 0.99 = 100.5µsec valu es, and whe n ano de cur ren t rea
che s
Example 23: For the circ uit sho wn 10% of max imu m valu e.
belo w if
the latching cur ren t of the SCR is 5mA 2. The role of gate cur ren t is
, the to cre ate
width of the gate puls e to be app lied a con duc tion are a in SCR from
for the whe re
SCR to turn ON is _ _ _µs. ano de cur ren t can flow.
3. Initially, gat e cha rge s can not
spre ad
thro ugh out dev ice flow s thro ugh a
sma ll
area .
di
4. Delay tim e dep end s on lg and
d; .
di
5. As I inc reas e or - 9 incr ease , t d dec
120V g dt reas e.

Rise tim e (t):

1. Tim e tak en by ano de cur ren t to incr
ease
from 10% to 90% of its fina l valu e.
2. It dep end s on the tim e conS t ant
Solution: of th e
di load .
L- = 120 3. If t is high, t, is also high.
dt
. 120 4 . If r = ~ = low, \ also low
l = -t
L 5. Dur in: this tim e V AK red uce s from
90% to
10%.
 Spread time (t.): Thyristor Triggering Methods
1. Tim e ta ke n by charge carriers to spread Forward voltage triggering:
t h ro u gh o ut the device is called spread
1. Under forward blocking mode .
t im e . . . , Ju ncr
J 2 Is reverse biased, while J and J 10
1
2. It d e p e nd s on the structure of the device forward biased. 1 ar
b ec au se if gate charges spread throughout
2. If forward voltage then J breaks d
the d evice, then anode current can also 2 0\'/1
and SCR enters forward cond uctio
flow throughout the device.
mode.
di 3. This method is not recommended as
3 . De lay tim e : I and _ 9
e dt can damage the device.
4 . Ri se time : • Load
5. Spread time: construction Gate triggering:
1. We have already seen that by applicatio
Turn off time (tq): of gate current a regenerative process
1. To turn OFF a SCR, we reduced the anode set up, which keeps on increasing anod
current below the holding current, and current.
then SCR is kept reverse biased till stored 2. Once the anode current reaches th
charges can be removed . latching current, the gate pulse may t
2. Turn OFF time is considered once anode removed.
current goes below holding current or 3. The minimum width of gate pulse requ ire
reaches zero. depends on the latching current.
3. During reverse recovery time negative 4. If continuous gate current is applied
anode current flows, which removes causes large power dissipation.
stored charge carriers from J , and J 3 5. Therefore, it is preferable to use a puls
(outer junctions). gate signal.
4. t (gate recovery time): During this time lg
sgt ored charges from the inner junction or
near to gate are removed.
s. Device turn OFF time, t 0 = t ,, + r9 , .
6 . If the device is not RB for at least tq then
stored charges are not removed and they
can act as gate current in the next cycle T t
when SCR is forward biased, which may Fig. 1.61 Pulse Gate Signal
trigger the SCR, so SCR loses its forward
blocking capability. T1 ~ minimum pulse width
T .
7. In order to safely commutate SCR, we Duty cycle, 8 =; mark-to-space ratio
reverse bias SCR for a duration of more
than t q.
a. The time for which SCR gets revers_e
(MSR) = (_l_J
T-T,
= ToN
T OFF

b iased in a circuit is called as circuit 6. Generally triggering circuit is a low po;;;

turn-off time (tJ circuit, whereas the load between a~usr
tc = (SF)tq and cathode is high power, so th eY
SF = safety factor (usually 2) be isolated. r,1er
7. We make use of a 1:1 pulse tranSfor
9 _ t = (50 _ 100µs) converter grade SCR (rtrec)ti-
f ie r, ac voltage regulator cycloconve er . for this purpose. uaris·
8. To reduce the size of the pul~~e rrius1
10 _ t = 3 µ 5 _ 50µ s inverter grade SCR(Chopper
a°n d inverter) . former, a high-frequency gate P
be used. I
 2. Thi s light cause s a photoelec tric effect
and generat es e- hole pairs.
3. These charges trigger SCR, and they are
called as light- activated SCR (LASCR)
and are used in HVDC.
t 4. Multiple SCR can be triggered
simultane ously by th is method.
Fig.1.62 High-Frequency Gatex· Pulse
Example 24: Why SCR cannot be turned OFF
9. By use of a pulse transforme r, we can
by negative gate pulse?
trigger multiple SCR simultaneo usly.
Load Solution:
A A SCR can be divided into multiple SCR
connected in parallel. Out of these only one
has an external gate terminal.
Gate
Firing When gate pulse lg, is applied to T,, on anode
Circuit K current 11 is establishe d, and a part of this
current becomes gate current for T •
2
Fig. 1.63 Pulse Transformer A

dv/dt triggering: T, T2 T3 r. Ts T6 P'

1. During forward blocking mode, J is
2
reverse biased so a depletion layer exists
! n-
across J 2 and opposite charges exist on
1, 12
~
13 1.
! 15 16
both sides, so it behaves as a capacitor.
p
2. The capacitanc e across a reverse biased 10J I~
pn junction is called junction capacitanc e
n
(Ci).
3. A charging current le = C. dv flows through K
' dt
the capacitor, which if more than the Similarly, lg2 establishe s 12 , which supplies lg:i
latching current can trigger an SCR. which will establish 1 and so on.
3
4. If the voltage across SCR is varied rapidly,
dv The gate becomes increasing ly ineffective as
or dt = high SCR may get triggered. more sections of the SCR get triggered.
5. This is an undesirabl e method of Since the gate terminal is not connected
triggering. directly to all sections of SCR, it cannot t urn
Thermal triggering: OFF an SCR.

1. By increasing the temperatu re near the Protection of SCR

gate region, bonds are broken so e- and The reliable operation of SCR requires that
holes are generated .
SCR is effectively protected, and ratings are
2. The holes in the gate region can act like not exceeded.
gate current to trigger SCR.
1. Overcurre nt protection
3. Th is method can thermally damage the di .
device so it is undesirabl e. 2. - protection
dt .
3. overvoltag e protection
Light triggering:
4 . Thermal protection
1. The pulse of light of appropriat e wave - dv .
5. - protection
length is guided by optical fibres and dt .
irradiated on the gate region . 6. gate protectio n
•• Overcurrent protection:
l& R

Main fuse

L
Cro~
th::, Gate trigger
circuit
Power
Convertor
0
A
D
V
Current
sensing resistor

Fig. 1.63 Over Current Protection

1. In case of high current, the devices inside

the power converter may get damaged
(BJT, IGBT etc). Fig. 1.64 V-1 Characteristics of Metal Oxide Varistor

2. If I = high, the voltage across the resistor

is also high, due to which the gate trigger
-di protect·,on:
dt
circuit triggers the crowbar thyristor. 1. When the gate signal is applied anod1
3 . This SCR short circuits supply and do not current begins to flow near the gat,
let high current reach the power converter. terminal.
4. SCR has a high surge current rating, i.e. 2. Current spreads throughout the devic1
it can tolerate high current for a short gradually. The thyristor design permit:
duration. the spread of current throughout t h1
5. Before SCR gets damaged, the main fuse device.
operates. 3. If ~= high, the current increase:
6. Crowbar protection: Shorting the supply more rapidly as compare d to sprea d'm i
dt
in case of fault. through the device, so the high current ii
concentrated near to gate.
Overvoltage protection: A
1. Overvoltage may be due to external
systems like surges in a transmission lnltlal T2 T3
conduction
system. Also may be due to internal area
reasons such as reverse recovery.
2. To avoid overvoltage, we connect a
non-linear resistor across SCR whose I i
resistance is high at low voltage, but n'
becomes low at a high voltage so acts as
a short circuit at high voltage.
K
3. This can be made from metal oxide.
Fig. 1.65 Spreading of Gate Current
4. In case of overvoltage high current flows . a
through varistor, and it causes resistance 4 . . If thecurrent is concentrated in f
' 0
to reduce, so the voltage across SCR small area then it leads to formation
decreases. hotspots.
5. Therefore, the ~ value must be kept
d' dt
below the _ 1 rating of SCR.
dt 5 (11ail
6 . This can be done by use of a
inductor in series with SCR ds
t sprea
7. The rate at which curren the
throughout the device depe~
inds on ,. J
 .
initial conductio n area. so to . prevent 11 . The highest ~rating can be obtained by
hotspot formation we need to increase dt
the initial conduction area. the use of an inte rdig itate d gate cathode
8. Higher gate current: At the st~r t of stru ctur e. The cost of such a stru ctur e
t_urn is .
ON, if a higher gate curr ent 1s appl high.
ied,
turned ON area of the cathode .surface
must be more for handling higher gate
current. So, the initia l conduction area
000
increases.
9. Structural modification of device:
cathode conduction area can also be
obtained by modifying the geometry of
Higher 000
the gate cathode.

p'
Anode 000
Fig. 1.68 Integ rated Gate Cathode Struc
ture
dv .
- protectio n:
dt
1. At a high value of dv , SCR may trigg
er
. dt
Cathode undesirably whic h was desc ribe d in the
previous sect ion.
2. Such trigg erin g mus t be avoided.

3. The rate of rise of anode volta ge dv

mus t
dv dt
be kep t belo w the - ratin g of the devi
ce.
dt
~ --- +- Initial conduction 4. A snu bbe r circ uit is used to prot
ect
area
against high dv .
. dt
5. During forw ard bloc king mode, junc tion
J
Fig. 1.66 Side Gated SCR is RB, so behaves as junc tion capa citan 2
ce
C..
. In centre gated SCR initia l cond uctio J

area increases. So
dt .
(~l
increases.
n 6. For V > 0, diod e ON, Rs: bypassed.

Anode rating + R
p·

V
p

77"~ ~-++ <W.. --, Cathode

dv .
Fig. 1.69 - Prote ction
dt

~--4- lnltlel conduction

area
C = Cs+ Cj

VT =V (1- e - t /r ); r = RC
dvT V - t/ r
-=- e
Fig. 1.67 Cent re Gate d SCR dt r

1·M¾Mi•lt4¥- 0 :;;:}@ii
 ~1
dt
mlU
=V
r
[t =O]
c) S w itc hin g lo s s
d) Gate triggering loss
3 . At low frequen cy, c onduction los
10
the major part of t otal loss. s r
V ( dv I 4 . If the heat produce d is t he s ame a
RC $ ~ dt ),011no dissipated, then the tem pe ratu re ~t
So, we obtain a series RC circuit device remains cons t a nt.
7. Cs gets fully charged to supply voltage V. 5. Thermal energy or h eat flows frorr
8. Now when SCR is triggered C5 discharges region of higher tempe rature to loi
through Rs and SCR (diode: OFF). temperature just like curre nt flows fo
high V to low V.
R5 : Limits max discharging current
6. The analogy between th e rm a l and el(
V
Idis < / ⇒ - < / ·• R1 = ? trical quantities
- m llJC R - m tuc •

• Temperature ➔ Voltage
9. When dealing with questions, assume at
Power ➔ c urrent
t = 0, C and L are discharged .
Thermal resistance ➔ e lectrica
C: Short Circuit L: Open Circuit
resistanc
10. In the previous circuit, at t = 0, C: Short
Circuit 7. Thermal resistance = _ f_ °C / w
KA
I=V K: Thermal conductivity
R .........
tti'f

Cdv V
0 P.,
-- = -
dt R /r, Jr,
dvl __v
dt m a, RC Fig. 1.70 Flow of Thermal Energy

Gate protection: (T1 - T2 ) = P0 , 0

1. Gate current must be limited to a value 0Jc: Junction to case
less than the maximum permissible value.
Des : Case to sink
Ig(min) < Ig < Ig(maJ<)
OSA: Sink to ambient (atmosphere)
2. This can be done by the use of series Pav
resistance in the gate circuit. • +M•+ '.♦M ..............

3. Gate voltage must also be kept less than

a max value and this is done by means of
a Zener diode.
4. The gate terminal must be protected against Fig. 1.71 Heat Flow from Junction to Atmosphere
noise signals to prevent false triggering. Equivalent thermal resistance:
5. This is done by the use of a filter. Over currenl Snubber Clrcul
" DI/di l\,ducl or __l
Thermal protection: C.B
1. The temperature of the device should not R,
-- - - - ·-·-·- -·- -·--·
J
Supply
exceed the maximum permissible value
R,
to protect the SCR. SCR
R,
z.o
2 . Various power losses in SCR
a) Forward conduction loss ----r
b) Leakage current loss Gel o prol octlon

Fig. 1.72 All Protection Schemot ln1ldo scR •

~ fft!if. .
Example 25: A thyristor carrying full load dv .
2. dt Rating: Maximum allowable value
current has an allowable case tem~erat~re
of 1300c , the maximum allowable J~nct1on of dv above which SCR gets triggered
temperature is 1500c . Thermal res1sta_ dt
nce
between case to ambient and sink to ambient without applying gate current.
are 0.6°C/W and 0.5°C/W respectively. The If dv > ( ddv ) : false triggering
sink temperature for an ambient of 50°C is dt t rating
oc?
------ 3. Finger voltage: Minimum value of the
thermal forward voltage between
Solution:
anode and cathode for turn ON by gate
Tj = 150°C triggering.
TC = 130°C 4. Average ON state current: When SCR is
TA= 50°C ON, there is a voltage drop across SCR
0CA = 0.6° C/W so power loss in the SCR is given by
0SA = 0.5° C/W p = VON/avg ,

50 The maximum value of the average

p = Tc - TA = Tc - TA = 130 - = 133.33W current that can be tolerated by SCR
av 0CA eCS + eSA 0.6
gives an average ON state current rating.
T - T T - T I
Also p = _c_
1
_s = c s / = rms
av eCS eCA - eAS av FF
130 - T5 5. RMS ON state current: Maximum value
133.33 =
0.6-0.5 of rms current that can be tolerated by
⇒ T5 = 130 - (133.33 x 0.1) = 116.667° C SCR.

Example 26: A thyristor has an internal 6. di rating: Maximum allowable value

power dissipation of 40W and is operated dt di
of dt above which the current does not
at an ambient temperatur e of 20°C if
thermal resistance is 1.6°C/W, the junction spread at fast enough speed leading to
temperature is? the formation of local hotspots.
(A) 114°C
(C) 94°C
(B) 164°C
(D) 84°C
dt
d' (d')
If - > -
1

dt
1

rating
: local hotspot

Solution: (D) 7. Surge current rating:

Given: a) An SCR can handle a very large amount
TA= 20°C of current for a short duration of t ime.
0i4 = 1.6°C/W b) As the duration increases, current
T. - T
handling capability reduces.
p =_J_ _A
c) The heat produced in SCR must not
e }A
exceed the J2rt ~ thermal limit.
- 20T thermal limit
⇒ 40 = -''1- - -
1.6 d) I2t = constant, i.e. I2t must not exceed
TI = 84° a certain value.
e) One cycle surge current rating is the
Thyristor Ratings peak valu e of a non- recurring ~alf
cycle of a sine w ave of 10 ms duration
1- Vr - ON
state drop: When SCR cond ucts
of 50 Hz.
a drop between anode and cathode is f) For sub-cycle surge current rating.
called an ON State Drop.

Semiconductor Devices ~, ~