University of Basra - Collage of Engineering Microprocessor Interface (CoE 335) 3m Year - Computer Engineering Dpt. 82C37A PROGRAMMABLE DIRECT MEMORY ACCESS CONTROLLER The 82C37A is the LSI controller IC that is widely used to implement the direct memory access (DMA) function in 8088- and 8086-based microcomputer systems. DMA capabil- ity permits devices, such as peripherals, to perform high-speed data transfers between either two sections of memory or between memory and an I/O device. In a microcom- puter system, the memory or I/O bus cycles initiated as part of a DMA transfer are not performed by the MPU; i DMA con- troller, such as the 82C37A,‘The DMA mode of operation is frequently used when blocks or packets of data are to be transferred. For instance, disk controllers, local area network controllers, and communication controllers are devices that normally process data as blocks or packets. A single 82C37A supports up to four peripheral devices for DMA operation. Microprocessor Interface of the 82C37A A block diagram that shows the interface signals of the 82C37A DMA controller is given in Fig. 10-40(@). The pin layout in Fig. 10-40(b) identifies the pins at which these signals are available. Let us now look briefly at the operation of the microprocessor inter- face of the 82C37A. - In a microcomputer system, the 82C37A acts as a peripheral controller device, and its operation must be initialized through software. This is done by reading from or writ- ing into the bits of its internal registers. These data transfers take place through its micro- processor itttcrface. Figure 10-41 shows how the 8088 connects to the 82C37A’s micro- processor interface. Whenever the 82C37A is not in use by a peripheral device for DMA operation, it is in a state known as the idle state, When in this state, the microprocessor can issue com- mands to the DMA controller and read from or write to its internal registers. Data bus lines DBy through DB, form the path over which these data transfers take place. Which register is accessed is determined by a 4-bit register address that is applied to address inputs Ag through A3. As Fig. 10-41 shows, address lines Ay through Aj of the micro- processor directly supply these inputs. J During the data-transfer bus cycle, other bits of the address are decoded in exter- nal circuitry to produce a chip-select (GS) input for the 82C37A. When in the idle state, the 82C37A continuously samples this input, waiting for it to become active. Logic 0 at this input enables the microprocessor interface.'The microprocessor tells the 82C37A whether an input or output bus cycle is in progress with the signal [OR or IOW, respec- tively. In this way, we see that the 82C37A maps into the I/O address spacc of the 8088 microcomputer, Prepared By: Dr. Mohammed Al-IbadiUniversity of Basra - Collage of Engineering Microprocessor Interface (CoE 335) 3rd Year - Computer Engineering Dpt. LENG v Ves Zo ky \'o ie I cly deli wer DMA handshake signals pray pao, clibey jaw 82037A ton > DACK,-DACK; iow a is = = be ws Figure 10-40 (a) Block diagram of the 82C37A DMA controller. (b) Pin layout (Reprinted by permission of Intel Corporation. Copytight/Intel Corp. 1987) : & bite address” AAs AeAg Address Latch 20370 ee ee Doe pe, TOR jE) controt logic iow Figure 10-41 Microprocessor interface of 82C37A to the 8088, Prepared By: Dr. Mohammed Al-IbadiUniversity of Basra - Collage of Engineering Microprocessor Interface (CoE 335) 3! Year - Computer Engineering Dpt- DMA Interface of the 82C37A Now that we have described how a microprocessor talks to the registers of the 82C37A, let us continue by looking at how petipheral devices initiate DMA service. The 82C37A contains four independent DMA channels, channels 0 through 3. Typically, each of these channels is dedicated to a specific peripheral device. Figure 10-42 shows that the device has four DMA request inputs, denoted as DREQo through DREQ,. These DREQ inputs cortespond to channels 0 through 3, respectively. In the idle state, the 82C37A continuously tests these inputs to see if one is active. When a peripheral device wants to perform DMA operations, it makes a request for service at its DREQ input by switching it to logic 1. . In response to the active DMA request, the DMA controller switches the hold request (HRQ) output to logic 1. Normally, this output is supplied to the HOLD input of the 8088 and signals the microprocessor that the DMA controller needs to take control of the system bus. When the 8088 is ready to give up control of the bus, it puts its bus signals into the high-impedance state and signals this fact to the 82C37A by switching the HLDA (hold- acknowledge) output to logic 1. HLDA of the 8088 is applied to the HLDA input of the 82C37A and signals that the system bus is now available for use by the DMA controller, When the 82C37A has control of the system bus, it tells the requesting peripheral device that it is ready by outputting a DMA-acknowledge (DACK) signal. Note in Fig. 10-42 that each of the four DMA request inputs, DREQ, through DREQ, has a corresponding DMA-acknowledge output, DACKo through DACKs. Once this DMA- request/acknowledge handshake sequence 1s complete, the peripheral device gets direct access to the system bus and memory under control of the 82C37A. ; During DMA bus cycles, the DMA controller, not the MPU, drives the system bus. The 82C37A generates the address and all control signals needed to Perform the een) or I/O data transfers. At the beginning of all DMA bus cycles, a 16-bit address is output on lines Ap through A; and DBp through DB. The upper 8 bits of the address, available Prepared By: Dr. Mohammed Al-IbadiUniversity of Basra - Collage of Engineering Microprocessor Interface (CoE 335) 3 Year - Computer Engineering Dpt. on the data bus lines, appear at the same time that address strobe (ADSTB) becomes active. Thus, ADSTB is intended to be used to strobe the most significant byte of the address into an external address latch. This 16-bit address gives the 82C37A the ability to directly address up to 64Kbytes of storage locations. The address enable (AEN) output signal is active during the complete DMA bus cycle and can be used to both enable the address latch and disable other devices connected to the bus, Let us assume for now that an I/O peripheral device is to transfer data to memory— that is, the I/O device wants to write data to memory. In this case, the 82C37A uses the JOR output to signal the 1/0 device to put the data onto data bus lines DBg through DB,. At the same time, it asserts MEMW to signal that the data available on the bus are to be written into memory, In this case, the data are transferred directly from the 1/O device to memory and do not go through the 82C37A, In a similar way, DMA transfers of data can take place from memory to an I/O device. In this case, the I/O device reads data from memory and outputs it to the periph- eral. For this data transfer, the 82C37A, activates the MEMR and IOW control signals, The 82C37A performs both the memory-to-/O and I/O-to-memory DMA bus cycles in just four clock periods, The duration of these clock periods is determined by the frequency of the clock signal applied to the CLOCK input, For instance, at 5 MHz the clock period is 200 ns and the bus cycle takes 800 ns. The 82C37A is also capable of performing memory-to-memory DMA transfers. In such a data transfer, both the MEMR and MEMW signals are utilized. Unlike the 1/0- to-memory operation, this memory-to-memory data transfer takes eight clock cycles, ‘This is because it is actually performed as a Separate four-clock read bus cycle from the Source memory location to a temporary register within the 82C37A and then another four- Clock write bus cycle from the temporary register to the destination memory location. At 5 MHz, a memory-to-memory DMA cycle takes 1.6 Ls. The READY input is used to accommodate slow memory or I/O devices, READY must go active, logic 1, before the 82C37A will complete a memory or I/O bus cycle. As long as READY is at logic 0, wait states are inserted to extend the duration of the current bus cycle. Prepared By: Dr. Mohammed Al-IbadiUniversity of Basra - Collage of Engineering Microprocessor Interface (CoE 335) 34 Year - Computer Engineering Dpt. ‘aie peal rat Dates ‘eancecve ‘contol 1} ty tt mm 4 Ko Ko “He Ke ga Kaj UU ‘Larehviogic stenny Z =i Bile = se BIA DACK, PROG| | elge Lu owe 10-42 DMA rie 90 ieee | os 1 Celene es des Each DMA channel has two address registers: the base address register and the current address register. The base address register holds the starting address for the DMA. operation, and the current address register contains the address of the next storage loca- tion to be accessed. Writing a value to the base address register automatically loads the same value into the current address register. In this way, we see that initially the current address register points to the starting I/O or memory address. These registers must be loaded with appropriate values prior to initiating a DMA cycle. To load a new 16-bit address into the base register, we must write two separate bytes, one after the other, to the address of the register. ‘The 82C37A also has two word-count registers for each of its DMA channels: the base count register and the current count register The number of bytes of data to be tran- sferred during a DMA operation is Specified by the value in the base word-count resister. At any time during the DMA cycle, the value in the current word-count register tells how many bytes remain to be transferred. Prepared By: Dr. Mohammed Al-IbadiUniversity of Basra - Collage of Engineering Microprocessor Interface (CoE 335) 34 Year - Computer Engineering Dpt. SERIAL COMMUNICATIONS INTERFACE Another type of I/O interface that is widely used in microcomputer systems is known as a serial communication port. This is the type of interface that is commonly used to con- nect peripheral units, such as CRT terminals, modems, and printers, to a microcomputer. It permits data to be transferred between two units using just two data lines. One line is used for transmitting data and the other for receiving data. For instance, data input at the keyboard of a terminal are passed to the MPU part of the microcomputer through this type of interface. Let us now look into the two different types of serial interfaces that are implemented in microcomputer systems. Synchronous and Asynchronous Data Communications ‘Two types of serial data communications are widely used in microcomputer sys- tems: asynchronous communications and synchronous communications. By synchronous, we mean that the receiver and transmitter sections of the two pieces of equipment com- municating with each-other must run synchronously. For this reason, as shown in Fig. 10-52(a), the interface includes a Clock line as well as Transmit data, Receive data, and Signal common lines. It is the clock signal that synchronizes both the transmission and reception of data. ‘The format used for synchronous communication of data is shown in Fig. 10-52(b). ‘To initiate synchronous transmission, the transmitter first sends out synchronization char- acters to the receiver. The receiver reads the synchronization bit pattern and compares it to a known sync pattern. Once they are identified as being the same, the receiver begins to read character data off the data line. Transfer of data continues until the complete block of data is received. If large blocks of data are being sent, the synchronization characters ‘Tronemit data Receive dats System 1 ‘Clock System 2 Signal common @ Date S¥N SYN CHAR #2 CHAR #1 co) Figure 10-52 (a) Synchronous communications interface. (b) Synchronous data-transmission format. Prepared By: Dr. Mohammed Al-IbadiUniversity of Basra - Collage of Engineering Microprocessor Interface (CoE 335) 34 Year - Computer Engineering Dpt. may be periodically resent to assure that synchronization is maintained. The synchronous type of communications is typically used in applications where high-speed data transfer is required. ‘The asynchronous method of communications eliminates the need for the Clock ignal. As shown in Fig. 10-53(a), the simplest form of an asynchronous communication interface could consist of a Receive data, Transmit data, and Signal common communi, cation lines. In this case, the data to be transmitted are sent out one character at a time, and at the receiver examining synchronization bits that are included at the beginning and end of each character performs end of the communication line synchronization, ‘The format of a typical asynchronous character is shown in Fig. 10-53(b). Here we see that the synchronization bit at the beginning of the character is called the start bit, and that at the end of the character the stop bit. Depending on the communications scheme, 1, 1%, or 2 stop bits can be used. The bits of the character are embedded between the start and stop bits. Notice that the start bit is either input or output first. The LSB of the char- acter, the rest of the character’s bits, a parity bit, and the stop bits follow it in the serial bit stream. For instance, 7-bit ASCII can be used and parity added as an eighth bit for higher reliability in transmission. The duration of each bit in the format is called a bit time. ‘The fact that a 0 or 1 logic level is being transferred over the communication line is identified by whether the voltage level on the line corresponds to that of a space or a mark, respectively. The start bit is always to the space level. It synchronizes the receiver to the transmitter and signals that the unit receiving data should start assembling the char- Transmit data Receive data System 1 Signal common. ‘System 2 @ MsB l ® any Sly) Go Figure 10-53 (a) Asynchronous communications interface. (b) Asynchronous data-transmission format. Prepared By: Dr. Mohammed Al-IbadiUniversity of Basra - Collage of Engineering Microprocessor Interface (CoE 335) 3! Year - Computer Engineering Dpt. oe See) ee are to the mark level. The nontransmitting line is always at the space logic level. This scheme assures that the receiving unit sees a transition of logic level at the start bit of the next character. Simplex, Half-Duplex, and Full-Duplex Communication Links Applications require different types of asynchronous links to be implemented. For instance, the communication link needed to connect a printer to a microcomputer just needs to support communications in one direction. That is, the printer is an output-only device; therefore, the MPU needs only to transmit data to the printer. Data are not trans- mitted back. In this case, as shown in Fig. 10-54(a), a single unidirectional communi- cation line can be used to connect the printer and microcomputer together. This type of connection is known as a simplex communication link. ‘Other devices, such as the CRT terminal with keyboard shown in Fig. 10-54(b), need to both transmit data to and receive data from the MPU. That is, they must both input and output data. Setting up a half-duplex communication link can also satisfy this requirement with a single communication line. In a half-duplex link, data are transmitted and received over the same line; therefore, transmission and reception of data cannot take place at the same time. If higher-performance communication is required, separate transmit and receive ines can be used to connect the peripheral and microcomputer. When this is done, data can be transferred in both directions at the same time. This type of link, illustrated in Fig. 10-54(c), is called a full-duplex communication link. Ei —— Microcomputer ——_—_—_—— @ i a am Printer asamc] RS-232¢| (Receive line, i) cet anemic tie, PE] cer, Microcomputer ecrive Hine 3) oun 4 Receive 2 ermtna | Figure 10-54 (a) Simplex communication link. (b) Half-duplex ‘communication link. (¢) Full-duplex communication link. Prepared By: Dr. Mohammed Al-IbadiUniversity of Basra - Collage of Engineering Microprocessor Interface (CoE 335) Baud Rate and the Baud-Rate Generator The rate at which data transfers take place over the receive and transmit lines ig known as the baud rate. By baud rate we mean the number of bits of data transferred per second. For instance, some of the common data transfer rates are 300 baud, 1200 bad and 9600 baud. They correspond to 300 bits/sccond (bps), 1200 bps, and 9600 bps, respectively. Baud rate is set by a part of the serial communication interface called the baud-rate generator. The baud rate at which data are transferred determines the bit time—that is, the amount of time each bit of data is on the communication line. At 300 baud, the bit time is found to be ter = 1/300 bps = 3.33 ms (atl st 0.223) = oS ee The data transfer across an asynchronous serial data communications line is observed and the bit time is measured as 0.833 ms. What is the baud rate? Solution Baud rate is calculated from the bit time as Baud rate = I/tgr = 1/0.833 ms = 1200 bps The RS-232C Interface ‘The RS-232C interface is a standard hardware interface for implementing asyn- chronous serial data communication ports on devices such as printers, CRT terminals, keyboards, and modems. The Electronic Industries Association (EIA) defines the pin definitions aria electrical characteristics of this interface. The aim behind publishing standards, such as the RS-232C, is to assure compatibility between equipment made by different manufacturers. Peripherals that connect to a microcomputer can be located within the systems or anywhere from several feet to many feet way. For instance, in large systems it is common to have the microcomputer part of the system in a separate room from the terminals and printers. This leads us to the main advantage of using a serial interface to connect peri- Pherals to a microcomputer, which is that as few as three signal lines can be used to con- nect the peripheral to the MPU: a receive-data line, a transmit-data line, and signal common. This results in a large savings in wiring costs, and the small number of lines that need (0 be put in place also leads to higher reliability. Prepared By: Dr. Mohammed Al-IbadiUniversity of Basra - Collage of Engineering Microprocessor Interface (CoE 335) 3r Year - Computer Engineering Dpt. PROGRAMMABLE COMMUNICATION INTERFACE CONTROLLERS poceeeay Communication interfaces are so widely used in modern electronic equip- pentane peripheral devices have been developed to permit cusy implementation ese types of interfaces. For instance, an RS-232C port is the type of interface needed to connect a CRT terminal or a modem to a microcomputer. To support connection of these two peripheral devices, the microcomputer would need two independent RS-232C 1/0 ports. This function is normally implemented with a programmable communication controller known as a universal synchronous/asynchronous receiver transmitter (USART). As the name implies, a USART is capable of implementing either an asynchronou: synchronous communication interface. Here we will concentrate on its use in implement- ing an asynchronous communication interface. ‘The programmability of the USART provides for a very flexible asynchronous com- munication interface. ‘Typically, it contains a full-duplex receiver and transmitter, which can be configured through software for communication of data using formats with charac- ter lengths between 5 and 8 bits, with even or odd parity, and with 1, 1%, or 2 stop bits. ‘A USART has the ability to automatically check characters during data reception to detect the occurrence of parity, framing, and overrun errors. A framing error means that after the detection of the beginning of a character with a start bit the appropriate number of stop bits were not detected. This means that the character that was transmitted was not received correctly and should be resent. An overrun error means that the prior character that was received was not read out of the USART’s receive data register by the micro- processor before another character was received. Therefore, the first character was lost and should be retransmitted. 8251A USART A block diagram showing the internal architecture of the 8251A is shown in Fig. 10-57(a) and its pin layout in Fig. 10-57(b). From this diagram we find that it includes four key sections: the bus interface section, which consists of the data bus buffer and read/write control logic blocks; the transmit section, which consists of the transmit buffer and transmit control blocks; the receive section, which consists of the receive buffer and receive-control blocks; and the modem-control section. Let us now look at cach of these sections in more detail ‘A UART cannot stand alone in a communication system; its operation must typi- cally be controlled by a microprocessor. The bus interface section is used to connect the 8251A to a microprocessor such as the 8086. Note that the interface includes an 8-bit bidirectional data bus Do through D, driven by the data bus buffer. It is over these lines that the microprocessor transfers commands to the 8251A, reads its status register, and inputs or outputs character data. se pa Data transfers over the bus are controlled by the signals C/D (controt/data), RD (read), WR (write), and CS (chip select), all inputs to the read/write control logic section. ‘Typically, the 8251A is located at a specific address in the microcomputer’s I/O or mem- ory address space. When the microprocessor is to access registers within the 8251A, it puts this address on the address bus. The address is decoded by external circuitry and must produce logic 0 at the CS input for a read or write bus cycle to take place to the 1A. ‘The other three control signals, C/D, RD. and WR, tell the 8251A what type of data wansfer is to take place over the bus. Figure 10-58 shows the various types of read/write perations that can occur. For example, the first state in the table, C/D = 0, RD = 0, and WR = 1, corresponds to a character data transfer from the 8251A to the microprocessor. Prepared By:University of Basra - Collage of Engineering Microprocessor Interface (CoE 335) serial Gh 3° Year - Computer Engineering Dpt. arene) > cpa-> Tfo = Tei op, She vale eo oe afr alo & o Jew W jo = I [omnes = = eee , a cocoa Read/write, end Ls | et Tosa = . oe von om ci RTS rs eee, = oR ask eset ™ “ten aes 2 a “sa Bo oy s ms dertle paral @ Tour i os me Inte a) LJ SYNDET/BD: = tng Jom mu _ [> smioer o Figure 10-57 (2) Block diagram of the 82S1A, ‘oration. Copyrighvints Corp. 1987), Corporation! Copyrighvstel Corp. » (Reprinted by permission of Intel Cor- Data bus Dats bus -+ 8251 Data ‘Status + Data bus : Data bus + Control Figure 10-58 Read/write operations. (Reprinted by permission of Intel Corporation. Copyright/Intel Corp. 1987) Data bus -» 3-State Data bus -> 3-State Note that in general RD = 0 signals that the microprocessor is reading data from the 8251A, WR = 0 indicates that data are being written into the 8251A, and the logic level of C/D indicates whether character data, control information, or status information is on the data bus. EXAMPLE 10.29 What type of data transfer is taking place over the bus if the control signals are at CS = 0, C/D = 1, RD = 0, and WR = 17 Solution Looking at the table in Fig. 10-58, we see that CS = 0 means that the 8251A’s data bus has been enabled for operation. Since C/D is 1 and RD is 0, status information is being read from the 8251A. ‘The receiver section is responsible for reading the serial bit stream of data at the Rxp (receive-data) input and converting it to parallel form. When a mark voltage level is detected on this line, indicating a start bit, the receiver enables a counter. As the counter increments to a value equal to one-half a bit time, the logic level at the Rx, line is sam. pled again. If it is still at the mark level, a valid start pulse has been detected. Then Rxp is examined every time the counter increments through another bit time. This continues until a complete character is assembled and the stop bit is read. After this, the complete character is transferred into the receive-data register. During reception of a character, the receiver automatically checks the character data for parity, framing, or overrun errors. If one of these conditions occurs, it is flagged by setting a bit in the status register. Then the Rxgpy (receiver ready) output is switched to the 1 logic level. This signal is sent to the microprocessor to tell it that a character is avail- able and should be read from the receive-data register. Rxapy is automatically reset to logic 0 when the MPU reads the contents of the receive-data register, sonar the 8251 does not have a built-in baud-rate generator. For this reason, the clock Signal that is used to set the baud rate must be externally generated and applied to the key input of the receiver. Through software the 8251A can be set up to internally divide wee clock signal input at Rxc by 1, 16, or 64 to obtain the desired baud rate, © a) Prepared By: Dr. Mohammed Al-IbadiUniversity of Basra - Collage of Engineering . Microprocessor Interface (CoE 335) 3d Year ~ Computer Engineering Dpt, The transmitter does the opposite of the receiver section. It receives paralle] char acter data from the MPU over the data bus. The character is then automatically frame with the start bit, appropriate parity bit, and the correct number of stop bits and Ut into the transmit data buffer register. Finally, it is shifted out of this register to produce abit. serial output on the Txp line. When the transmit data buffer register is empty, the Trapy output switches to logic 1. This signal can be returned to the MPU to tell it that ano character should be output to the transmitter section. When the MPU writes another char: acter out to the transmitter buffer register, the Txppy output resets. Data are output on the transmit line at the baud rate set by the external transmitter clock signal that is input at Txc. In most applications, the transmitter and receiver Te ate at the same baud rate. Therefore, the same baud-rate generator supplies both Rx and Txo. : The 8251A UART, just like the other peripheral ICs discussed earlier in the chapter, can be configured for various modes of operation through software. Its operation is con- trolled through the setting of bits in three internal control registers: the mode-control reg- ister, command register, and the status register. For instance, the way in which the 8251A’s receiver and transmitter works is determined by the contents of the mode control register. Figure 10-60 shows the organization of the mode control register and the function of each of its bits. Note that the two least significant bits B, and Bz determine whether the device operates as an asynchronous or synchronous communication controller and in asynchronous mode how the external baud rate clock is divided within the 8251A. For example, if these two bits are 11, it is set for asynchronous operation with divide-by-64 for the baud-rate input. The two bits that follow these, L, and L,, set the length of the character. For instance, when information is being transmitted and received as 7-bit ASCTI characters, these bits should be loaded with 10. The next two bits, PEN and EP, determine whether parity is in use and, if so, ~ whether it is even parity or odd parity. Looking at Fig. 10-60, we see that PEN enables or disables parity. To enable parity, it is set to 1. Furthermore, when parity is enabled, logic 0 in EP selects odd parity, or logic 1 in this position selects even parity. To disable parity, all we need to do is reset PEN. ‘We will assume that the 8251A is working in the asynchronous mode; therefore, bits S, and S, determine the number of stop bits. Note that if 11 is loaded into these bit positions, the character is transmitted with 2 stop bits. Prepared By: Dr. Mohammed Al-IbadiUniversity of Basra - Collage of Engineering Microprocessor Interface (CoE 335) 34 Year - Computer Engineering Dpt. Dr Ds Ds Ds Ds Dp Dy Dy S. |S: | ep [PEN | t | ty | B | By | Baud Rate Select 4-Patity enable a; -Dise ‘Gharacter Stopbit oar Selection Selection { Invaiid] 0 | 0 o | o | seis 0 | 0 | synch. Mode toe) 0 1 1 | seen o} 1 | 6Bks o | 4 | 4XAsynch ten} 4 | 0 | parity 1] 0 | 7Bits 1 | 0 | 16xAsynch 2 0-0¢d 2bis} a | 1 | Parity 1] 4 | seis 1] 1 | 64xasynen ten N.B.—Stop bit selection as above is only for transmitlr, Receiver never requires a more than one stop bit ys cleck Fig. 10.60 Mode instruction Format Asynchronous Mode LH EXAMPLE 10.30 What value must be written into the mode-control register in order to configure the 8251A, such that it works as an asynchronous communications controller with the baud:-rate-clock internally divided by 16? Character size is to be 8 bits; parity is odd; and one stop bit is used. Solution From Fig. 10-60, we find that B2B, must be set to 10 in order to select asynchronous operation with divide-by-16 for the external baud clock input. BB, = 1 To select a character length of 8 bits, the next 2 bits are both made logic 1. ‘This gives Lak, = 11 To set up odd parity, EP and PEN must be made equal to 0 and 1, respectively. EP PEN = 01 Finally, $2, are set to O1 for one stop bit. S281 Therefore, the complete control word is Prepared By: Dr. Mohammed Al-Ibadi