Chapter 07 – RISC

Prepared By:
BIJAY MISHRA
(बिजय मिश्र)
[email protected]
@jijibisha
Chapter 7 - RISC 8 Hrs.

7.1 RISC and CISC Systems

7.2 RISC Instructions
7.3 Processor to Memory Movement
7.4 Pipelining with RISC
7.5 RISC and Cache
COMPLEX INSTRUCTION SET COMPUTER (CISC)
• A computer with large no of instruction is classified as complex instruction
set computer (CISC).
• The basic reason to a design a complex instruction set is the need to
simplify the compilation and enhance the overall computer efficiency.
• The essential goal of a CISC architecture is to attempt to provide a single
machine instruction for each statement that is written in a high-level
language.
• CISC has the ability to execute addressing modes or multi-step operations
within one instruction set.
• It is the design of the CPU where one instruction performs many low-level
operations.
• For example, memory storage, an arithmetic operation and loading from
memory.
Major Characteristics of CISC Architecture

1. Large no of instructions typically form hundred to 250 instructions.

2. Same instructions that perform specialized task and are used in
frequency.
3. A large variety of addressing modes typically form 2-50 different
modes.
4. Variable length instruction format.
5. Instruction that manipulate operands in main memory.
 CISC ARCHITECTURE
• The CISC approach attempts to minimize
the number of instructions per program,
sacrificing the number of cycles per
instruction.
• Computers based on the CISC architecture
are designed to decrease the memory
cost.
• Because, the large programs need more
storage, thus increasing the memory cost
and large memory becomes more
expensive.
• To solve these problems, the number of
instructions per program can be reduced
by embedding the number of operations
in a single instruction, thereby making the
instructions more complex.
 Example of CISC PROCESSORS

IBM 370/168 – It was introduced in the year 1970. CISC design is a 32 bit processor and
four 64-bit floating point registers.

VAX 11/780 – CISC design is a 32-bit processor and it supports many numbers of
addressing modes and machine instructions which is from Digital Equipment Corporation.

Intel 80486 – It was launched in the year 1989 and it is a CISC processor, which has
instructions varying lengths from 1 to 11 and it will have 235 instructions.
History of CISC
In the late 1950s, faced with the need to rationalize it's computer product
lines, IBM instituted a research program having the objective of creating a
range of software compatible computers that would also capture its existing
software investments. The result, introduced on April 7, 1964 was the
System/360, the first commercially available microprogrammed computer
architecture (later me known as complex instruction set computer, or CISC
architecture). The success of System/360 resulted in CISC architectures
dominating computer, and later microprocessor, design for two decades.

However, the ability to incorporate any instruction which could be

microprogrammed turned out to be a mixed blessing. During the mid-1970s,
improved performance measurement tools demonstrated that the execution
of most application programs on CISC-based systems was dominated by a few
simple instructions, and the complex ones were seldom used.
Why CISC ?
• Compiler simplification
• Disputed
• Complex machine instructions harder to exploit
• Optimization more difficult
• Faster programs
• Bias towards use of simpler instructions
• More complex control unit
• Microprogram control store larger
• thus simple instructions take longer to execute
• Smaller programs
• Program takes up less memory
• Memory is now cheap
• May not occupy less bits, just look shorter in symbolic form
• More instructions require longer op-codes
• Register references require fewer bits
CISC Advantages
At the time of their initial development, CISC machines used available
technologies to optimize computer performance.
• Microprogramniing is as easy as assembly language to implement, and
much less expensive than hardwiring a control unit.
• The ease of microcoding new instructions allowed designers to make CISC
machines upwardly compatible: a new computer could run the same
programs as earlier computers because the new computer would contain a
superset of the instructions of the earlier computers.
• As each instruction became more capable, fewer instructions could be used
to implement a given task. This made more efficient use of the relatively
slow main memory.
• Because microprogram instruction sets can be written to match the
constructs of high-level languages, the compiler does not have to be as
complicated.
CISC Disadvantages
Designers soon realised that the CISC philosophy had its own problems, including:
• Earlier generations of a processor family generally were contained as a subset in every
new version - so instruction set & chip hardware become more complex with each
generation of computers.
• So that as many instructions as possible could be stored in memory with the least
possible wasted space, individual instructions could be of almost any length - this means
that different instructions will take different amounts of clock time to execute, slowing
down the overall performance of the machine.
• Many specialized instructions aren't used frequently enough to justify their existence -
approximately 20% of the available instructions are used in a typical program.
• CISC instructions typically set the condition codes as a side effect of the instruction. Not
only does setting the condition codes take time, but programmers have to remember to
examine the condition code bits before a subsequent instruction changes them.
 REDUCED INSTRUCTION SET COMPUTER (RISC)
• The underlying philosophy of RISC machines is that a system is better able to
manage program execution when the program consists of only a few different
instructions that are the same length and require the same number of clock cycles
to decode and execute.
• In the early 1980’s a number of computer designers recommended that computer
use fewer instructions with a simple construct so they can be executed much faster
within the CPU without having to use memory as often. This type of computer is
classified as RISC.
• The concept of RISC architecture involves attempt to reduce execution time by
simplifying the instruction set of the computer.
• RISC is a CPU design strategy based on the insight that simplified instruction set
gives higher performance when combined with a microprocessor architecture
which has the ability to execute the instructions by using some microprocessor
cycles per instruction.
Major Characteristics of RISC Architecture
1. Relatively few instruction.
2. Relatively few addressing mode.
3. Memory access limited to load and store instruction.
4. All operations done within the register of CPU.
5. Fixed length, easily decoded instruction format.
6. Single cycle instruction execution.
7. Hard-wired rather than micro program control
8. A relatively large number of register in the processor unit.
9. Use of overlapped register windows to speed-up procedure call and return.
10. Efficient instruction pipeline.
11. Compiler support for efficient translation of high-level language programs into
machine language programs.
 RISC ARCHITECTURE
• RISC (Reduced Instruction Set Computer)
is used in portable devices due to its
power efficiency.
• For Example, Apple iPod and Nintendo DS.
• RISC is a type of microprocessor
architecture that uses highly-optimized set
of instructions.
• RISC does the opposite, reducing the
cycles per instruction at the cost of the
number of instructions per program
• Pipelining is one of the unique feature of
RISC.
• It is performed by overlapping the
execution of several instructions in a
pipeline fashion.
 Example of RISC PROCESSORS
• The PowerPC microprocessor (old Mac) , used in IBM's RISC System/6000
workstation and Macintosh computers, is a RISC microprocessor.

• CDC 6600, highly innovative supercomputer of the mid 1960s

• IBM 801, influential single-chip processor project of the late 1970s

• In the early 1980s, two projects brought RISC to the forefront: UC

Berkeley’s RISC 1 and 2, forerunners of the Sun SPARC Stanford’s MIPS,
later marketed by a company of the same name

• Other Examples: SparcTM, AlphaTM, etc.

History of RISC
• The original RISC prototype computer, called the 801 Minicomputer, was
built at IBM's Research Division in 1980 - the result of a project that began
in the 1970's.
• 1950s: IBM instituted a research program
• 1964: Release of System/360
• 1975: 801 project initiated at IBM’s Watson Research Center
• 1979: 32-bit RISC microprocessor (801) developed led by Joel Birnbaum
• 1984: MIPS developed at Stanford, as well as projects done at Berkeley
• 1988: RISC processors had taken over high-end of the workstation market
• Early 1990s: IBM’s POWER (Performance Optimization With Enhanced RISC)
architecture introduced with the RISC System/6k
• AIM (Apple, IBM, Motorola) alliance formed, resulting in PowerPC
• CPU performance is given by the fundamental law:

• Thus, CPU performance is dependent upon Instruction Count, CPI (Cycles per instruction)
and Clock cycle time, and all three are affected by the instruction set architecture.

• RISC systems shorten execution time by reducing the clock cycles per instruction.
• CISC systems improve performance by reducing the number of instructions per program.
CHARACTERISTICS OF INITIAL RISC MACHINES

RISC Characteristics IBM 801 RISC I MIPS

Year 1980 1982 1983

Number of instructions 120 39 55
Control memory size 0 0 0
Instruction size (bits) 32 32 32
Technology ECL MSI NMOS VLSI NMOS VLSI
Execution model reg-reg reg-reg reg-reg
Comparison of Processors
Why RISC?
• Simple instructions are preferred
• Complex instructions are mostly ignored by compilers
• Due to semantic gap
• Simple data structures
• Complex data structures are used relatively infrequently
• Better to support a few simple data types efficiently
• Synthesize complex ones
• Simple addressing modes
• Complex addressing modes lead to variable length instructions
• Lead to inefficient instruction decoding and scheduling
Why RISC?
• Large register set
• Efficient support for procedure calls and returns
• Patterson and Sequin’s study
• Procedure call/return: 12-15% of HLL statements
• Constitute 31-33% of machine language instructions
• Generate nearly half (45%) of memory references
• Small activation record
• Tanenbaum’s study
• Only 1.25% of the calls have more than 6 arguments
• More than 93% have less than 6 local scalar variables
• Large register set can avoid memory references
Why RISC?
Traditional CISC structure has inherent shortcomings, the
development of computer technology is constantly introducing new
and complex set of instructions.

To support these new instructions, the computer will be more

complex architecture, however, in many instructions of CISC’s
instruction set, almost 20% instructions will be use repeatedly, and
it accounted for 80% of the entire code. The remaining 80% of the
instruction is not frequently used in the programming, but it still
take 20% of the rest code.

Obviously, this structure is not reasonable.

Why RISC?
Based on the above irrationality, 1979, University of California at Berkeley
in the United States put forward the concept of RISC, RISC is not simply to
reduce the instruction, but to focus on how to make computers simple and
reasonable way to improve operations Speed​​.

RISC structure of the highest priority to select the simple instructions

frequently used to avoid complex instructions; to fixed instruction length,
to reduce instruction format and the ways to search.

Based on control logic, do not use or use less amount of microcode to

achieve above purpose.
Why RISC?
Consider the program fragments:
mov ax, 0
mov ax, 10 mov bx, 10
mov bx, 5 mul cx, 5
CISC RISC Begin add ax, bx
mul bx
loop Begin

• The total clock cycles for the CISC version might be:
(2 movs  1 cycle) + (1 mul  30 cycles) = 32 cycles
• While the clock cycles for the RISC version is:
(3 movs  1 cycle) + (5 adds  1 cycle) + (5 loops  1 cycle) = 13 cycles

• With RISC clock cycle being shorter, RISC gives us much faster execution
speeds.
Advantage of RISC
1. RISC is that they can execute their instructions very fast
because the instructions are so simple. The instructions
usually finish in 4 or 5 processor cycle.
2. Because instruction operand has to store in the register, thus
the operation time is unified.
3. RISC are used pipelining, cache memory, less or do not use
microcode.
4. More important advantage is that RISC chips require fewer
transistors, which makes them cheaper to design and
produce.
Disadvantage of RISC
• There is still considerable controversy among experts about the
ultimate value of RISC architectures. Its proponents argue that RISC
machines are both cheaper and faster, and are therefore the
machines of the future.
• However, by making the hardware simpler, RISC architectures put a
greater burden on the software. Is this worth the trouble because
conventional microprocessors are becoming increasingly fast and
cheap anyway?
• RISC architectures put a greater burden on the software.
• Is this worth the trouble because conventional microprocessors are
becoming increasingly fast and cheap anyway?
Applications of RISC architectures
• Powerful Workstations
• used for engineering purposes (ex. Sun station)
• High-end graphical stations
• used for simulation, animation, etc.
• Microcontrollers
• used for control applications and peripheral devices
• Digital signal processors
• used for signal processing
• Mobile devices
• iPAD, tablet, support for Android systems
•Java
•C
•Python
•Scheme
•Prolog
•C++
•C#
•Java script
•Lisp
•Ruby
 RISC and CISC Approaches
RISC
architecture
Applications Primitive 1

CISC
Processes Primitive 2 architecture

Assembler Long Short

Sequence sequence sequence of
Single
of of proper
instruction
instructions instructions instructions

Firmware
microprogram

Hardware
Performance Parameters
Completion time of a program
• Benchmark approach to performance evalutation (e.g., SPEC benchmarks)
• Comparison of distinct machines, differing at the assembler (and firmware) level
• On the contary: the Performance parameters is meaningful only for the comparison of
different firmware implementations of the same assembler machine.

m m = average number of executed instructions

Tc  m  T 

This simple formula holds rigorously for uniprocessors
without Instruction Level Parallelism

It holds with good approximation for Instruction Level

Parallelism (m = stream length), or for parallel architectures.
Performance Parameters: RISC vs. CISC

m
Tc  m  T 


• RISC decreases T and increases m

• CISC increases T and decreases m

Where is the best trade-off?

• For Instruction Level Parallelism machines: RISC optimizations may be able to
achieve a T decrease greater than the m increase
• cases in which the execution bandwidth has greater impact than the latency
• Where execution latency dominates, CISC achieves lower completion time
• e.g. process cooperation and management, services, special functionalities, …
RISC PIPELINING
• Pipelining is the use of the processor to work on different phases of multiple
instructions in parallel
• A RISC processor pipeline operates in much the same way, although the
stages in the pipeline are different.
• While different processors have different numbers of steps, they are
basically variations of these five, used in the MIPS R3000 processor:
- fetch instructions from memory
- read registers and decode the instruction
- execute the instruction or calculate an address
- access an operand in data memory
- write the result into a register
Basic five-stage pipeline in a RISC machine:
IF = Instruction Fetch
ID = Instruction Decode
EX = Execute instruction
MEM = Memory access
WB = Register write back
In the fourth clock cycle (the green column), the earliest instruction is in MEM stage, and the
latest instruction has not yet entered the pipeline.
 RISC Pipeline Stages
• Fetch instruction
• Decode instruction
• Execute instruction
• Access operand
• Write result

Note: All modern processors operate pipelining with 5 or more stages

Without Pipelining
• Normally, you would perform the fetch, decode, execute, operate,
and write steps of an instruction and then move on to the next
instruction
Without Pipelining

Clock Cycle 1 2 3 4 5 6 7 8 9 10

Instr 1

Instr 2
With Pipelining
• The processor is able to perform each stage simultaneously.
• If the processor is decoding an instruction, it may also fetch another
instruction at the same time.
With Pipelining

Clock Cycle 1 2 3 4 5 6 7 8 9

Instr 1
Instr 2
Instr 3
Instr 4
Instr 5
With Pipelining

• Length of pipeline depends on the longest step

• Thus in RISC, all instructions were made to be the same length
• Each stage takes 1 clock cycle
• In theory, an instruction should be finished each clock cycle
Pipelining on the 486/Pentium
• 486 has a 5-stage pipeline
• Fetch
• Instructions can have variable length and can make this stage out of sync with
other stages. This stage actually fetches about 5 instructions with a 16 byte load
• Decode1
• Decode opcode, addressing modes – can be determined from the first 3 bytes
• Decode2
• Expand opcode into control signals and more complex addressing modes
• Execute
• Write Back
• Store value back to memory or to register file
Pipelining on the 486/Pentium
Fetch D1 D2 Ex WB MOV R1, M
Fetch D1 D2 Ex WB MOV R1, R2
Fetch D1 D2 Ex WB MOV M, R1

Fetch D1 D2 Ex WB MOV R2, M

Fetch D1 D2 Ex MOV R1, (R2)

Need R2 written back to use as addr for second instruction in stage D2

Normally this data is not available until after the WB stage, but bypass circuitry allows us
to send the proper data directly to EX of the next stage (this is called forwarding)
Pipelining on the 486/Pentium

Fetch D1 D2 Ex WB CMP R1,Imm

Fetch D1 D2 Ex JCC Target

Fetch D1 … Target

Target address known after D2 phase

Runs a speculative Fetch on the target during EX
hoping we will execute it (predict taken)

Also fetches next consecutive instruction if branch not taken

Problem in Pipelining
Problem: An instruction may need to wait for the result of another
instruction
Example: add $r3, $r2, $r1
add $r5, $r4, $r3
………

Solution: Compiler may recognize which instructions are dependent or

independent of the current instruction, and rearrange them to run the
independent one first
Problems in Pipelining
• Led to an increase in performance
• Works best when
• all instructions are the same length and
• follow in direct sequence
• Not always the case!
Problems in Pipelining
Instruction Length
• In CISC-based designs, instructions can vary in length
• A long slow instructions can hold up the pipeline
• Less of a problem in RISC-based designs as most instructions are fairly
short
Problems in Pipelining
Data dependency
• If one instruction relies on the result produced by a previous instruction
• Data required for the 2nd instruction may not yet be available because the
1st instruction is still being executed
• Pipeline must be stalled until data is ready for the 2nd instruction
Problems in Pipelining
Branch instructions
• BCC 25 - branch 25 bytes ahead if the carry flag is clear
• If the carry flag is set, the next instructions is carried out as normal
• If the carry flag is clear then the instruction 25 bytes ahead is next
 I: Instruction fetch
Effects of RISC Pipelining E: Execute
D: Memory

(2 stage since
ED are
effectively
one stage)

(E1 register
read, E2
execute &
register write
Particularly
beneficial if E
phase is long)

(Allows 2 memory accesses per stage)

 COMPARISON OF INSTRUCTION SEQUENCE
32b memory port

OP DEST SOUR1 SOUR2

AB+C
RISC 1 register
AA+1
ADD rA rB rC
operand

DD-B ADD rA rA
immediate
operand
1

register
SUB rD rD rB
operand

VAX ADD register B register C register A

(3 operands) operand operand operand
INC register SUB register
A B
(1 operands) operand (2 operands) operand
register D
operand

432 3 operands
B C ...
in memory
A
... C A D
D
A 1 operand I
D A N
D in memory C
I 2 operands
N B
in memory D ...
C

... D SUB
REGISTERS
• By having a large number of general purpose registers, a processor can minimize
the number of times it needs to access memory to load or store a value
• This results in a significant speed up, since memory accesses are much slower
than register accesses
• Register accesses are fast, since they just use the bus on the CPU itself, and any
transfer can be done in one clock cycle
• To go off-processor to memory requires using the much slower memory (or
system) bus
• It may take many clock cycles to read or write to memory across the memory bus
• The memory bus hardware is usually slower than the processor
• There may even be competition for access to the memory bus by other devices in
the computer (e.g. disk drives)
• So, for this reason alone, a RISC processor may have an advantage over a
comparable CISC processor, since it only needs to access memory
• for its instructions, and
• occasionally to load or store a memory value
 EXAMPLE: BERKELEY RISC I
- 32-bit integrated circuit CPU
- 32-bit address, 8-, 16-, 32-bit data
- 32-bit instruction format
- total 31 instructions
- three addressing modes:
register; immediate; PC relative addressing
- 138 registers
10 global registers
8 windows of 32 registers each
 EXAMPLE: BERKELEY RISC I
Berkeley RISC I Instruction Formats
Regsiter mode: (S2 specifies a register)
31 24 23 19 18 14 13 12 5 4 0
Opcode Rd Rs 0 Not used S2
8 5 5 1 8 5

Register-immediate mode (S2 specifies an operand)

31 24 23 19 18 14 13 12 0
Opcode Rd Rs 1 S2
8 5 5 1 13

PC relative mode
31 24 23 19 18 0
Opcode COND Y
8 5 19
 EXAMPLE: BERKELEY RISC I
• Register 0 was hard-wired to a value of 0.
• There are eight memory access instructions
• Five load-from-memory instructions
• Three store-to-memory instructions.

• The load instructions:

LDL load long
LDSU load short unsigned
LDSS load short signed
LDBU load byte unsigned
LDBS load byte signed
• Where long is 32 bits, short is 16 bits and a byte is 8 bits

• The store instructions:

STL store long
STS store short
STB store byte
 EXAMPLE: BERKELEY RISC I
LDL Rd  M[(Rs) + S2] load long

LDSU Rd  M[(Rs) + S2] load short unsigned

LDSS Rd  M[(Rs) + S2] load short signed

LDBU Rd  M[(Rs) + S2] load byte unsigned

LDBS Rd  M[(Rs) + S2] load byte signed

STL M[(Rs) + S2]  Rd store long

STS M[(Rs) + S2]  Rd store short
STB M[(Rs) + S2]  Rd store byte

Here the difference between the lengths is

• A long is simply loaded, since it is the same size as the register (32 bits).
• A short or a byte can be loaded into a register
• Unsigned - in which case the upper bits of the register are loaded with 0’s.
• Signed - in which case the upper bits of the register are loaded with the sign bit of the short/byte loaded.
INSTRUCTION SET OF BERKELEY RISC I
Opcode Operands Register Transfer Description

Data manipulation instructions

ADD Rs,S2,Rd Rd  Rs + S2 Integer add
ADDC Rs,S2,Rd Rd  Rs + S2 + carry Add with carry
SUB Rs,S2,Rd Rd  Rs - S2 Integer subtract
SUBC Rs,S2,Rd Rd  Rs - S2 - carry Subtract with carry
SUBR Rs,S2,Rd Rd  S2 - Rs Subtract reverse
SUBCR Rs,S2,Rd Rd  S2 - Rs - carry Subtract with carry
AND Rs,S2,Rd Rd  Rs  S2 AND
OR Rs,S2,Rd Rd  Rs  S2 OR
XOR Rs,S2,Rd Rd  Rs  S2 Exclusive-OR
SLL Rs,S2,Rd Rd  Rs shifted by S2 Shift-left
SRL Rs,S2,Rd Rd  Rs shifted by S2 Shift-right logical
SRA Rs,S2,Rd Rd  Rs shifted by S2 Shift-right arithmetic

Data transfer instructions

LDL (Rs)S2,Rd Rd  M[Rs + S2] Load long
LDSU (Rs)S2,Rd Rd  M[Rs + S2] Load short unsigned
LDSS (Rs)S2,Rd Rd  M[Rs + S2] Load short signed
LDBU (Rs)S2,Rd Rd  M[Rs + S2] Load byte unsigned
LDBS (Rs)S2,Rd Rd  M[Rs + S2] Load byte signed
LDHI Rd,Y Rd  Y Load immediate high
STL Rd,(Rs)S2 M[Rs + S2]  Rd Store long
STS Rd,(Rs)S2 M[Rs + S2]  Rd Store short
STB Rd,(Rs)S2 M[Rs + S2]  Rd Store byte
GETPSW Rd Rd  PSW Load status word
PUTPSW Rd PSW  Rd Set status word
INSTRUCTION SET OF BERKELEY RISC I

Opcode Operands Register Transfer Description

Program control instructions
JMP COND,S2(Rs) PC  Rs + S2 Conditional jump
JMPR COND,Y PC  PC + Y Jump relative
CALL Rd,S2(Rs) Rd  PC, PC  Rs + S2 Call subroutine and change window
CWP  CWP - 1
CALLR Rd,Y Rd  PC, PC  PC + Y Call relative and change window
CWP  CWP - 1
RET Rd,S2 PC  Rd + S2 Return and change window
CWP  CWP + 1
CALLINT Rd Rd  PC,CWP  CWP - 1 Call an interrupt pr.
RETINT Rd,S2 PC  Rd + S2 Return from interrupt pr.
CWP  CWP + 1
GTLPC Rd Rd  PC Get last PC
Referencing a Scalar - Window Based Register File
Referencing a Scalar - Cache
Memory to Memory vs. Register to Memory Operations
(RISC uses only Register to memory)

 Actually these numbers are bits, not bytes

Book References:
• W. Stalling, “Computer Organization and Architecture”, 7th
edition, Prentice-Hall India Limited, New Delhi.
• A.J. Vande Goor, “Computer Architecture and Design”,
Addison Wesley, Wokingham, UK, 1989
• A.S. Tanenbaum, “Structured Computer Organization”,
Prentice Hall India Limited, new Delhi.
• M. Morris Mano, “Computer System Architecture”, Latest
Edition.
• John P. Hayes, “Computer Architecture and Organization”,
Latest Edition.