Save trees use e-Question Paper Go green DOWNLOAD THIS FREE AT www.viuresource.com USN O ] 10cs74 Seventh Semester B.E. Degree Examination, June/July 2016 Advanced Computer Architecture Time: 3 hrs, Max. Marks: Note: Answer any FIVE full questions, selecting atleast TWO questions from each PART—A 1a. Define lostnston Set Artest). Expl even dimensions ofan os Assume a disk subsystem with the following components and MTTP #10 disks each rated at 1,000,000 hr MTTF 1 SCSI controller, $00,000 — hour MTTF * 1 Power supply, 200,000 ~ hour MITF * 1 Fap, 200, 000 — hour MTTF. * 1 SCSI cable, 1,000,000 — hour MTTF. Using the simplifying assumptions that the lifetimes are expor failures are independent, compute the MTTF of the systema cc. List and explain four important technologies, witichyehange critical to modern implementation. ly distributed and that shal (0S Marks) dramatic pace and are (05 Marks) 2a With aneat diagram, explain the classic five List three major hurdles of pipelining Explain’ SOPRISC processor. (10 Marks) pf minimizing data hazards stalls below DSUB —R4,RI,RS AND —-R6RI,RT OR R8.RI,R9 XOR R10, RI, RIL do Mans) 3a, Show how the below loop, MIPS 5 — stage pipeline, under the following Situations, Also find ve rer of e¥@l8s per iteration for each case. Latens of LOAD is 2, ADD Dis 3, store is is 2 and Branches is 1 (12 Marks) 3) Without Fthout uarolling il). With scheduling, without unrolling. ii) Wi ling, without scheduling iv) With loop unrelling, with seheduling. What ist xk of | - bit dynamic branch prediction method? Clearly state how it is. ‘ovygroome in 2 — Bit prediction, Give the state transition diagram of 2— bit predictor. (8 Marks) 4 al the basic VLIW approach or exploiting TLP, with multiple issues using the example, We have a VLIW that could issue two memory references, two FP tons and one integer ot branch every clock cycle. Use the unrolled version of the code "B}VER in question 3a, How many clock eyeles per result does it require? (Oo Marks) ‘What is Branch Target Buffer? With a neat diagram, explain the steps when using BTB. (0 Marks) 1 of2 BRANCHES | ALL SEMESTERS | NOTES | QUESTON PAPERS | LAB MANUALS A Viuresource Go Green initiativeSave trees use e-Question Paper Go green DOWNLOAD THIS FREE AT www.viuresource.com 10cs74 "ART. 5 a, With the help of neat diagram, explain the basi structure of centralized shared memory distributed memory multiprocessor. (lO Marks) b, Explain dcectory based cache coherence for @ distribated memory multi sty along with the state transition diagram. 8) 6 a. Listthe basic cache optimization techniques. Explain any four lars) b. Assume we have a computer where the CPI is 1.0 when all memffy accesges hit in the ofthe i cache. The only data accesses are loads and stores and these tot ructions. If the miss penalty is 25 clock cycles and the miss rate is 2%, would the computer be if all instructions were cache hits? (0 Marks) 7a. Which ate the shajor categories of advanced optimizations Ogche Rtformance? Explain ‘multibanked caches to increase cache bandwidth (10 Marks) bb. Explain in detail, the architecture support for protect@Raproceges from each other via (0 Marks) ao 44 i ha oft el lt ie ett my aa 20f2 BRANCHES | ALL SEMESTERS | NOTES | QUESTON PAPERS | LAB MANUALS A Viuresource Go Green initiative