Combinatorial Logic

Logic Gates and Boolean (Binary, 1/0 or TRUE/FALSE) Algebra

Digital (logic) circuits operate in the binary mode when each input and output
voltage is either a 1 or 0 (TRUE or FALSE).

1 and 0 are represented by predefined voltage ranges.

For example, for the TTL (Transistor Transistor Logic), have

Logic Input Range Output Range

0 0-0.8 V 0-0.4 V
1 2-5 V 2.4-5V

Note that the output range is tighter than the

input range to ensure greater reliability.
Combinatorial Circuits designed/analyzed using the principles of Boolean Algebra,
where variables can only take the logical values 0 (FALSE) or 1 (TRUE)
Basic Functions of Boolean Algebra are –

NOT In Boolean Algebra, 1 and 0

B=A (NOT) A B=1 if A=0 or B=0 if A=1 are NOT NUMBERS.
OR C=A+B C=0 only if A=B=0; else C=1
They merely represent the
AND C=AB C=1 if A=B=1; else C=0 logical variables TRUE and
FALSE

Other commonly used functions derived from these are –

NAND (NOT AND) C=AB C=0 only if A=B=1; else C=1
NOR (NOT OR) C=A+B C=1 only if A=B=0; else C=0
ExOR (Exclusive OR) C=AB+AB C=1 only if A=1, B=0 or A=0, B=1 i.e. A  B
Logic Gates Digital circuits implementing different logic functions

+5 V
Example: TTL NAND Gate
R2 R4
1.6 KΩ 130 Ω
This is the basic logic gate as one R1
can use this to implement all the 4 KΩ

other gates Q4

D
A Q2 Y=AB
B Q1
Output
Inputs Q3

R3
1 KΩ

When A and B are HIGH,

GND
the transistor Q1 is in the
Inverse Active Mode
Logic Gates Digital circuits implementing different logic functions

CMOS Inverter (NOT) CMOS NAND Gate

Important: Outputs of two or more standard logic gates should not be connected
together, even if they are of the same family!!

Special logic devices do allow their outputs to be connected. These are

Open Collector/Open Drain Output Gates: (TTL/CMOS)

* These need an external resistor connected to the power supply (VCC)
* Not very popular these days except when high current has to be driven
* Does allow a Wire-AND operation which is also not very popular now

Tri-State Output: (Both TTL and CMOS)

* Gate output has three states HIGH, LOW and High Impedance (Floating)
* Multiple Gate Outputs can be shorted as long as all of them, EXCEPT
ONE, are in the High Impedance state. Example: Bussed Architecture
TTL Open Collector NAND Gate

Open Collector Circuit Schematic Open Collector Circuit Schematic

(without resistor) (with resistor)
Tristate Noninverting Buffers

The outputs of multiple

gates can be connected
together as long as only
one of them is enabled
TTL Inverter Gate with Tristate Output

R2 R4
1.6 KΩ 130 Ω
R1
4 KΩ

Q4
EN=1 Gate operates normally
Input D
EN=0 Q3 and Q4 are OFF and Q1
Q2 Y=A
the output is FLOATING Output
Q3
EN
R3
1 KΩ

GND
 Truth Table

Tabular representation describing how a logic

circuit’s output(s) depend on its input(s)

See examples in the subsequent slides

NOT gate or Inverter
A X=A
A X=A 0 1
1 0
Truth Table
1

0
A
1
0
OR operation X = A+B

A B X
A
X=A+B 0 0 0
B
0 1 1
1 0 1
2-Input OR gate 1 1 1
Truth Table
OR operation X = A+B+C A B C X
0 0 0 0
0 0 1 1
A 0 1 0 1
B
C X=A+B+C 0 1 1 1
1 0 0 1
1 0 1 1
3-Input OR gate 1 1 0 1
1 1 1 1

Truth Table
AND operation X = AB

A B X
A X = AB 0 0 0
B 0 1 0
1 0 0
1 1 1
2-Input AND gate
Truth Table
NOR Gate
A B A+B A+B
0 0 0 1
A
B X=A+B 0 1 1 0
1 0 1 0
1 1 1 0

Truth Table
NAND Gate

A B AB AB
A 0 0 0 1
X = AB
B 0 1 0 1
1 0 0 1
1 1 1 0

Truth Table
Ex-OR (or XOR) Gate A
Y

Y=A  B=AB+AB
B

This gate can be viewed in two ways.

A B Y
Comparator Output is LOW only when both the inputs are
identical 0 0 0
Half-Adder Y is the BINARY SUM of A and B ignoring the carry- 0 1 1
out generated by adding 1+1 1 0 1
A
AB
1 1 0

Y
Truth Table
AB

AB
B
Describing Logic Circuits Algebraically

Examples: B
X=AB+C
X= ?
C

A
B X= ? X=(A+B)C
C

A
B X= ?

X=A+B

B X= ?
X = (A + B)
Boolean Algebra Theorems

Duals Distributive Law

Interchange + and .
(1) A = A Interchange 0 and 1 (10) A(B+C)=AB+AC
(11) Dual A+BC=(A+B)(A+C)
(2) A+0=A (6) A.1 = A
(3) A+1=1 (7) A.0 =0
(4) A+A=A (8) A.A=A
(5) A+A = 1 (9) A.A = 0
A + AB = A (12)
A + AB = A + B (13)
AB + AB = A (14)
AB + AC = (A + C)(A + B) (15)
AB + AC + BC = AB + AC (16)

Duals

A.(A + B) = A (17)
A.(A + B) = A.B (18)
(A + B).(A + B) = A (19)
(A + B).(A + C) = AC + AB (20)
(A + B).(A + C).(B + C) = (A + B).(A + C) (21)
De Morgan’s Theorem:

A.B.C..... ...... = A + B + C + .......... ...... (22)

A + B + C......... .. = A. B. C .......... ...... (23)

Examples Z = (A + C ).(B + D ) Z = AC( ABD) + ABCD + ABC

= (A + C ) + (B + D ) =AC( A + B + D) + ABCD + ABC
( )
= A. C + B.D ( )
= AC A + B + D + ABCD + ABC
= AC + BD = ACA + ABC + ACD + ABCD + ABC
= 0 + BC( A + A) + ACD + ABCD
= BC + A D( C + BC)
= BC + A D( C + B)
Universality of NAND and NOR gates

• All the Boolean expressions can be implemented using various combinations of

OR, AND and NOT gates.

• Again NAND or NOR gates in proper combination can be used to perform each of
the Boolean operations OR, AND and NOT.

• Any logic expression can be implemented using ONLY NAND or NOR gates.

• Therefore, NAND and NOR Gates are known as Universal Gates

Standard Forms For Logical Expression

For Logic circuit simplification and design, we try to

express the logical expression in one of two standard
forms –

Sum-of-Products Form ABC+ABC AB+ABC+CD+D

or Product-of-Sums Form (A+B+C)(A+C) (A+B+C)(A+B+C)

Note that (i) The same variable used never appears twice because A.A=A A.A=0 A+A=A A+A = 1
and (ii) One complement sign cannot cover more than one variable in a term (e.g., we cannot have
ABC as we can then use De Morgan’s Law to simplify.
Standard Sum of Products (SOP) Form
A SOP Form in which each product term involves all the variables, complemented or
uncomplemented. Each individual term is referred to as a minterm.

Example: Z=ABC+ABC+ABC

Standard Product of Sums (POS) Form

A POS Form in which each term consists of a sum, involving all the variables in
either complemented or uncomplemented form. Each sum is referred to as a
maxterm

Example: Z=(A+B+C)(A+B+C)