Features

• Fast Read Access Time – 120 ns

• 5-volt Only Reprogramming
• Sector Program Operation
– Single Cycle Reprogram (Erase and Program)
– 2048 Sectors (256 bytes/sector)
– Internal Address and Data Latches for 256 Bytes
• Internal Program Control and Timer
• Hardware and Software Data Protection
• Two 16 KB Boot Blocks with Lockout
•
•
Fast Sector Program Cycle Time - 10 ms
DATA Polling for End of Program Detection
4-megabit
• Low Power Dissipation
– 40 mA Active Current (512K x 8)
– 100 µA CMOS Standby Current
• Typical Endurance > 10,000 Cycles 5-volt Only
• Single 5V ± 10% Supply
• CMOS and TTL Compatible Inputs and Outputs 256-byte Sector
Description Flash Memory
The AT29C040A is a 5-volt only in-system Flash Programmable and Erasable Read
Only Memory (PEROM). Its 4 megabits of memory is organized as 524,288 words by
8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS EEPROM technology, AT29C040A
the device offers access times up to 120 ns, and a low 220 mW power dissipation.
When the device is deselected, the CMOS standby current is less than 100 µA. The
device endurance is such that any sector can typically be written to in excess of
10,000 times. The programming algorithm is compatible with other devices in Atmel’s
5-volt only Flash family. (continued)
PLCC Top View
Pin Configurations
VCC
A18
A12
A15
A16

A17
WE

Pin Name Function

4
3
2
1
32
31
30

A7 5 29 A14
A0 - A18 Addresses A6 6 28 A13
A5 7 27 A8
CE Chip Enable A4 8 26 A9
A3 9 25 A11
OE Output Enable A2 10 24 OE
A1 11 23 A10
WE Write Enable A0 12 22 CE
I/O0 13 21 I/O7
14
15
16
17
18
19
20

I/O0 - I/O7 Data Inputs/Outputs

I/O1
I/O2
GND
I/O3
I/O4
I/O5
I/O6

NC No Connect

DIP Top View TSOP Top View

Type 1
A18 1 32 VCC
A16 2 31 WE A11 1 32 OE
A15 3 30 A17 A9 2 31 A10
A12 4 29 A14 A8 3 30 CE
A7 5 28 A13 A13 4 29 I/O7
A6 6 27 A8 A14 5 28 I/O6
A5 7 26 A9 A17 6 27 I/O5
A4 8 25 A11 WE 7 26 I/O4
A3 9 24 OE VCC 8 25 I/O3
A2 10 23 A10 A18 9 24 GND
A1 11 22 CE A16 10 23 I/O2
A15 11 22 I/O1
A0 12 21 I/O7
A12 12 21 I/O0
I/O0 13 20 I/O6
A7 13 20 A0
I/O1 14 19 I/O5
A6 14 19 A1
I/O2 15 18 I/O4
A5 15 18 A2 Rev. 0333G–03/01
GND 16 17 I/O3
A4 16 17 A3

1
To allow for simple in-system reprogrammability, the first data byte has been loaded into the device, successive
AT29C040A does not require high input voltages for pro- bytes are entered in the same manner. Each new byte to
gramming. Five-volt-only commands determine the opera- be programmed must have its high to low transition on WE
tion of the device. Reading data out of the device is similar (or CE) within 150 µs of the low to high transition of WE (or
to reading from an EPROM. Reprogramming the CE) of the preceding byte. If a high to low transition is not
AT29C040A is performed on a sector basis; 256 bytes of detected within 150 µs of the last low to high transition, the
data are loaded into the device and then simultaneously load period will end and the internal programming period
programmed. will start. A8 to A18 specify the sector address. The sector
During a reprogram cycle, the address locations and 256 address must be valid during each high to low transition of
bytes of data are internally latched, freeing the address and WE (or CE). A0 to A7 specify the byte address within the
data bus for other operations. Following the initiation of a sector. The bytes may be loaded in any order; sequential
program cycle, the device will automatically erase the sec- loading is not required. Once a programming operation has
tor and then program the latched data using an internal been initiated, and for the duration of tWC, a read operation
control timer. The end of a program cycle can be detected will effectively be a polling operation.
by DATA polling of I/O7. Once the end of a program cycle SOFTWARE DATA PROTECTION: A software con-
has been detected, a new access for a read or program troll ed data pr otec tion feature is av ailable on the
can begin. AT29C040A. Once the software protection is enabled a
software algorithm must be issued to the device before a
Block Diagram program may be performed. The software protection fea-
ture may be enabled or disabled by the user; when shipped
from Atmel, the software data protection feature is dis-
abled. To enable the software data protection, a series of
three program commands to specific addresses with spe-
cific data must be performed. After the software data pro-
tection is enabled the same three program commands
must begin each program cycle in order for the programs to
occur. All software program commands must obey the sec-
tor program timing specifications. The SDP feature protects
all sectors, not just a single sector. Once set, the software
data protection feature remains active unless its disable
command is issued. Power transitions will not reset the
software data protection feature, however the software fea-
ture will guard against inadvertent program cycles during
Device Operation power transitions.
READ: The AT29C040A is accessed like an EPROM.
After setting SDP, any attempt to write to the device without
When CE and OE are low and WE is high, the data stored
the three-byte command sequence will start the internal
at the memory location determined by the address pins is
write timers. No data will be written to the device; however,
asserted on the outputs. The outputs are put in the high
for the duration of tWC, a read operation will effectively be a
impedance state whenever CE or OE is high. This dual-line
polling operation.
control gives designers flexibility in preventing bus conten-
tion. After the software data protection’s 3-byte command code
is given, a byte load is performed by applying a low pulse
BYTE LOAD: Byte loads are used to enter the 256 bytes
on the WE or CE input with CE or WE low (respectively)
of a sector to be programmed or the software codes for
and OE high. The address is latched on the falling edge of
data protection. A byte load is performed by applying a low
CE or WE, whichever occurs last. The data is latched by
pulse on the WE or CE input with CE or WE low (respec-
the first rising edge of CE or WE. The 256 bytes of data
tively) and OE high. The address is latched on the falling
must be loaded into each sector by the same procedure as
edge of CE or WE, whichever occurs last. The data is
outlined in the program section under device operation.
latched by the first rising edge of CE or WE.
HARDWARE DATA PROTECTION: Hardware features
PROGRAM: The device is reprogrammed on a sector
protect against inadvertent programs to the AT29C040A in
basis. If a byte of data within a sector is to be changed,
the following ways: (a) V CC sense—if V CC is below 3.8V
data for the entire sector must be loaded into the device.
(typical), the program function is inhibited; (b) VCC power on
Any byte that is not loaded during the programming of its
delay—once V CC has reached the V CC sense level, the
sector will be erased to read FFH. Once the bytes of a sec-
device will automatically time out 5 ms (typical) before pro-
tor are loaded into the device, they are simultaneously pro-
gramming; (c) Program inhibit—holding any one of OE low,
grammed during the internal programming period. After the

2 AT29C040A
 AT29C040A

CE high or WE high inhibits program cycles; and (d) Noise BO OT BLOCK PROGRAMMING LOCKO UT: The
filter—pulses of less than 15 ns (typical) on the WE or CE AT29C040A has two designated memory blocks that have
inputs will not initiate a program cycle. a programming lockout feature. This feature prevents pro-
PRODUCT IDENTIFICATION: The product identification gramming of data in the designated block once the feature
mode identifies the device and manufacturer as Atmel. It has been enabled. Each of these blocks consists of 16K
may be accessed by hardware or software operation. The bytes; the programming lockout feature can be set inde-
hardware operation mode can be used by an external pro- pendently for either block. While the lockout feature does
grammer to identify the correct programming algorithm for not have to be activated, it can be activated for either or
the Atmel product. In addition, users may wish to use the both blocks.
software product identification mode to identify the part (i.e. These two 16K memory sections are referred to as boot
using the device code), and have the system software use blocks. Secure code which will bring up a system can be
the appropriate sector size for program operations. In this contained in a boot block. The AT29C040A blocks are
manner, the user can have a common board design for located in the first 16K bytes of memory and the last 16K
256K to 4-megabit densities and, with each density’s sector bytes of memory. The boot block programming lockout fea-
size in a memory map, have the system software apply the ture can therefore support systems that boot from the lower
appropriate sector size. addresses of memory or the higher addresses. Once the
For details, see Operating Modes (for hardware operation) programming lockout feature has been activated, the data
or Software Product Identification. The manufacturer and in that block can no longer be erased or programmed; data
device code is the same for both modes. in other memory locations can still be changed through the
regular programming methods. To activate the lockout fea-
DATA POLLING: The AT29C040A features DATA poll-
ture, a series of seven program commands to specific
ing to indicate the end of a program cycle. During a pro-
addresses with specific data must be performed. Please
gram cycle an attempted read of the last byte loaded will
see Boot Block Lockout Feature Enable Algorithm.
result in the complement of the loaded data on I/O7. Once
the program cycle has been completed, true data is valid If the boot block lockout feature has been activated on
on all outputs and the next cycle may begin. DATA polling either block, the chip erase function will be disabled.
may begin at any time during the program cycle. BOOT BLOCK LOCKOUT DETECTION: A software
TOGGLE BIT: In addition to DATA polling the method is available to determine whether programming of
AT29C040A provides another method for determining the either boot block section is locked out. See Software Prod-
end of a program or erase cycle. During a program or erase uct Identification Entry and Exit sections. When the device
operation, successive attempts to read data from the is in the software product identification mode, a read from
device will result in I/O6 toggling between one and zero. location 00002H will show if programming the lower
Once the program cycle has completed, I/O6 will stop tog- address boot block is locked out while reading location
gling and valid data will be read. Examining the toggle bit FFFF2H will do so for the upper boot block. If the data is
may begin at any time during a program cycle. FE, the corresponding block can be programmed; if the
data is FF, the program lockout feature has been activated
OPTIONAL CHIP ERASE MODE: The entire device can
and the corresponding block cannot be programmed. The
be erased by using a 6-byte software code. Please see
software product identification exit mode should be used to
Software Chip Erase application note for details.
return to standard operation.

Absolute Maximum Ratings*

Temperature Under Bias................................ -55°C to +125°C *NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
Storage Temperature ..................................... -65°C to +150°C age to the device. This is a stress rating only and
functional operation of the device at these or any
All Input Voltages (including NC Pins) other conditions beyond those indicated in the
with Respect to Ground ...................................-0.6V to +6.25V operational sections of this specification is not
implied. Exposure to absolute maximum rating
All Output Voltages conditions for extended periods may affect
with Respect to Ground .............................-0.6V to VCC + 0.6V device reliability.

Voltage on OE
with Respect to Ground ...................................-0.6V to +13.5V

3
DC and AC Operating Range
AT29C040A-12 AT29C040A-15 AT29C040A-20

Operating Com. 0°C - 70°C 0°C - 70°C 0°C - 70°C

Temperature (Case) Ind. -40°C - 85°C -40°C - 85°C -40°C - 85°C
VCC Power Supply 5V ± 10% 5V ± 10% 5V ± 10%

Operating Modes
Mode CE OE WE Ai I/O
Read VIL VIL VIH Ai DOUT
(2)
Program VIL VIH VIL Ai DIN
Standby/Write Inhibit VIH X(1) X X High Z
Program Inhibit X X VIH
Program Inhibit X VIL X
Output Disable X VIH X High Z
Product Identification
A1 - A18 = VIL, A9 = VH,(3) A0 = VIL Manufacturer Code(4)
Hardware VIL VIL VIH
A1 - A18 = VIL, A9 = VH,(3) A0 = VIH Device Code(4)
A0 = VIL Manufacturer Code(4)
Software(5)
A0 = VIH Device Code(4)
Notes: 1. X can be VIL or VIH.
2. Refer to AC Programming Waveforms.
3. VH = 12.0V ± 0.5V.
4. Manufacturer Code: 1F, Device Code: A4.
5. See details under Software Product Identification Entry/Exit.

DC Characteristics
Symbol Parameter Condition Min Max Units
ILI Input Load Current VIN = 0V to VCC 10 µA
ILO Output Leakage Current VI/O = 0V to VCC 10 µA
Com. 100 µA
ISB1 VCC Standby Current CMOS CE = VCC - 0.3V to VCC
Ind. 300 µA
ISB2 VCC Standby Current TTL CE = 2.0V to VCC 3 mA
ICC VCC Active Current f = 5 MHz; IOUT = 0 mA 40 mA
VIL Input Low Voltage 0.8 V
VIH Input High Voltage 2.0 V
VOL Output Low Voltage IOL = 2.1 mA 0.45 V
VOH1 Output High Voltage IOH = -400 µA 2.4 V
VOH2 Output High Voltage CMOS IOH = -100 µA; VCC = 4.5V 4.2 V

4 AT29C040A
 AT29C040A

AC Read Characteristics
AT29C040A-12 AT29C040A-15 AT29C040A-20
Symbol Parameter Min Max Min Max Min Max Units
tACC Address to Output Delay 120 150 200 ns
(1)
tCE CE to Output Delay 120 150 200 ns
(2)
tOE OE to Output Delay 0 50 0 70 0 80 ns
tDF(3)(4) CE or OE to Output Float 0 30 0 40 0 50 ns
Output Hold from OE, CE or
tOH 0 0 0 ns
Address, whichever occurred first

AC Read Waveforms(1)(2)(3)(4)

Notes: 1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC.
2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change
without impact on tACC.
3. tDF is specified from OE or CE whichever occurs first (CL = 5 pF).
4. This parameter is characterized and is not 100% tested.

Input Test Waveforms and Output Test Load

Measurement Level

tR, tF < 5 ns

Pin Capacitance
f = 1 MHz, T = 25°C(1)
Symbol Typ Max Units Conditions
CIN 4 6 pF VIN = 0V
COUT 8 12 pF VOUT = 0V
Note: 1. This parameter is characterized and is not 100% tested.

5
AC Byte Load Characteristics
Symbol Parameter Min Max Units
tAS, tOES Address, OE Setup Time 10 ns
tAH Address Hold Time 50 ns
tCS Chip Select Setup Time 0 ns
tCH Chip Select Hold Time 0 ns
tWP Write Pulse Width (WE or CE) 90 ns
tDS Data Setup Time 50 ns
tDH, tOEH Data, OE Hold Time 10 ns
tWPH Write Pulse Width High 100 ns

AC Byte Load Waveforms(1)

WE Controlled

CE Controlled

Note: 1. A complete sector (256 bytes) should be loaded using the waveforms shown in these byte load waveform diagrams.

6 AT29C040A
 AT29C040A

Program Cycle Characteristics

Symbol Parameter Min Max Units
tWC Write Cycle Time 10 ms
tAS Address Setup Time 10 ns
tAH Address Hold Time 50 ns
tDS Data Setup Time 50 ns
tDH Data Hold Time 10 ns
tWP Write Pulse Width 90 ns
tBLC Byte Load Cycle Time 150 µs
tWPH Write Pulse Width High 100 ns

Program Cycle Waveforms(1)(2)(3)

Notes: 1. A8 through A18 must specify the sector address during each high to low transition of WE (or CE).
2. OE must be high only when WE and CE are both low.
3. All bytes that are not loaded within the sector being programmed will be indeterminate.

7
Software Data Protection Software Data Protection
Enable Algorithm(1) Disable Algorithm(1)
LOAD DATA AA LOAD DATA AA
TO TO
ADDRESS 5555 ADDRESS 5555

LOAD DATA 55 LOAD DATA 55

TO TO
ADDRESS 2AAA ADDRESS 2AAA

LOAD DATA A0 LOAD DATA 80

TO TO
ADDRESS 5555 WRITES ENABLED ADDRESS 5555

LOAD DATA LOAD DATA AA

TO ENTER DATA TO
PAGE (256 BYTES)(4) PROTECT STATE(2) ADDRESS 5555

Notes for software program code:

1. Data Format: I/O7 - I/O0 (Hex); LOAD DATA 55
Address Format: A14 - A0 (Hex). TO
2. Data Protect state will be activated at end of program ADDRESS 2AAA
cycle.
3. Data Protect state will be deactivated at end of program
period. LOAD DATA 20
4. 256 bytes of data MUST BE loaded. TO
ADDRESS 5555 EXIT DATA
PROTECT STATE(3)

LOAD DATA
TO
PAGE (256 BYTES)(4)

Software Protected Program Cycle Waveform(1)(2)(3)

Notes: 1. A8 through A18 must specify the sector address during each high to low transition of WE (or CE) after the software code
has been entered.
2. OE must be high when WE and CE are both low.
3. All bytes that are not loaded within the sector being programmed will be indeterminate.

8 AT29C040A
 AT29C040A

Data Polling Characteristics(1)

Symbol Parameter Min Typ Max Units
tDH Data Hold Time 10 ns
tOEH OE Hold Time 10 ns
(2)
tOE OE to Output Delay ns
tWR Write Recovery Time 0 ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See tOE spec in AC Read Characteristics.

Data Polling Waveforms

Toggle Bit Characteristics(1)

Symbol Parameter Min Typ Max Units
tDH Data Hold Time 10 ns
tOEH OE Hold Time 10 ns
(2)
tOE OE to Output Delay ns
tOEHP OE High Pulse 150 ns
tWR Write Recovery Time 0 ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See tOE spec in AC Read Characteristics.

Toggle Bit Waveforms(1)(2)(3)

Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit. The tOEHP specification must be met by the toggling
input(s).
2. Beginning and ending state of I/O6 will vary.
3. Any address location may be used but the address should not vary.

9
Software Product Identification Entry(1) Boot Block Lockout
LOAD DATA AA
Feature Enable Algorithm(1)
TO
LOAD DATA AA
ADDRESS 5555
TO
ADDRESS 5555

LOAD DATA 55
TO
LOAD DATA 55
ADDRESS 2AAA
TO
ADDRESS 2AAA

LOAD DATA 90
TO
LOAD DATA 80
ADDRESS 5555
TO
ADDRESS 5555

PAUSE 10 mS ENTER PRODUCT

LOAD DATA AA
IDENTIFICATION
TO
MODE(2)(3)(5)
ADDRESS 5555

Software Product Identification Exit(1)

LOAD DATA 55
LOAD DATA AA TO
TO ADDRESS 2AAA
ADDRESS 5555

LOAD DATA 40
LOAD DATA 55 TO
TO ADDRESS 5555
ADDRESS 2AAA

LOAD DATA 00 LOAD DATA FF

LOAD DATA F0 TO TO
TO ADDRESS 00000H(2) ADDRESS FFFFFH(3)
ADDRESS 5555

PAUSE 10 mS PAUSE 10 mS
PAUSE 10 mS EXIT PRODUCT
IDENTIFICATION
MODE(4) Notes for boot block lockout feature enable:
Notes for software product identification: 1. Data Format: I/O7 - I/O0 (Hex);
1. Data Format: I/O7 - I/O0 (Hex); Address Format: A14 - A0 (Hex).
Address Format: A14 - A0 (Hex). 2. Lockout feature set on lower address boot block.
2. A1 - A18 = VIL. 3. Lockout feature set on higher address boot block.
Manufacturer Code is read for A0 = VIL;
Device Code is read for A0 = VIH.
3. The device does not remain in identification mode if
powered down.
4. The device returns to standard operation mode.
5. Manufacturer Code is 1F. The Device Code is A4.

10 AT29C040A
 AT29C040A

Ordering Information
tACC ICC (mA)
(ns) Active Standby Ordering Code Package Operation Range
120 40 0.1 AT29C040A-12JC 32J Commercial
AT29C040A-12PC 32P6 (0° to 70°C)
AT29C040A-12TC 32T
40 0.3 AT29C040A-12JI 32J Industrial
AT29C040A-12PI 32P6 (-40° to 85°C)
AT29C040A-12TI 32T
150 40 0.1 AT29C040A-15JC 32J Commercial
AT29C040A-15PC 32P6 (0° to 70°C)
AT29C040A-15TC 32T
40 0.3 AT29C040A-15JI 32J Industrial
AT29C040A-15PI 32P6 (-40° to 85°C)
AT29C040A-15TI 32T
200 40 0.1 AT29C040A-20JC 32J Commercial
AT29C040A-20PC 32P6 (0° to 70°C)
AT29C040A-20TC 32T
40 0.3 AT29C040A-20JI 32J Industrial
AT29C040A-20PI 32P6 (-40° to 85°C)
AT29C040A-20TI 32T

Package Type
32J 32-lead, Plastic J-leaded Chip Carrier (PLCC)
32P6 32-lead, 0.600" Wide, Plastic Dual Inline Package (PDIP)
32T 32-lead, Thin Small Outline Package (TSOP)

11
Packaging Information
32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC) 32P6, 32-lead, 0.600” Wide, Plastic Dual Inline
Dimensions in Inches and (Millimeters) Package (PDIP)
JEDEC STANDARD MS-016 AE Dimensions in Inches and (Millimeters)

.025(.635) X 30˚ - 45˚ 1.67(42.4)

.045(1.14) X 45˚ PIN NO. 1 1.64(41.7)
.012(.305) PIN
IDENTIFY 1
.008(.203)

.530(13.5)
.553(14.0) .566(14.4)
.490(12.4) .530(13.5)
.032(.813) .547(13.9)
.595(15.1) .021(.533)
.026(.660)
.585(14.9) .013(.330)
.090(2.29)
1.500(38.10) REF MAX
.050(1.27) TYP .030(.762) .220(5.59)
.300(7.62) REF .015(.381) .005(.127)
MAX MIN
.430(10.9) .095(2.41)
.390(9.90) .060(1.52) SEATING
AT CONTACT .140(3.56) PLANE
POINTS .065(1.65)
.120(3.05) .161(4.09) .015(.381)
.125(3.18)
.022(.559)
.065(1.65) .014(.356)
.110(2.79) .041(1.04)
.022(.559) X 45˚ MAX (3X) .090(2.29)
.630(16.0)
.590(15.0)
.453(11.5)
0 REF
.447(11.4) 15
.012(.305)
.495(12.6)
.008(.203)
.485(12.3) .690(17.5)
.610(15.5)

32T, 32-lead, Plastic Thin Small Outline Package

(TSOP)
Dimensions in Millimeters and (Inches)*
JEDEC OUTLINE MO-142 BD

INDEX
MARK

18.5(.728) 20.2(.795)
18.3(.720) 19.8(.780)

0.50(.020)
0.25(.010)
BSC 7.50(.295) 0.15(.006)
REF

8.20(.323)
7.80(.307) 1.20(.047) MAX

0.15(.006)
0.05(.002)
0 0.20(.008)
5 REF
0.10(.004)

0.70(.028)
0.50(.020)

*Controlling dimension: millimeters

12 AT29C040A
 Atmel Headquarters Atmel Operations
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1-(408) 441-0732
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© Atmel Corporation 2001.

Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty
which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors
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® ™
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0333G–03/01/xM