CHAPTER 6

NON-VOLATILE SEMICONDUCTOR
MEMORY (NVSM)
 For all modern electronic systems, there are two most
important electronic devices:
 The transistor (MOSFET) for logic and volatile memory circuits.

 The NVSM for long-term storage of code and data

 In this chapter we consider:

 The floating gate concept of NVSM

 Historical development of the floating gate NVSM

 Applications of NVSM

 Scaling challenges

 Alternate non-volatile-memory structures

 HISTORICAL DEVELOPMENT OF
FLOATING-GATE NVSM
YEAR DEVICE INVENTOR(S)/AUTHOR(S) ORGANIZATION

1967 Floating-Gate Concept D. Kahng, S.M. Sze Bell Labs

1971 EPROM-FAMOS D. Frohman-Bentchkowsky Intel
1976 EEPROM-SAMOS H. Iizuka et al. Toshiba
1984 Flash Memory F. Masuoka et al. Toshiba
1985 FLOTOX Transistor S.K. Lai et al Intel
1985 NOR Flash F. Masuoka et al. Toshiba
1987 NAND Flash F. Masuoka et al. Toshiba
1994 Room-Temperature K. Yano et al. Hitachi
Single-Electron Transistor
1995 Multilevel Cell M. Bauer et al. Intel
2010 Multi-layer integration S.J Whang et al. Hynix
2013 128 Gb 3b/cell G.Naso et al. Micron
NAND Flash
 UNIQUE FEATURES OF THE
FLOATING-GATE NVSM
 Long-term information storage without power supply (10-100 years)

 Lowest power consumption among all solid-state memories (1/100

of DRAM, 1/10 of HDD)

 Ultra-high density (~0.0002 μm2 /bit)

 Compatible with CMOS technology

 NVSM is the only solid-state memory that can provide “intelligence”

(i.e., pre-programmable and reprogrammable capabilities) with
minimal energy consumption.
 FLOATING GATE CONCEPT
 The floating-gate NVSM (non-volatile semiconductor memory) was
conceived in 1967.

 The device looks like a conventional MOSFET but with one essential
difference --- the addition of a metal layer embedded inside the gate
oxide.

 There is no direct electrical contact to the embedded metal layer, its

potential is floating, thus the name “floating gate”.

 Since 1990, the floating gate NVSM has been the prime technology
driver of the largest industry in the world --- the electronics industry.
 FLOATING GATE CONCEPT(Cont.)

The NVSM has ushered in the Digital Age, and forever changed the
world we live in.

Shown below, M(1) is the floating gate which is sandwiched between a

tunnel oxide I(1) and a blocking oxide I(2).
 BASIC OPERATION OF NVSM
 Figure below shows energy band diagrams of a floating gate memory
device with a semiconductor-insulator-metal-insulator-metal sandwich.
(a) Programming mode, positive voltage is applied to the control gate. (b)
Storage mode, voltage is removed. (c) Erase mode, negative voltage is
applied to the control gate.

(VG > 0)

(VG = 0)

(VG < 0)
 BASIC OPERATION OF NVSM(CONT.)

 Programming Mode: a positive voltage (VG > 0) is applied to the

control gate M(2), electron transport across I(1) via Fowler-
Nordheim tunneling or hot electron injecting into the floating
gate.

 Storage Mode: If the insulator I(1) and I(2) are sufficiently thick,
the charge in the floating gate can be stored for a long time. Note,
in the storage mode, the applied voltage is removed. (VG = 0)

 Erase Mode : When a negative voltage (VG < 0) is applied to M(2),

electron can transport out of the floating gate via Fowler-
Nordheim tunneling.
 FIRST EXPERIMENTAL NVSM
 Device parameter : I(1) = 5 nm SiO2, I(2) = 100 nm ZrO2
𝝐𝝐𝟏𝟏ϵ 𝝐𝝐𝟐𝟐ϵ
1= 𝟑𝟑. 𝟗𝟗 𝐒𝐒𝐒𝐒𝐎𝐎 , 2= 𝟑𝟑𝟎𝟎 𝐙𝐙𝐙𝐙𝐎𝐎
𝝐𝝐𝟎𝟎ϵ0
= 3.9 (SiO 𝟐𝟐 2),
𝝐𝝐𝟎𝟎ϵ0
= 30 (ZrO 𝟐𝟐 2)

M(1) = 100 nm Zr, M(2) = Al gate

 VG = 50V, t1= 0.5 μs , 1012 electron/cm2 were transported to the floating gate.
 VT shift  device “on” with channel current of 0.25 mA
 VG = −50V, t1= 0.5μs, stored charge was depleted device “off”
 From the slope of the “on” state, the retention time is a few hundred
milliseconds.
 This is the first demonstration of the EEPROM (electrically erasable
programmable read-only memory) operation.

(a) (b)
 FOWLER-NORDHEIM
 FN tunneling is tunneling through a partial width of the barrier :

𝟐𝟐
𝑩𝑩
𝑱𝑱𝒕𝒕 = 𝑨𝑨ℰ𝒐𝒐𝒐𝒐 𝐞𝐞𝐞𝐞𝐞𝐞 −
ℰ𝒐𝒐𝒐𝒐
where ℰ𝒐𝒐𝒐𝒐 is the electric field across the oxide
A = 1.25×106 A/V2
B = 233.5 MV/cm
} for thermal oxide
 FN tunneling is a strong function of the electric field.
A 50% change in ℰ𝒐𝒐𝒐𝒐 (6.6  9.9 MV/cm) will cause an eight orders of
magnitude increase in current density (10-9  10-1 A/cm2)

Jt
EF

EF

oxide
 HOT-ELECTRON INJECTION
 Near the drain, the lateral field is at its highest level. The channel
electrons acquire energy from the field and become hot electrons.
High field also induces impact ionization. Some hot electrons with
energy > 3.2 eV will inject into the floating gate.
 Hot-electron injection is similar to the thermionic emission:
𝝋𝝋
𝑱𝑱 ~ ℰ 𝟐𝟐 𝐞𝐞𝐞𝐞𝐞𝐞 −
𝝀𝝀ℰ
Where ℰ = the maximum lateral field
λ = the inelastic scattering length ( ~5 nm)
φ = the barrier height between Si and SiO2 (~3.2eV)
 HE injection is also a strong function of the electric field.

8 10 12
𝑽𝑽(𝐕𝐕)
 PROGRAMMING MODE
 From Gauss’s law (assuming the voltage drop in the semiconductor is small):

𝝐𝝐𝟏𝟏 ℰ𝟏𝟏 = 𝝐𝝐𝟐𝟐 ℰ𝟐𝟐 + 𝑸𝑸 (4)

and 𝑽𝑽𝑮𝑮 = 𝑽𝑽𝟏𝟏 + 𝑽𝑽𝟐𝟐 = 𝒅𝒅𝟏𝟏 ℰ𝟏𝟏 + 𝒅𝒅𝟐𝟐 ℰ𝟐𝟐 (5)

where the subscript 1 and 2 correspond to the bottom and top oxide layer,𝑸𝑸
(negative) is the stored charge in the floating gate.

 From Eqs.4 and 5

𝑽𝑽𝑮𝑮 − 𝒅𝒅𝟏𝟏 ℰ𝟏𝟏 𝝐𝝐𝟐𝟐 𝑽𝑽𝑮𝑮 𝒅𝒅𝟏𝟏

𝝐𝝐𝟏𝟏 ℰ𝟏𝟏 = 𝝐𝝐𝟐𝟐 + 𝑸𝑸 = − 𝝐𝝐 ℰ + 𝑸𝑸
𝒅𝒅𝟐𝟐 𝒅𝒅𝟐𝟐 𝒅𝒅𝟐𝟐 𝟐𝟐 𝟏𝟏
PROGRAMMING MODE(Cont.)
𝒅𝒅𝟏𝟏 𝝐𝝐𝟐𝟐 𝑽𝑽𝑮𝑮
ℰ𝟏𝟏 𝝐𝝐𝟏𝟏 + 𝝐𝝐 = + 𝑸𝑸
𝒅𝒅𝟐𝟐 𝟐𝟐 𝒅𝒅𝟐𝟐
𝝐𝝐𝟐𝟐 𝑽𝑽𝑮𝑮
+ 𝑸𝑸 𝑽𝑽𝑮𝑮 𝑸𝑸
𝒅𝒅𝟐𝟐
∴ ℰ𝟏𝟏 = = − (𝟔𝟔)
𝒅𝒅 𝝐𝝐 𝒅𝒅𝟏𝟏
𝝐𝝐𝟏𝟏 + 𝟏𝟏 𝝐𝝐𝟐𝟐 𝒅𝒅𝟏𝟏 + 𝟏𝟏 𝒅𝒅𝟐𝟐 𝝐𝝐𝟏𝟏 + 𝝐𝝐
𝒅𝒅𝟐𝟐 𝝐𝝐𝟐𝟐 𝒅𝒅𝟐𝟐 𝟐𝟐

I(1) M(1) I(2) M(2)

Floating Gate Control Gate

Bottom Oxide Top Oxide

FN
Ec
EF
Ev Q
(VG > 0)
EF

d1 (𝝐𝝐1) d2 (𝝐𝝐2)
 PROGRAMMING MODE(Cont.)

 The stored charge 𝑸𝑸 (negative) is

𝒕𝒕 𝒕𝒕
𝑩𝑩
𝑸𝑸 = � 𝑱𝑱𝑱𝑱𝑱𝑱 = � 𝑨𝑨ℰ𝟏𝟏𝟐𝟐 𝐞𝐞𝐞𝐞𝐞𝐞 − 𝒅𝒅𝒅𝒅 for FN tunneling
𝟎𝟎 𝟎𝟎 ℰ𝟏𝟏

 When |𝑸𝑸| is small, ℰ𝟏𝟏 is given by the first term of Eq.6, J ≈ constant. Thus |𝑸𝑸|
varies linearly with the time. As |𝑸𝑸| increases, ℰ𝟏𝟏 will decrease, causing a
reduction of the FN current. For sufficiently long time, the current will drop
to zero, and |𝑸𝑸| approaches a steady value.
 PROGRAMMING MODE (Cont.)
 For example: Figure below shows the calculated charging current and stored
charge as a function of charging time.
at 𝒕𝒕 = 𝟏𝟏𝟎𝟎−𝟏𝟏𝟏𝟏 𝐬𝐬, 𝑱𝑱J == 𝟔𝟔 𝐀𝐀⁄𝐜𝐜𝐜𝐜𝟐𝟐 , 𝑸𝑸 = 𝟑𝟑 × 𝟏𝟏𝟎𝟎𝟗𝟗 𝐜𝐜𝐜𝐜𝐜𝐜𝐜𝐜𝐜𝐜𝐜𝐜𝐬𝐬/𝐜𝐜𝐦𝐦𝟐𝟐
at 𝒕𝒕 = 𝟏𝟏𝟎𝟎−𝟔𝟔 𝐬𝐬, J𝑱𝑱 == 𝟓𝟓 × 𝟏𝟏𝟎𝟎−𝟏𝟏 𝐀𝐀⁄𝐜𝐜𝐜𝐜𝟐𝟐 , 𝑸𝑸 = 𝟏𝟏𝟎𝟎𝟏𝟏𝟏𝟏 𝐜𝐜𝐜𝐜𝐜𝐜𝐜𝐜𝐜𝐜𝐜𝐜𝐬𝐬/𝐜𝐜𝐦𝐦𝟐𝟐
at 𝒕𝒕 = 𝟏𝟏𝟎𝟎−𝟓𝟓 𝐬𝐬, 𝑱𝑱 = 𝟓𝟓 × 𝟏𝟏𝟎𝟎−𝟐𝟐 𝐀𝐀⁄𝐜𝐜𝐜𝐜𝟐𝟐 ,𝑸𝑸 = 𝟏𝟏. 𝟓𝟓 × 𝟏𝟏𝟎𝟎𝟏𝟏𝟏𝟏 𝐜𝐜𝐜𝐜𝐜𝐜𝐜𝐜𝐜𝐜𝐜𝐜𝐬𝐬/𝐜𝐜𝐦𝐦𝟐𝟐
 THRESHOLD VOLTAGE SHIFT
 Figure 30 shows its drain-current characteristics of a stacked-gate n-
channel memory transistor, notice the change of threshold voltage after
erasing and programming.
 The stored charge in the floating gate will cause a threshold voltage shift

𝑸𝑸 𝑸𝑸 𝒅𝒅𝟐𝟐 |𝑸𝑸| (8)

∆𝑽𝑽𝑻𝑻 = − =
𝑸𝑸 + 𝝐𝝐 𝑸𝑸 = 𝒅𝒅𝟐𝟐 |𝑸𝑸|
∆𝑽𝑽𝑻𝑻 =𝑪𝑪𝑭𝑭𝑭𝑭
− = + 𝟐𝟐𝝐𝝐𝟐𝟐 = 𝝐𝝐𝟐𝟐
𝑪𝑪𝑭𝑭𝑭𝑭 𝝐𝝐𝟐𝟐
𝒅𝒅𝟐𝟐𝒅𝒅𝟐𝟐
where 𝑪𝑪𝑭𝑭𝑭𝑭 is the capacitance between the control gate and the floating
gate. The charge in the floating gate is like a fixed oxide charge(𝑸𝑸𝒇𝒇 ) at the
interface of M(1) and I(2).
 THRESHOLD VOLTAGE SHIFT (Cont.)

 The 𝑽𝑽𝑻𝑻 shift can be measured directly as shown in the 𝑰𝑰𝑫𝑫 − 𝑽𝑽𝑮𝑮
plot. ∆𝑽𝑽𝑻𝑻 can also be measured from the drain conductance

𝐝𝐝𝐝𝐝 𝒁𝒁
= =𝐃𝐃𝒅𝒅𝒅𝒅
∵ 𝐠𝐠∵𝐃𝐃 𝒈𝒈 =𝑫𝑫 =𝝁𝝁𝒏𝒏𝒁𝒁𝑪𝑪𝝁𝝁𝒐𝒐𝒐𝒐𝑪𝑪(𝑽𝑽𝑮𝑮(𝑽𝑽− 𝑽𝑽𝑻𝑻 )
𝑫𝑫 𝒅𝒅𝑽𝑽𝑫𝑫 𝑳𝑳 𝒏𝒏 𝒐𝒐𝒐𝒐 𝑮𝑮 − 𝑽𝑽𝑻𝑻 )
𝒅𝒅𝑽𝑽𝑫𝑫 𝑳𝑳

The change in 𝑽𝑽𝑻𝑻 results in a change in 𝒈𝒈𝑫𝑫

 To erase the 𝑸𝑸, a negative bias is applied to the control gate－the

reverse of programming process
 COUPLING RATIO
 For programing and erasing, 𝑽𝑽𝑮𝑮 must modulate the potential of the
floating gate, and a significant portion of 𝑽𝑽𝑮𝑮 must be coupled to the
floating gate capacitively.
 The coupling ratio is the ratio of 𝑽𝑽𝑭𝑭𝑭𝑭 (floating gate potential ) to the
control-gate voltage 𝑽𝑽𝑮𝑮 :
𝟏𝟏 𝟏𝟏

 𝑽𝑽𝑭𝑭𝑭𝑭 𝑹𝑹𝑪𝑪𝑪𝑪𝑽𝑽=
𝟏𝟏
𝑽𝑽𝑭𝑭𝑭𝑭
=
𝑽𝑽𝟏𝟏
𝑨𝑨𝟏𝟏=𝑪𝑪𝟏𝟏 𝟏𝟏 𝑨𝑨𝟏𝟏 𝑪𝑪𝟏𝟏
𝑨𝑨𝟐𝟐 𝑪𝑪𝟐𝟐
𝑹𝑹𝑪𝑪𝑪𝑪 = = 𝑽𝑽 𝑮𝑮 = 𝑽𝑽 𝟏𝟏 +𝑽𝑽 𝟐𝟐 + =
𝟏𝟏
𝑽𝑽𝑮𝑮 𝑽𝑽𝟏𝟏 + 𝑽𝑽𝟐𝟐 𝟏𝟏 𝑨𝑨𝟏𝟏 𝑪𝑪𝟏𝟏
𝟏𝟏 𝑨𝑨𝟐𝟐 𝑪𝑪𝟐𝟐 𝑨𝑨 𝑪𝑪 + 𝑨𝑨 𝑪𝑪
𝟏𝟏 𝟏𝟏 𝟐𝟐 𝟐𝟐
+
𝑨𝑨𝟏𝟏 𝑪𝑪𝟏𝟏 𝑨𝑨𝟐𝟐 𝑪𝑪𝟐𝟐

where 𝑨𝑨𝟏𝟏 , 𝑨𝑨𝟐𝟐 are the areas of the capacitances,

𝝐𝝐𝒐𝒐𝒐𝒐 𝑽𝑽𝑮𝑮 𝑽𝑽𝑮𝑮
𝑪𝑪𝟏𝟏 =
𝒅𝒅𝟏𝟏
𝝐𝝐𝒐𝒐𝒐𝒐 𝒅𝒅𝟐𝟐 𝑨𝑨𝟐𝟐 𝑪𝑪𝟐𝟐 𝑽𝑽𝟐𝟐
𝑪𝑪𝟐𝟐 =
𝒅𝒅𝟐𝟐 𝒅𝒅𝟏𝟏
𝒏𝒏+ 𝒏𝒏+ 𝑨𝑨𝟏𝟏 𝑪𝑪𝟏𝟏 𝑽𝑽𝟏𝟏
𝒑𝒑
 COUPLING RATIO (Cont.)
𝑨𝑨 𝑨𝑨𝟐𝟐
 Example, if 𝒅𝒅𝟏𝟏 = 𝟖𝟖 nm, 𝒅𝒅𝟐𝟐 = 𝟏𝟏𝟏𝟏 nm, 𝑨𝑨𝑨𝑨𝟏𝟏𝟏𝟏==𝟐𝟐𝟐𝟐
𝟐𝟐
𝝐𝝐𝒐𝒐𝒐𝒐
𝝐𝝐𝒐𝒐𝒐𝒐 𝟐𝟐𝑨𝑨𝟏𝟏 𝟏𝟏𝟏𝟏 𝟐𝟐
∴ 𝑹𝑹
𝟐𝟐𝑨𝑨𝟏𝟏 𝑪𝑪𝑪𝑪 = 𝝐𝝐𝒐𝒐𝒐𝒐 =
∴ 𝑹𝑹𝑪𝑪𝑪𝑪 = 𝟏𝟏𝟏𝟏 𝑨𝑨𝟏𝟏 𝝐𝝐𝒐𝒐𝒐𝒐 𝟐𝟐𝑨𝑨𝟏𝟏𝟏𝟏𝟏𝟏
= + = 𝟎𝟎. 𝟓𝟓𝟓𝟓
𝑨𝑨𝟏𝟏 𝝐𝝐𝒐𝒐𝒐𝒐 𝟐𝟐𝑨𝑨𝟏𝟏 𝝐𝝐𝒐𝒐𝒐𝒐𝟖𝟖 𝟏𝟏 𝟏𝟏𝟏𝟏 𝟐𝟐
+
𝟖𝟖 + 𝟏𝟏𝟏𝟏 𝟖𝟖 𝟏𝟏𝟏𝟏

Therefore 𝑽𝑽𝑭𝑭𝑭𝑭 = 𝟎𝟎. 𝟓𝟓𝟓𝟓𝑽𝑽𝑮𝑮

(i.e., 53% of control-gate voltage is coupled to the floating gate)

 Typical coupling rate is 𝟎𝟎. 𝟓𝟓~. 𝟎𝟎. 𝟔𝟔

 RETENTION TIME
 For non-volatile memory operation, long retention time is required.
The retention time 𝝉𝝉 is defined as the time when the stored charge
decreases to 50% of its initial value:
𝒕𝒕𝒕𝒕
−
−𝒕𝒕𝒕𝒕
𝑸𝑸
𝑸𝑸 𝒕𝒕𝒕𝒕 =
= 𝑸𝑸
𝑸𝑸𝒐𝒐𝒐𝒐𝒆𝒆𝒆𝒆 𝒐𝒐𝒐𝒐
were 𝟏𝟏 𝒕𝒕 = 𝒒𝒒∅𝟏𝟏𝑩𝑩𝒆𝒆
where 𝒕𝒕𝒐𝒐 = 𝐞𝐞𝐞𝐞𝐞𝐞
𝒐𝒐 𝒗𝒗
𝒗𝒗 𝒌𝒌𝒌𝒌

𝒗𝒗 = dielectric relaxation frequency

∅𝑩𝑩 = the barrier height of the floating gate to oxide

𝑸𝑸(𝒕𝒕) 𝟏𝟏 −𝝉𝝉
= = 𝒆𝒆 𝒕𝒕𝒐𝒐
𝑸𝑸𝒐𝒐 𝟐𝟐
𝒍𝒍𝒍𝒍 𝟐𝟐 𝒒𝒒∅𝑩𝑩
∴ 𝝉𝝉 = (𝒍𝒍𝒍𝒍 𝟐𝟐) 𝒕𝒕𝒐𝒐 = 𝐞𝐞𝐞𝐞𝐞𝐞 as T↑ , 𝝉𝝉↓
𝒗𝒗 𝒌𝒌𝒌𝒌
 RETENTION TIME (Cont.)

 Figure below shows the normalized charge storage versus time

for two ambient temperatures.
Example : At 125 °C 𝝉𝝉 = 𝟏𝟏𝟏𝟏𝟏𝟏 years
At 170 °C 𝝉𝝉 = 𝟏𝟏 year.
 HISTORICAL DEVELOPMENT OF FG NVSM
FAMOS (EPROM)
 FAMOS (floating-gate avalanche-injection MOS) : This is an EPROM
(erasable programmable read-only memory) developed in 1971.
 FAMOS had a floating gate but no control gate.
• stored charge came from hot electrons generated at the avalanche
region near the drain, then injected over the Si − SiO2 barrier.
 The stored charge can not be erased electrically, it requires UV light to
do the erasing.
 EPROM had an 80% world NVSM market share until 1990. By late 1990,
EPROM was totally supplanted by Flash memory.
 SAMOS (EEPROM)
 SAMOS (stacked gate avalanche injection MOS) : This is an EEPROM
(electrically erasable programmable read-only memory) developed in 1976.
 SAMOS had both the control gate and the floating gate. It is similar to the
first NVSM proposed in 1967. However, SAMOS used avalanche injection
instead of Fowler-Nordheim tunneling process.
 Because of the relatively thick oxide I(1), a substantial improvement of the
retention time was obtained
 EEPROM operation requires two devices per cell, i.e., an EEPROM and a
selection MOSFET. Therefore, the cell size is relativity large.
 EEPROM had a NVSM market share about 20% before 1990. At present, it’s
market share has been reduced to about 2%.
 FLASH MEMORY
 Flash memory was developed in 1984(shown below)
 Along 𝐀𝐀 − 𝐀𝐀′ section, it is the basic floating gate configuration.
Along 𝐁𝐁 − 𝐁𝐁′ section, an erase gate is added to facilitate the erase operation.
 The erase gate is connected to many cells in series. When a voltage is applied
to the erase gate, a whole block of memory cells is erased simultaneously, thus
the named “Flash”.
 Advantages of Flash memory : high density, lower cost.
 FLOTOX TRANSISTOR
 FLOTOX (Floating gate tunnel oxide) transistor confines the
tunneling process to a small area over the drain, shown below
 Typical programing and erasing transients for a FLOTOX
transistor are also shown below . For example to reach ∆𝑽𝑽𝑻𝑻 = 𝟐𝟐V
with 𝑽𝑽𝑮𝑮 = 𝟏𝟏𝟏𝟏V, the program time is 𝟓𝟓 × 𝟏𝟏𝟎𝟎−𝟓𝟓 s.
 NOR AND NAND FLASH

 NOR and NAND Flash memory were proposed in 1985 and 1987,
respectively.

 In NOR Flash, each cell is directly connected to the word line

and the bit line of the memory array – it offers faster random
access. Its basic unit is one memory device.

 In NAND Flash, cells are arranged in series within small

block(e.g., 16 cells as shown below).It has higher packing
density than NOR Flash.
 NOR AND NAND FLASH(Cont.)

 Figure below shows (a) NOR architecture with a basic unit of one
memory device. (b) NAND architecture with a basic unit of 16 memory
devices and 2 select transistors. The basic unit can be extended to 32 or
64 devices.
 NOR AND NAND CIRCUITS
 NOR (A,B transistors in parallel, when both A,B are off, A + B →VDD ,
otherwise, A + B →0)
VDD A B A+B
1 0 0

A
0 1 0
A+B A+B
B
1 1 0
A B 0 0 1

 NAND (A,B transistors in series, when both A,B are on, A∙B →0, otherwise,
A∙B →VDD )
VDD
A B A+B
A 1 0 1
A∙B B A∙B
0 1 1
A
0 0 1
B
1 1 0
 MULTI – LEVEL CELLS
 Multi-level cell (MLC) was proposed in 1995. It allows multiple bits to be
stored per cell.
 MLC provided higher density than the conventional single-level cell(SLC).
 For SLC, to read a bit, only a single comparison with a reference voltage
is required.
 For MLC with 2 bits per cell, three 𝑽𝑽𝐓𝐓 ’s are required.
 Figure below shows the voltage distributions for (a) single-level cell with
1bit/cell, and (b) multi-level cell with 2 bits/cell.
 MULTI-CHIP STACKING
● To increase the number of memory cells, and to reduce cost of memory
cells per package, 3D structures are proposed.
● One approach is multi-chip stacking with through silicon via (TSV)
technology.
● 1 tera-bit (1012 bits) solid- state drive(SSD) can be made, which consists of
32 stacked NAND Flash chips each having 32 Gb.
● The foot print is only 2.52 cm2 (15 times smaller than a planar 1 Tb SSD).
 MULTI-LAYER INTEGRATION
 Another approach is multi-layer integration.

 One example is the 3D dual control gate with surrounding

floating gate NAND Flash, shown below (a) Cross-sectional
view.(b) A bird’s eye view of one section.

 The tunnel oxide is perpendicular to the blocking oxide, instead

of parallel to it as in a conventional cell design.

 It has negligible floating-gate to floating gate interference due to

the control gate shield effect.

 1 terabit NAND Flash can be made with an effective cell size of

130 nm2 and 3 bits per cell (MLC), with a 63 cells multi-layer
dual control gate/surrounding floating gate structure.
MULTI-LAYER INTEGRATION (Cont.)
 MARKET SHARE OF NVSM DEVICES
 Today, the principal NVSM products are EEPROM, NOR Flash and NAND Flash.
 EEPROM is used where bit alterability is required
NOR Flash for code storage
NAND Flash for high-volume data storage
 NAND Flash will reach 90% market share in 2020 due to high-volume storage
demand for MP3, digital camera , solid–state drive and cloud computing.
 APPLICATIONS
 NVSM’s attributes: non-volatility, in-system rewritable, ruggedness,
high density, low power consumption, small form factor, and low cost.
 NAND Flash’s cost has dropped from $600,000/GB in 1987( for 256 kb
SLC) to $1.0/GB in 2010( for 64 Gb MLC), shown below.
 NAND –Flash-based solid-state drive is now replacing HDD in ultrabook
computer.
 Figure below shows the cost per gigabyte(GB) of magnetic hard disk
drive(HDD) and NAND Flash from 1985 to 2011, and projected to 2020.
The cost/GB for NAND Flash may become equal or less than that of
HDD around year 2015.
 APPLICATIONS (Cont.)
 Communications
Cellular Phone, Cordless, Bluetooth, Pagers, Modems, Internet Appliance, Line Card,
PBX, Set Top Box, LAN Modules, Network System, Network Adapters, Data
Communication.
 Computer and Peripheral
PC, Flash-Drive Notebook, USB Drive, Personal Digital Assistant, Solid-State Drive,
Portable DVD, Graphics Card, FAX, Printer.
 Consumer
Digital Camera, Digital Voice Recorder, MP3 Music Player, Digital Camcorder, Digital TV,
Directories, Bar-code Reader, Smart IC Card.
 Transportation
Automotive System, Global Positioning System (Auto, Marine, Aviation), ABS (anti-lack
braking system), Air Bag, Electronic Toll.
 Industrial
Meter, Sensing Device, Embedded System, POS, Servo Control, Motor Control,
Robotics.
 As shown in Ch.𝟎𝟎, the penetration rate of NVSM in electronic systems is
now 100%, i.e., every modern electronic system needs NVSM to perform
its function, either as a standalone non-volatile memory or as an
imbedded memory on the system core chip.
 APPLICATION (Cont.)
 The annual production of some selected electronic systems is
shown below.

 The most rapid increase of the digital cellular phone — since

1990, the volume of production has increased by 300 times (i.e.,
from 5 million units/year to 1.5 billion units/year) (the digital
cellular phone is considered the most useful invention of all
time!)*

 NVSM-based technology also has wide-range applications in

automation(laser printer), automobile (GPS,ABS),
commerce( smart IC card), healthcare( portable defibrillator),
household applications ( microwave oven), and
machinary( motor control).
* J.Kluger, ” the Spark of Invention”, TIME, p.84-91, New York ,Nov 25, 2013.
APPLICATION (Cont.)
 SCALING SHALLENGES
 Half pitch decreases rapidly from 360 nm in 1995 to 24 nm in 2011.
It may reach 11nm around 2020( shown below). By 2020, the half pitch may
reach 11nm.
 The scaling challenges include
 Retention (i.e., the ability to retain the information for 10 to 20 years) will

require a tunnel oxide of 6-7nm. This requirement makes it difficult to improve

the programming/erase speed, or to reduce the applied voltage.
 SCALLING CHANGES (Cont.)
 Endurance ( i.e., the number of program/erase cycles a memory device is
able to perform) is limited by the generation of traps and charge trapping
in the tunnel oxide during the high-field programing and erasure
operation. Typically the endurance is 105 ~106 cycles for SLC. 103 ~104 for
MLC (2 bites/ cell).
 Interference of neighboring cells causing cell-to-cell talks, 𝑽𝑽𝑻𝑻 shift.
 Reduction of coupling ratio (i.e., the ratio of 𝑪𝑪𝑭𝑭𝑭𝑭 to the total capacitance)
due to parasitic capacitances as the cell-to-cell spacing is reduced.
 Reduction of number of electrons in the floating gate. At 20nm, there are
about 10 electrons, so a reduction of one electron will cause a significant
change in 𝑽𝑽𝑻𝑻 .
 Dielectric leakage which will cause retention problem.
 Variability of 𝑵𝑵𝑨𝑨 , line edge roughness, and gate granularity which will
affect device performance and reliability.
 Random telegraph noise (RTN) due to capture and emission of a channel
electron by a single tunnel oxide trap near the substrate surface. RTN
will cause drain current fluctuation and 𝑽𝑽𝑻𝑻 shift—∆𝑽𝑽 𝒒𝒒 𝟏𝟏�𝟏𝟏𝑪𝑪�𝑭𝑭𝑭𝑭𝑪𝑪 + 𝟏𝟏+�𝑪𝑪𝟏𝟏𝑭𝑭𝑭𝑭�𝑪𝑪
∆𝑽𝑽𝑻𝑻𝑻𝑻 ==𝐪𝐪( )
𝑭𝑭𝑭𝑭 𝑭𝑭𝑭𝑭
As the device size decrease, 𝑪𝑪𝑭𝑭𝑭𝑭 and 𝑪𝑪𝑭𝑭𝑭𝑭 are reduced causing a large 𝑽𝑽𝑻𝑻
shift which will affect the readout operation.
 ALTERNATIVE DEVICE STRUCTURES
 There are two approaches to the alternative memory
structure
 Changing the change-storage materials, but retaining the

basic MOS structures and the storage principle

1.Floating-trap device
2.Nano-floating-gate device

 Proposing new device concepts without using the

storage principle, the so-called unified memories include
1.FRAM
2.PCRAM
3.RRAM
4.STT-MRAM
5.etc.
 FLOATING-TRAP( Charge-Trapping) DEVICES
 MNOS( metal-nitride-oxide-semiconductor)—It is similar to a floating
gate memory device except the floating gate is replaced by a nitride
layer.
 electrons are trapped in the nitride layer close to the oxide-nitride-interface.
 the oxide is to provide a good interface to the semiconductor and to prevent
back-tunneling of the injected charge for better charge reflection.
 electrons tunnel through the trapezoidal oxide barrier, followed by a triangular
barrier in the nitride–a modified Fowler- Nordhelm transport. Electrons then
pass the nitride layer by Frenkle-Poole transport.
VG

VD
Gate

Si3N3
SiO2

n+ n+
p-si
 FLOATING –TRAP DEVICE (Cont.)
 Figure 33 shows the rewriting of MNOS memory.(a) Programming:
electrons tunnel through the oxide and are trapped in the nitride.(b)
Erasing: holes tunnel through the oxide to neutralize the trapped
electrons and tunneling of trapped electrons.

 Advantage of MNOS
 reasonable speed for programming and erase.

 superior radiation hardnees due to minimal oxide thickness and

no floating gate.
 FLOATING-TRAP DEVICE (Cont.)
 Drawbacks of MNOS
 Requires large programming and erasing voltages.

 Non-uniform 𝑉𝑉T from device to device.

 continuous loss of charge through the thin oxide.

 the programming current has to pass the entire channel region to uniformly

distribute the trapped charge throughout the channel

 At deca-nanometer require , the randomly distributed charges within the nitride

layer may cause a large fluctuation in 𝑉𝑉𝑇𝑇 and a deterioration of device reliability
 MONOS(metal-oxide-nitride-oxide-silicon) transistor- similar to MNOS except
the addition of a blocking oxide layer between the gate and the nitride layer.
 the blocking oxide is to prevent electron injection from the metal to the nitride

layer during erase operation.

 if the gate metal is replaced by polysilicon, it is called a SONOS. The MONOS
(and SONOS) has replaced the MNOS.
Gate
Oxide
Nitride
Oxide
n+ n+

p-si
 FLOATING-TRAP DEVICES (Cont.)
 𝑽𝑽𝑻𝑻 shift versus programming pulse width as shown below.
 𝑽𝑽𝑻𝑻 ’s variation is similar to that of a floating gate device. Initially 𝑽𝑽𝑻𝑻 increase
linearly with time. Eventually it saturates because when the negative charge
starts to built-up, the oxide field decrease and the modified FN tunneling
starts to limit the current.
 Total gate capacitance 𝟏𝟏 𝑪𝑪𝒐𝒐𝒐𝒐 𝑪𝑪𝒏𝒏
𝑪𝑪𝑮𝑮 = = (10)
𝟏𝟏⁄𝑪𝑪𝒏𝒏 + 𝟏𝟏⁄𝑪𝑪𝒐𝒐𝒐𝒐 𝑪𝑪𝒐𝒐𝒐𝒐 + 𝑪𝑪𝒏𝒏
𝝐𝝐 𝝐𝝐
where 𝑪𝑪𝒐𝒐𝒐𝒐
𝑪𝑪𝐨𝐨𝐨𝐨== 𝒐𝒐𝒐𝒐𝝐𝝐�𝒐𝒐𝒐𝒐𝒅𝒅𝒐𝒐𝒐𝒐 𝑪𝑪𝒏𝒏 ,=
⁄𝒅𝒅,𝒐𝒐𝒐𝒐 �𝒅𝒅𝝐𝝐𝒏𝒏𝒏𝒏 ⁄𝒅𝒅𝒏𝒏
𝑪𝑪𝒏𝒏 𝒏𝒏=
𝑸𝑸 (11)
∆𝑽𝑽𝑻𝑻 = −
𝑪𝑪𝒏𝒏
 To erase, a large negative bias is applied to the gate, Tunneling of holes from
the substrate can neutralize the trapped electrons.
 NANO-FLOATING-GATE DEVICE
 For nano-floating-gate device, the continuous floating gate is replaced by
an array of discrete nano-scale semiconductor or metal partices ( of the
order of 5-10nm in diameter)
 Charge storage in a distributed nano-floating-gate offers higher program/
erase speed and larger retention time.(A leakage from a single particle will
have minor effect on the overall stored charge).
 At deca-nanometer regime, we reach a limiting case of only one particle
under the control gate — a single electron memory cell (SEMC)

Nano-floating Gate
VG
(Nanocrystal)
VS VD

n+ n+

p-si
 SINGLE-ELECTRON MEMORY CELL (SEMC)

 The minimum energy of a single electron is

𝑪𝑪𝑽𝑽𝟐𝟐 𝑪𝑪 𝒒𝒒 𝟐𝟐 𝒒𝒒𝟐𝟐
𝑬𝑬 = = =
𝟐𝟐 𝟐𝟐 𝑪𝑪 𝟐𝟐𝟐𝟐

let E =1 eV, a capacitor has an oxide layer of 2 nm thick and an

area of 𝒍𝒍 × 𝒍𝒍, Then
𝑪𝑪 𝒒𝒒𝟐𝟐 𝒒𝒒 𝟏𝟏. 𝟔𝟔 × 𝟏𝟏𝟎𝟎−𝟏𝟏𝟏𝟏
= −𝟏𝟏𝟏𝟏
𝒍𝒍𝟐𝟐
𝑪𝑪 = = = = 𝟑𝟑. 𝟗𝟗 × 𝟖𝟖. 𝟖𝟖𝟖𝟖 × 𝟏𝟏𝟎𝟎 ×
𝟐𝟐𝟐𝟐 𝟐𝟐 𝟐𝟐 𝟐𝟐 × 𝟏𝟏𝟎𝟎−𝟕𝟕

∴ 𝒍𝒍𝒍𝒍== 𝟐𝟐.
𝟐𝟐. 𝟏𝟏
𝟏𝟏 ×
× 𝟏𝟏𝟏𝟏 −𝟕𝟕𝐜𝐜𝐜𝐜
𝟏𝟏𝟎𝟎−𝟕𝟕 cm≈≈𝟐𝟐nm
𝟐𝟐 𝐧𝐧𝐧𝐧 (almost a cube)
 SINGLE-ELECTRON MEMORY CELL (SEMC)
(Cont.)
Tunneling resistance

Power of a resistor: 𝑷𝑷𝑷𝑷==𝑰𝑰𝑰𝑰𝟐𝟐𝟐𝟐𝑹𝑹𝑹𝑹

𝒒𝒒 𝟐𝟐 𝒒𝒒𝟐𝟐 𝑹𝑹�
energy of a resistor: ∆𝑬𝑬
∆𝑬𝑬== 𝑰𝑰 𝑹𝑹∆𝒕𝒕== 𝑰𝑰𝟐𝟐𝟐𝟐𝑹𝑹∆𝒕𝒕 𝑹𝑹∆𝒕𝒕 = ∆𝒕𝒕
∆𝒕𝒕
∆𝒕𝒕
Uncentainly principle:
∆𝑬𝑬∆𝒕𝒕 > ℏ⁄𝟐𝟐
𝒉𝒉
∴ 𝒒𝒒𝟐𝟐 𝑹𝑹 >
4𝝅𝝅
𝒉𝒉 𝟔𝟔. 𝟔𝟔𝟔𝟔 × 𝟏𝟏𝟎𝟎−𝟑𝟑𝟑𝟑
𝑹𝑹 > = = 𝟐𝟐. 𝟎𝟎𝟎𝟎 𝐤𝐤𝐤𝐤
𝟒𝟒𝟒𝟒𝒒𝒒𝟐𝟐 𝟒𝟒𝝅𝝅 𝟏𝟏. 𝟔𝟔 × 𝟏𝟏𝟎𝟎−𝟏𝟏𝟏𝟏 𝟐𝟐

𝑹𝑹 > 𝟏𝟏𝟏𝟏𝟏𝟏 𝐤𝐤𝐤𝐤

 SINGLE-ELECTRON MEMORY(CONT.)
 By reducing the floating gate length to nm regime, we obtain SEMC.
Because of its small size, the capacitance is very small (~10−19 F).
 When an electron tunnels into the quantum well (floating gate), the
potential on the left side is reduced and the transfer of another electron is
blocked – the Coulomb Blockade.
 SEMC is an ultimate floating-gate memory cell.
 Note the SEMC band diagrams are similar to these shown in Fig.2.
 SEMC operation was demonstrated at 300 K in 1994.

EF
EF q
2C

(Before Filling) EF
(Coulomb Blockade) EF
 UNIFIED MEMORIES
 Unified memory : high speed, high density and nonvolatility (i.e., high
retention time)
 Current semiconductors memories
−6
 NVSM : high density, non-volatility, but speed is relatively low(~10 s,
for programing).
 DRAM : relatively high density, high speed (~10 ns ), but volatile.

 SRAM : very high speed(~5 ns ), low density and volatile.

Therefore, the unified memory has not been developed.

 EMERGING UNIFIED MEMORIES

 Many non-volatile memories have been proposal for the unified

memory. Here are a few candidates :
 FeRAM (ferroelectric random access memory) is based on the

remanent polarization in Perovskite materials.

 PCRAM (phase change RAM) is based on reverible phase

convertion between the amorphous and the crystalline state of

a chalcogenide glass, which is a accomplished by heating and
cooling of the glass.
 RRAM (resistance RAM) is based on change in resistance with

applied electric field. Resistance switching from low to high

resistance or other way around has been found in materials
such as lead zirconium titanate (PZT) and tantalum pentoxide
(Ta2 O5 )
 STT-MRAM (spin-torque transfer magnetic RAM) is based on

spin polarization that can be used to control the magnetic

orientation of layers in an MRAM cell.
 EMERGING UNFIED MEMORIES (Cont.)

FeRAM PCRAM

RRAM STT-MRAM
Classical floating-gate NVSM

 Most above candidates are two-terminal devices. It is a major

challenge to find the right material to meet the requirements of high
speed, high density, and nonvolatility.
 The materials must be compatible with the IC technology, since the
logic devices will be CMOS.
 SUMMARY OF CHAPER 6
 Since 1967, NVSM has grown from a floating-gate concept to
FAMOS, SAMOS, Flash memory, multi-level cell, and 3-dimentional
structure.

 Since 1990, NVSM-inspired technology has ushered in the Digital

Age, and enabled the development of all modern electronic
systems.

 To date, over 40 billion NVSM-based products were shipped, and

in 10 years, the cumulative units will reach 80 billion. Therefore on
average, every person in the world will have 10 such products.

 Many innovations are being made to overcome the scaling

challenges, and a unified memory may be developed to improve
system performances.