FPGA Based System Design

Reference

• Wayne Wolf, ‘FPGA-Based System Design’ Pearson

Education, 2004

N Krishna Prakash, Amrita School of Engineering

 Why VLSI?
 Integration improves the design:
 higher speed;
 lower power;
 physically smaller.
 Integration reduces manufacturing cost (almost) - no
manual assembly.

N Krishna Prakash, Amrita School of Engineering

Integrated Circuits

N Krishna Prakash, Amrita School of Engineering

 Full Custom ICs
 Can achieve very high transistor density (transistors per
square micron)
 design time can be very long (multiple months).
 Involves the creation of a completely new chip, which
consists of masks (for the photolithographic manufacturing
process)
 Benefits - Excellent performance, small size, low power

N Krishna Prakash, Amrita School of Engineering

 Standard Cell
 Designer uses a library of standard cells
 an automatic place and route tool does the layout
 Transistor density and performance degradation depends
on type of design being done.
 Design time can be much faster than full custom because
layout is automatically generated.

N Krishna Prakash, Amrita School of Engineering

 Gate Array
 Designer uses a library of standard cells.
 The design is mapped onto an array of transistors which is
already created on a wafer
 wafers with transistor arrays can be created ahead of time
 A routing tool creates the masks for the routing layers and
"customizes" the pre-created gate array for the user's
design
 Transistor density can be almost as good as standard cell.
 Design time advantages are the same as for standard cell.

N Krishna Prakash, Amrita School of Engineering

Semi-custom ICs
 Flexible as portion of the IC is customized by the user
 Suitable for specific applications
 Gate array + standard cell
 Paves way for application specific ICs (ASIC)

N Krishna Prakash, Amrita School of Engineering

 Role of FPGA
 Microprocessors used in variety of environments
 Rely on software to implement functions

 Generally slower and more power-hungry than custom

chips
 When FPGAs?
 Design economics

 Shortest time to market

 Lowest NRE cost
 Highest unit cost
 Make quick grab for market share
 Same FPGA reused in several designs

N Krishna Prakash, Amrita School of Engineering

Programmable logic devices
 Programmable Logic Device (PLD):
 An integrated circuit chip that can be configured by

end user to implement different digital hardware

 Also known as “Field Programmable Logic Device

(FPLD) “

N Krishna Prakash, Amrita School of Engineering

 PLD
 PLD as a Black Box

Logic gates
Inputs and Outputs
(logic variables) programmable (logic functions)
switches

N Krishna Prakash, Amrita School of Engineering

 Programmable Logic Array (PLA)
x1 x2 xn

 Use to implement
circuits in SOP form
Input buffers
and
 The connections in inverters
the AND plane are
x1 x1 xn xn
programmable
P1
 The connections in
the OR plane are AND plane OR plane
Pk
programmable

N Krishna Prakash, Amrita School of Engineering f1 fm

 Gate Level Version of PLA
x1 x2 x3

Programmable
connections

f1 = x1x2+x1x3'+x1'x2'x3 OR plane
P1

f2 = x1x2+x1'x2'x3+x1x3
P2

P3

P4

AND plane
N Krishna Prakash, Amrita School of Engineering
f1 f2
 Customary Schematic of a PLA
x1 x2 x3

OR plane
f1 = x1x2+x1x3'+x1'x2'x3
P1
f2 = x1x2+x1'x2'x3+x1x3
P2

P3

P4

x marks the connections left in AND plane

place after programming
N Krishna Prakash, Amrita School of Engineering
f1 f2
 Limitations of PLAs
 Typical size is 16 inputs, 32 product terms, 8 outputs
 Each AND gate has large fan-in - this limits the number
of inputs that can be provided in a PLA
 16 inputs  216 = possible input combinations; only 32
permitted (since 32 AND gates) in a typical PLA
 32 AND terms permitted  large fan-in for OR gates as
well

 This makes PLAs slower and slightly more expensive than

some alternatives to be discussed shortly
N Krishna Prakash, Amrita School of Engineering
Programmable ROM (PROM)

N input N M output
2 xM
ROM

Address: N bits; Output word: M bits

N
ROM contains 2 words of M bits each

The input bits decide the particular word that becomes available
on output lines

N Krishna Prakash, Amrita School of Engineering

16
Logic Diagram of 8x3 PROM

Sum of minterms
N Krishna Prakash, Amrita School of Engineering

17
Combinational Circuit Implementation
using PROM

I0 I1 I2 F0 F1 F2
0 0 0 1 0 0
0 0 1 0 1 0
0 1 0 0 1 1
0 1 1 1 0 0
1 0 0 0 1 0
1 0 1 0 0 1
1 1 0 1 0 0
1 1 1 0 1 0 F0 F1 F2

N Krishna Prakash, Amrita School of Engineering

18
PROM Types
 Programmable PROM
 Break links through current pulses

 Write once, Read multiple times

 Erasable PROM (EPROM)

 Program with ultraviolet light

 Write multiple times, Read multiple times

 Electrically Erasable PROM (EEPROM)/ Flash

Memory
 Program with electrical signal

 Write multiple times, Read multiple times

N Krishna Prakash, Amrita School of Engineering

19
PROM: Advantages and Disadvantages
 Widely used to implement functions with large number
of inputs and outputs

 For combinational circuits with lots of don’t care terms,

PROM is a wastage of logic resources

N Krishna Prakash, Amrita School of Engineering

20
 Programmable Array Logic (PAL)
x1 x2 xn

 Also used to implement

circuits in SOP form
Input buffers
and
inverters fixed connections
 The connections in
the AND plane are x1 x1 xn xn
programmable
P1
 The connections in
the OR plane are AND plane OR plane
Pk
NOT programmable

f1 fm
N Krishna Prakash, Amrita School of Engineering
 Example Schematic of a PAL
x1 x2 x3

f1 = x1x2x3'+x1'x2x3
P1
f2 = x1'x2'+x1x2x3
f1
P2

P3

f2
P4

AND plane
N Krishna Prakash, Amrita School of Engineering
 Comparing PALs and PLAs

 PALs have the same limitations as PLAs (small number of

allowed AND terms) plus they have a fixed OR plane  less
flexibility than PLAs

 PALs are simpler to manufacture, cheaper, and faster (better

performance)

 PALs also often have extra circuitry connected to the output

of each OR gate
 The OR gate plus this circuitry is called a macrocell

N Krishna Prakash, Amrita School of Engineering

 Macrocell
Select
Enable
OR gate from PAL 0
f1
1

D Q
Flip-flop
Clock

back to AND plane

N Krishna Prakash, Amrita School of Engineering

 Macrocell Functions

 Enable = 0 can be used to allow the output pin for f1 to be

used as an additional input pin to the PAL
Select
Enable
 Enable = 1, Select = 0 is normal 0
for typical PAL operation f1
1

D Q
 Enable = Select = 1 allows Clock
the PAL to synchronize the
output changes with a clock
back to AND plane
pulse

 The feedback to the AND plane provides for multi-level design

N Krishna Prakash, Amrita School of Engineering

 Multi-Level Design with PALs

 f = A'BC + A'B'C' + ABC' + AB'C = A'g + Ag'

 where g = BC + B'C' and C = h below
A B

Sel = 0
En = 0
0
1
h

D Q
Sel = 0
Clock En = 1
0
g
1

D Q
Select
Clock
0
f
1

D Q

Clock
N Krishna Prakash, Amrita School of Engineering
 FPGA Programming
 FPGAs implement multi-level logic
 Need both programmable logic blocks
and programmable interconnect
 Combination of logic and interconnect
is fabric

 Microprocessor is a stored-program
computer

N Krishna Prakash, Amrita School of Engineering

Moore’s Law
 Gordon Moore: co-founder of Intel.
 Predicted that number of transistors per chip would
grow exponentially (double every 18 months).

N Krishna Prakash, Amrita School of Engineering

Mask cost Vs technology line width

1,000,000
900,000
800,000
700,000
600,000
500,000
mask cost ($)
400,000
300,000
200,000
100,000
0
.25 micron .18 micron .13 micron .09 micron

N Krishna Prakash, Amrita School of Engineering

Goals and Techniques
 Performance
 Logic rate

 Power/energy
 Design time
 Design cost
 FPGA tools less expensive than custom VLSI tools

 Manufacturing cost

N Krishna Prakash, Amrita School of Engineering

Design Challenges
 Multiple levels of abstraction

 Power consumption

 Short design time

N Krishna Prakash, Amrita School of Engineering

 FPGA Abstractions

English specification
Executable Throughput,
program behavior design time

register- Function units,

function Sequential clock cycles cost
transfer
machines
Literals,
Logic gates logic logic depth

transistors circuit nanoseconds

rectangles layout microns

N Krishna Prakash, Amrita School of Engineering

 Top-down design adds functional detail.
 Create lower levels of abstraction from upper

levels.
 Bottom-up design creates abstractions from low-level
behavior.
 Good design needs both top-down and bottom-up
efforts.

N Krishna Prakash, Amrita School of Engineering

Methodology
 Hardware Description logic (HDL)
 VHDL

 VerilogHDL

N Krishna Prakash, Amrita School of Engineering

Major FPGA Vendors
 SRAM-based FPGAs
 Xilinx, Inc
Share 80% of the market
 Altera Corp.

 Atmel

 Lattice Semiconductor

 Flash & Antifuse FPGAs

 Actel Corp.

 Quick logic Corp.

N Krishna Prakash, Amrita School of Engineering

FPGA Vendors and Device families
 Xilinx
 Spartan

 Virtex

 Kintex

 Artix

 Altera
 Stratix

 Cyclone

 MAX 3000/7000 CPLD

 MAX-II

N Krishna Prakash, Amrita School of Engineering

Xilinx Families

N Krishna Prakash, Amrita School of Engineering

Altera Families

N Krishna Prakash, Amrita School of Engineering