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TP4-Información Adjunta

This document contains information about switch symbols and a microcontroller program connected to a 4x4 keypad matrix with interrupt handling and an 8-digit display. It includes configuration bits for the microcontroller, macros and subroutines for displaying digits on the 7-segment display, an interrupt service routine to read the keypad and increment a displayed value, and initialization routines.
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0% found this document useful (0 votes)
22 views11 pages

TP4-Información Adjunta

This document contains information about switch symbols and a microcontroller program connected to a 4x4 keypad matrix with interrupt handling and an 8-digit display. It includes configuration bits for the microcontroller, macros and subroutines for displaying digits on the 7-segment display, an interrupt service routine to read the keypad and increment a displayed value, and initialization routines.
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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SÍMBOLOS DE LOS SWITCHS

Seleccionar según la penúltima cifra del CUI del delegado

0 1

1 2 3 A A 1 2 3

4 5 6 B B 4 5 6

7 8 9 C C 7 8 9

E 0 F D D E 0 F

2 3

1 4 7 E A B C D

2 5 8 0 1 4 7 E

3 6 9 F 2 5 8 0

A B C D 3 6 9 F
4 5

E 7 4 1 D C B A

0 8 5 2 E 7 4 1

F 9 6 3 0 8 5 2

D C B A F 9 6 3

6 7

E 0 F D D E 0 F

7 8 9 C C 7 8 9

4 5 6 B B 4 5 6

1 2 3 A A 1 2 3
8 9

1 4 7 F D C B A

2 5 8 0 1 4 7 F

3 6 9 E 2 5 8 0

D C B A 3 6 9 E

PROGRAMA AFÍN
; ************************************************************************
; TRABAJO PRÁCTICO 4
; Conexión del Microcontrolador con el Teclado Matricial 4x4
; con gestión por interrupción y con un display de 8 dígitos
; ************************************************************************
#INCLUDE "P18F4550.INC"

; CONFIG1L
CONFIG PLLDIV = 1 ; PLL Prescaler Selection bits
;(No prescale (4 MHz oscillator input drives PLL directly))
CONFIG CPUDIV = OSC1_PLL2 ; System Clock Postscaler Selection bits ([Primary Oscillator
;Src: /1][96 MHz PLL Src: /2])
CONFIG USBDIV = 1 ; USB Clock Selection bit (used in Full-Speed USB mode only; UCFG:FSEN = 1)
; (USB clock source comes directly from the primary oscillator block with no postscale)

; CONFIG1H
CONFIG FOSC = XT_XT ; Oscillator Selection bits (XT oscillator (XT))
CONFIG FCMEN = OFF ; Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor disabled)
CONFIG IESO = OFF ; Internal/External Oscillator Switchover bit (Oscillator Switchover mode disabled)

; CONFIG2L
CONFIG PWRT = OFF ; Power-up Timer Enable bit (PWRT disabled)
CONFIG BOR = ON ; Brown-out Reset Enable bits (Brown-out Reset enabled in hardware only (SBOREN is disabled))
CONFIG BORV = 3 ; Brown-out Reset Voltage bits (Minimum setting 2.05V)
CONFIG VREGEN = ON ; USB Voltage Regulator Enable bit (USB voltage regulator enabled)

; CONFIG2H
CONFIG WDT = OFF ; Watchdog Timer Enable bit (WDT disabled (control is placed on the SWDTEN bit))
CONFIG WDTPS = 32768 ; Watchdog Timer Postscale Select bits (1:32768)

; CONFIG3H
CONFIG CCP2MX = ON ; CCP2 MUX bit (CCP2 input/output is multiplexed with RC1)
CONFIG PBADEN = OFF ; PORTB A/D Enable bit (PORTB<4:0> pins are configured as digital I/O on Reset)
CONFIG LPT1OSC = OFF ; Low-Power Timer 1 Oscillator Enable bit (Timer1 configured for higher power operation)
CONFIG MCLRE = ON ; MCLR Pin Enable bit (MCLR pin enabled; RE3 input pin disabled)

; CONFIG4L
CONFIG STVREN = ON ; Stack Full/Underflow Reset Enable bit (Stack full/underflow will cause Reset)
CONFIG LVP = OFF ; Single-Supply ICSP Enable bit (Single-Supply ICSP disabled)
CONFIG ICPRT = OFF ; Dedicated In-Circuit Debug/Programming Port (ICPORT) Enable bit (ICPORT disabled)
CONFIG XINST = OFF ; Extended Instruction Set Enable bit (Instruction set extension and Indexed Addressing
;mode disabled (Legacy mode))

; CONFIG5L
CONFIG CP0 = OFF ; Code Protection bit (Block 0 (000800-001FFFh) is not code-protected)
CONFIG CP1 = OFF ; Code Protection bit (Block 1 (002000-003FFFh) is not code-protected)
CONFIG CP2 = OFF ; Code Protection bit (Block 2 (004000-005FFFh) is not code-protected)
CONFIG CP3 = OFF ; Code Protection bit (Block 3 (006000-007FFFh) is not code-protected)

; CONFIG5H
CONFIG CPB = OFF ; Boot Block Code Protection bit (Boot block (000000-0007FFh) is not code-protected)
CONFIG CPD = OFF ; Data EEPROM Code Protection bit (Data EEPROM is not code-protected)
; CONFIG6L
CONFIG WRT0 = OFF ; Write Protection bit (Block 0 (000800-001FFFh) is not write-protected)
CONFIG WRT1 = OFF ; Write Protection bit (Block 1 (002000-003FFFh) is not write-protected)
CONFIG WRT2 = OFF ; Write Protection bit (Block 2 (004000-005FFFh) is not write-protected)
CONFIG WRT3 = OFF ; Write Protection bit (Block 3 (006000-007FFFh) is not write-protected)

; CONFIG6H
CONFIG WRTC = OFF ; Configuration Register Write Protection bit (Configuration registers
;(300000-3000FFh) are not write-protected)
CONFIG WRTB = OFF ; Boot Block Write Protection bit (Boot block (000000-0007FFh) is not write-protected)
CONFIG WRTD = OFF ; Data EEPROM Write Protection bit (Data EEPROM is not write-protected)

; CONFIG7L
CONFIG EBTR0 = OFF ; Table Read Protection bit (Block 0 (000800-001FFFh)
;is not protected from table
;reads executed in other blocks)
CONFIG EBTR1 = OFF ; Table Read Protection bit (Block 1 (002000-003FFFh)
;is not protected from table reads executed in other blocks)
CONFIG EBTR2 = OFF ; Table Read Protection bit (Block 2 (004000-005FFFh)
;is not protected from table reads executed in other blocks)
CONFIG EBTR3 = OFF ; Table Read Protection bit (Block 3 (006000-007FFFh)
;is not protected from table reads executed in other blocks)

; CONFIG7H
CONFIG EBTRB = OFF ; Boot Block Table Read Protection bit (Boot block (000000-0007FFh)
;is not protected from table reads executed in other blocks)
;***************************************************************************
N100 EQU 0XA5
CONT100 EQU 0X20

UNIDAD EQU 0X21


DECENA EQU 0X22
CENTENA EQU 0X23
MILLAR EQU 0X24
DEC_MILLAR EQU 0X25
CEN_MILLAR EQU 0X26
MILLON EQU 0X27
DEC_MILLON EQU 0X28

W1 EQU 0X29
W2 EQU 0X2A
STATUS1 EQU 0X2B
STATUS2 EQU 0X2C
W3 EQU 0X2D
W4 EQU 0X2E
W5 EQU 0X2F

MOSTRAR_DIGITO MACRO DIGITO,ACTIVA_EN_A,ACTIVA_EN_E


MOVLW 0X00
MOVWF PORTA
MOVWF PORTE
MOVF DIGITO,0,1
CALL HEX_A_7SEG
MOVWF W3
COMF W3,W,1
MOVWF PORTD
MOVLW ACTIVA_EN_A
MOVWF LATA
MOVLW ACTIVA_EN_E
MOVWF PORTE
ENDM

ORG 0
GOTO PRINCIPAL
ORG 8
GOTO ISR
PRINCIPAL

BUCLE
MOSTRAR_DIGITO UNIDAD,0X01,0X00
CALL RETARDO
MOSTRAR_DIGITO DECENA,0X02,0X00
CALL RETARDO
MOSTRAR_DIGITO CENTENA,0X04,0X00
CALL RETARDO
MOSTRAR_DIGITO MILLAR,0X08,0X00
CALL RETARDO
MOSTRAR_DIGITO DEC_MILLAR,0X10,0X00
CALL RETARDO
MOSTRAR_DIGITO CEN_MILLAR,0X20,0X00
CALL RETARDO
MOSTRAR_DIGITO MILLON,0X00,0X02
CALL RETARDO
MOSTRAR_DIGITO DEC_MILLON,0X00,0X01
CALL RETARDO
GOTO BUCLE

HEX_A_7SEG
MOVWF W1
ADDWF W1,0,1
ADDWF PCL
RETLW B'00111111' ;0
RETLW B'00000110' ;1
ISR
MOVFF WREG,W2
MOVFF STATUS,STATUS1
BCF INTCON, RBIF;
CALL RETARDO;
CALL CODIF_BN;
MOVWF W4;
ANDLW 0X10;
BTFSS STATUS,Z;
BRA NO_HAY_TECLA;
CALL DESPLAZAR;
MOVF W4,0,1;
MOVWF UNIDAD,1;
NO_HAY_TECLA
MOVLW 0XF0;
MOVWF PORTB;
MOVF PORTB,W,0;
BCF INTCON, RBIF;
MOVFF STATUS1,STATUS
MOVFF W2,WREG
RETFIE

DESPLAZAR

RETURN
RETARDO
MOVFF WREG,W5
MOVFF STATUS,STATUS2
MOVLW N100
MOVWF CONT100
REPIT
DECFSZ CONT100,1,1
GOTO REPIT
MOVFF STATUS2,STATUS
MOVFF W5,WREG
RETURN

INITA

RETURN
INITE

RETURN
INITB

RETURN
INITD

RETURN
INITINT
RETURN
CODIF_BN
MOVLW 0XFE
MOVWF PORTB
BTFSS PORTB,4
RETLW 0X00
BTFSS PORTB,5
RETLW 0X01
BTFSS PORTB,6
RETLW 0X02
BTFSS PORTB,7
RETLW 0X03
MOVLW 0XFD
MOVWF PORTB
BTFSS PORTB,4
RETLW 0X04
BTFSS PORTB,5
RETLW 0X05
BTFSS PORTB,6
RETLW 0X06
BTFSS PORTB,7
RETLW 0X07
MOVLW 0XFB
MOVWF PORTB
BTFSS PORTB,4
RETLW 0X03
BTFSS PORTB,5
RETLW 0X06
BTFSS PORTB,6
RETLW 0X09
BTFSS PORTB,7
RETLW 0X0F
MOVLW 0XF7
MOVWF PORTB
BTFSS PORTB,4
RETLW 0X0A
BTFSS PORTB,5
RETLW 0X0B
BTFSS PORTB,6
RETLW 0X0C
BTFSS PORTB,7
RETLW 0X0D
RETLW 0X10

END

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