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integratedelectronicsUNIT 3converters

This document summarizes different types of analog to digital and digital to analog converters. It discusses sample and hold circuits, which sample analog signals for conversion. It describes digital to analog converters that use R-2R ladder networks or binary weighting. For analog to digital converters, it outlines flash converters, successive approximation converters, and dual slope converters. It provides functional diagrams and applications of phase locked loops.

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0% found this document useful (0 votes)
36 views11 pages

integratedelectronicsUNIT 3converters

This document summarizes different types of analog to digital and digital to analog converters. It discusses sample and hold circuits, which sample analog signals for conversion. It describes digital to analog converters that use R-2R ladder networks or binary weighting. For analog to digital converters, it outlines flash converters, successive approximation converters, and dual slope converters. It provides functional diagrams and applications of phase locked loops.

Uploaded by

Yogeshwaran
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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UNIT 3 PLL& A/D AND D/A CONVERTERS

Sample and Hold circuit, Digital to analog converters: R-2R ladder network and Binary weighted,
Analog to digital converters: Flash converter, Successive approximation converter, Dual slope,
Phase locked loop, Functional diagram description VCO IC LM 566, Applications, Frequency
multiplier, Frequency divider, Frequency synthesizer, AM detector and FM demodulator.

Sample and Hold Circuit

A Sample and Hold Circuit, sometimes represented as S/H Circuit or S & H Circuit, is usually
used with an Analog to Digital Converter to sample the input analog signal and hold the
sampled signal.
In the S/H Circuit, the analog signal is sampled for a short interval of time, usually in the range
of 1µS to 10µS. After this, the sampled value is hold until the arrival of next input signal to be
sampled. The duration for holding the sample will be usually between few milliseconds to few
seconds.
The following image shows a simple block diagram of a typical Sample and Hold Circuit.

Need for Sample and Hold Circuits


If the input analog voltage of an ADC changes more than ±1/2 LSB, then there is a
severe chance that the output digital value is an error. For the ADC to produce accurate results,
the input analog voltage should be held constant for the duration of the conversion.
As the name suggests, a S/H Circuit samples the input analog signal based on a
sampling command and holds the output value at its output until the next sampling command
is arrived. The following image shows the input and output of a typical Sample and Hold
Circuit
.

Digital to Analog Converter (DAC)

A Digital to Analog Converter (DAC) converts a digital input signal into an analog output signal.
The digital signal is represented with a binary code, which is a combination of bits 0 and 1.
The block diagram of DAC is shown in the following figure –

A Digital to Analog Converter (DAC) consists of a number of binary inputs and a single output. In
general, the number of binary inputs of a DAC will be a power of two.
Types of DACs
There are two types of DACs
 Weighted Resistor DAC
 R-2R Ladder DAC

Weighted Resistor DAC


A weighted resistor DAC produces an analog output, which is almost equal to the digital (binary) input
by using binary weighted resistors in the inverting adder circuit. In short, a binary weighted resistor
DAC is called as weighted resistor DAC.

The circuit diagram of a 3-bit binary weighted resistor DAC is shown in the following figure −
Let the 3-bit binary input is b1 b2 b3. Here, the bits b1 and b3 denote the Most Significant Bit (MSB)
and Least Significant Bit (LSB) respectively.
The digital switches shown in the above figure will be connected to ground, when the corresponding
input bits are equal to ‘0’. Similarly, the digital switches shown in the above figure will be connected
to the negative reference voltage, −VR when the corresponding input bits are equal to ‘1’.

In the above circuit, the non-inverting input terminal of an op-amp is connected to ground. That means
zero volts is applied at the non-inverting input terminal of op-amp.

According to the virtual short concept, the voltage at the inverting input terminal of opamp is same
as that of the voltage present at its non-inverting input terminal. So, the voltage at the inverting input
terminal’s node will be zero volts.

The nodal equation at the inverting input terminal’s node is:

The above equation represents the output voltage equation of a 3-bit binary weighted resistor DAC.
Since the number of bits are three in the binary (digital) input, we will get seven possible values of
output voltage by varying the binary input from 000 to 111 for a fixed reference voltage, VR.

We can write the generalized output voltage equation of an N-bit binary weighted resistor DAC as
shown below based on the output voltage equation of a n-bit binary weighted resistor DAC.

The disadvantages of a binary weighted resistor DAC are as follows −

 The difference between the resistance values corresponding to LSB & MSB will increase as
the number of bits present in the digital input increases.

 It is difficult to design more accurate resistors as the number of bits present in the digital input
increases.
R-2R Ladder DAC
The R-2R Ladder DAC overcomes the disadvantages of a binary weighted resistor DAC. As the name
suggests, R-2R Ladder DAC produces an analog output, which is almost equal to the digital (binary)
input by using a R-2R ladder network in the inverting adder circuit.

The circuit diagram of a 3-bit R-2R Ladder DAC is shown in the following figure −

Recall that the bits of a binary number can have only one of the two values. i.e., either 0 or 1. Let the 3-
bit binary input is b1 b2 b3. Here, the bits b1 and b3 denote the Most Significant Bit (MSB) and
Least Significant Bit (LSB) respectively.
The digital switches shown in the above figure will be connected to ground, when the corresponding
input bits are equal to ‘0’. Similarly, the digital switches shown in above figure will be connected to
the negative reference voltage, −VR when the corresponding input bits are equal to ‘1’.

It is difficult to get the generalized output voltage equation of a R-2R Ladder DAC. But, we can find
the analog output voltage values of R-2R Ladder DAC for individual binary input combinations easily.

The advantages of a R-2R Ladder DAC are as follows −

 R-2R Ladder DAC contains only two values of resistor: R and 2R. So, it is easy to select and
design more accurate resistors.

 If more number of bits are present in the digital input, then we have to include required number
of R-2R sections additionally.

Analog to Digital Converter (ADC)

Analog to Digital Converter (ADC) is an electronic integrated circuit used to convert


the analog signals such as voltages to digital or binary form consisting of 1s and 0s. Most of
the ADCs take a voltage input as 0 to 10V, -5V to +5V, etc. and correspondingly
produces digital output as some sort of a binary number.
Types of ADCs: ADCs come in various speeds, use different interfaces, and provide differing
degrees of accuracy. The most common types of ADCs are flash, successive approximation,
and dual slope.

Flash / Parallel type ADC

Flash analog-to-digital converters, also known as parallel ADCs, are the fastest way to convert an
analog signal to a digital signal. Flash ADCs are ideal for applications requiring very large bandwidth,
but they consume more power and much bigger in size than other ADC architectures. A Flash
converter requires a huge number of comparators compared to other ADCs, especially as the
resolution increases. A Flash converter requires 2n-1 comparators for an n-bit conversion.
 Circuit shown is a 3 bit flash converter
 Reference ladder consists of 2n (23 = 8) equal size resistors
 Input voltage is compared to 2n-1 reference voltages using 2n-1 comparators. The reference
voltages can be calculated using KVL.
 A Priority Encoder is used to transform the comparator outputs to the correct digital binary
output.
 Change the input voltage and observe the comparators and the priority encoder digital
outputs.
Advantages:
(i) Simultaneous type A/D converter is the fastest among other ADC’s, because A/D
conversion is performed simultaneously through a set of comparators. Hence, it is also
called flash type A/D converter. Typical conversion time is 100 ns or less.
(ii) It takes only one clock pulse for conversion

Disdvantages:
The simultaneous type A/D converter is not suitable for A/D conversion with more than 3 or 4
digital output bits. It is because of the fact that (2n – 1) comparators are required for an n-bit A/D
converter and the number of comparators required doubles for each added bit. Circuit is very
complex to design.

The counter type A/D converter

The counter type A/D converter is constructed using only one comparator with a variable
reference voltage. The variable reference voltage can be obtained by a sequence counter
and a D/A converter.

The block diagram for an n-bit counter type A/D converter


Wave form of a counter type A/D converter

The operation of the counter type A/D converter is as follows. The n-bit binary counter is
initially set to 0 by the Reset switch which is normally active LOW. Therefore, the digital output
is zero and the analog equivalent Vr is also 0. When Reset signal is released (HIGH), the clock
pulses gated through the AND gate are counted by the binary counter. The D/A converter converts
the digital output to an analog voltage and supplies it as the inverting input to the comparator. The
output of the comparator enables the AND gate to pass the clock. The number of counted pulses
increases with time and the analog input Vr is a rising staircase waveform. The counting will
continue until the reference voltage Vr equals and just rises more than Vi. Then the comparator
output becomes LOW and this disables the AND gate from passing the clock. The counting stops
at the instance Vi > Vr and at that instant the digital output of the comparator represents the analog
input voltage Vi. Then the clock is inhibited, the counter stops its progress and the conversion is
said to be complete. The numbers stored in the n-bit counter is the equivalent n-bit digital data for
the given analog input voltage.
Advantages:
(i) The counter type A/D converter is very simple and needs less hardware compared to the
simultaneous type A/D converter. (ii) This is suitable for digitising applications with high
resolution.
Disdvantages:
In counter type A/D converter, the conversion time is very long since, the counter is reset after
every conversion. As the
For an n-bit A/D converter, the average conversion time
Tc = 2n–1 Tclk, which can be very long for large value of n.

Successive-Approximation ADC

The conversion time is maintained constant in successive approximation type A/D converter, and
it is proportional to the number of bits in the digital output, unlike the counter type A/D converters.

For an n-bit A/D converter, the average conversion time


Tc = n Tclk,
The basic principle of this A/D converter is that the unknown analog input voltage is approximated
against an n-bit digital value by trying one bit at a time, beginning with the MSB. The principle of
successive approximation process for a 4-bit conversion is shown in Fig.

Successive approximation digital 0utput

This type of A/D converter operates by successively dividing the voltage range by half, as
explained in the following steps. (i) The MSB is initially set to 1 with the remaining three bits set
as 0. The digital equivalent is compared with the unknown analog input voltage. (ii) If the analog
input voltage is higher than the digital equivalent, the MSB is retained as 1 and the second MSB
is set to 1. Otherwise, the MSB is reset to 0 and the second MSB is set to 1. (iii) Comparison is
made as given in step 1 to decide whether to retain or reset the second MSB. The third MSB is set
to 1 and the operation is repeated down to LSB and by this time, the converted digital value is
available in the SAR.

From Fig., it can be seen that the conversion time is constant (i.e., four cycles for 4-bit A/D
converter) for various digital outputs. This method uses a very efficient search strategy to complete
an n-bit conversion in just n-clock periods. Therefore, for an 8-bit successive approximation type
A/D converter, the conversion requires only 8 cycles, irrespective of the amplitude of analog input
voltage. The functional block diagram of successive approximation type A/D converter is shown
in Fig . The circuit employs a successive approximation register (SAR) which finds the required
value of each successive bit by trial-and-error method. The output of the SAR is fed to an n-bit
D/A converter. The analog output equivalent of the D/A converter is applied to the non-inverting
input of the comparator, while the other input of the comparator is connected with an unknown
analog input voltage Vi under conversion. The comparator output is used to activate the successive
approximation logic of SAR.
Block diagram

For an 8-bit A/D converter, it requires 8 pulses to compute the output irrespective of the value of the
analog input.

Advantages:

 High accuracy

 Low power consumption

 East to use and low latency time

Dual slope type A/D converter

The dual slope type A/D converter are the most accurate converters of all. In dual slope type A/D
converter, the integrator generates two different ramps, one with the unknown analog input voltage
Vi as the input, and another with a known reference voltage (–VR) as the input. Hence, it is called
dual slope type A/D converter. Its logic diagram and the dual ramp output waveform in Fig.
Operation:
The binary counter is initially reset to 0000; the output of integrator reset to 0V and the input to the
integrator is switched to the unknown analog input voltage VA. The analog input voltage VA is integrated
by the inverting integrator and generates a negative ramp output. The output of comparator is positive
and the clock is passed through the AND gate. This results in counting up of the binary counter. The
negative ramp continues for a fixed time period t1, which is determined by a count detector for the time
period t1. At the end of the fixed time period t1, the ramp output of integrator is given by
𝑉𝐴
∴VS= - ×t1
𝑅𝐶

When the counter reaches the fixed count at time period t1, the binary counter resets to 0000 and
switches the integrator input to a negative reference voltage –Vref. Now the ramp generator starts with
the initial value –Vs and increases in positive direction until it reaches 0V and the counter gets
advanced. When Vs reaches 0V, comparator output becomes negative (i.e. logic 0) and the AND gate
is deactivated. Hence no further clock is applied through AND gate. Now, the conversion cycle is said
to be completed and the positive ramp voltage is given by
𝑉𝑟𝑒𝑓
∴VS= - 𝑅𝐶
×t2

Where Vref & RC are constants and time period t2 is variable.


The dual ramp output waveform is shown below.

Since ramp generator voltage starts at 0V, decreasing down to –Vs and then increasing up to 0V, the
amplitude of negative and positive ramp voltages can be equated as follows.
𝑉𝐴
∴Vref/RC×t2= - 𝑅𝐶
t1
𝑉𝐴
∴t2= - t1× 𝑉𝑟𝑒𝑓
𝑡1
∴VA= - Vref× 𝑡2

Thus, the unknown analog input voltage VA is proportional to the time period t2, because Vref is a
known reference voltage and t1 is the predetermined time period.
The actual conversion of analog voltage VA into a digital count occurs during time t2. The binary
counter gives corresponding digital value for time period t2. The clock is connected to the counter at
the beginning of t2 and is connected at the end of t2. Thus, the counter counts digital output as
Digital output= (counts/sec) t2
VA
∴Digital output= (counts/sec) [t1× Vref ]

Total conversion time


Tc = t1 + t2
= (2n – 1) T + (2n – 1) T
= 2 (2n – 1) T
= (2n+1 – 2) T
Tc = 2n+1 T

Advantages:
1. High accuracy converter
2. Used in measuring instruments and digital multimeter

Disadvantages:
1. Very slow conversion
2. Cannot be used for data acquisition system

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