ADA214144

1 ELECTROSTATIC
DISCHARGE
SUSCEPTIBILITY
DATA i
DTIC 8 9! "E0CTE
Nov 6 1989
Volume I
Ansos
R~e~liabli puCenter
l Reliability Analysis Center

The information and data contained herein have been compiled from
government and nongovernment technical reports and from material
suppneo by various manufacturers and are intended to be used for
reference purposes. Neither the United States Government nor lIT
Research Institute warrant the accuracy of this information and data. The
user is further cautioned that the data contained herein may not be used in
lieu of other contractuallv cited references and specifications.
Publication of this information is not an expression of the opinion of The

United States Government or of HT Research Institute as to the quality or
durability of any product mentioned herein and any use for advertising or
promotional purposes of this information in conjunction with the name of
The United States Government or lIT Research Institute without written
permission is expressly prohibited.
Ordering No. VZAP-2
ELECTROSTA TIC
DISCHARGE
SUSCEPTIBILITY DATA
OF
MICROCIRCUIT
DEVICES VAccesto Fo" -
Volume I NTS RAM.
DTIC 1A13 [
1989 J b ', o
Prepared by: ".b
A\,a!. " Ior

William H. Crowell Dist
Reliability Analysis Center
Under contract to:
Rome Air Development Center

Griffis AFB, NY 13441-5700
Reliability Analysis Center

The Reliability Analysis Centcr (RAC) is a Department of Defense Information Analysis Center
sponsored by the Defense Logistics Agency, managed by the Rome Air Development Center (RADC), and
operated at RADC by lIT Research Institute (IITRI). RAC is chartered to collect, analyze and disseminate
reliability information pertaining to systems and parts used therein. The present scope includes integrated
circuits, hybrids, discrete semiconductors, microwave devices, optoelectronics and nonelectronic parts
employed in military, space and commercial applications. In addition to data collection and analysis
attributes. RAC is also chartered as being a center for all aspects of reliability engineering and related
disciplines including: Reliability, Testability, Statistical Process Control, Electrostatic Discharge, and Total
Quality Management.
Data is collected on a continuous basis from a broad range of sources, including testing laboratories,
device md equipment manufacturers, government laboratories and equipment users (government and non-
,government). Automatic distribution lists, voluntary data submittals and field failure reporting systems
supplement an intensive data solicitation program.
Reliability data and analysis documents covering most of the device types mentioned above are
available from the RAC. Also, RAC provides reliability consulting, training, technical and bibliographic
inquir-y services which are discussed at the end of this document.
REQUEST FOR TECHNICAL ALL OTHER REQUESTS

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C 1989, lIT Research Institute

Aii
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11. TITLE (Include Security Classification)
Electrostatic Discharge Susceptibility Data

12. PERSONAL AUTHOR(S)
William H. Crowell
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FROM _ __TO 1989, March 13 PU box 4/UU,
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17. COSATI CODES 18. SUBJECT TERMS (Continue on reverse if necessary and identify by block number)
FIELD GROUP SUB-GROUP Electrostatic Discharge (ESD)
Electrostatic Discharge Sensitive (ESDS)
Integrated Circuits; Discrete Semiconductor
19. ABSTRACT (Continue on reverse if necessary and identify by block number)
This publictaion contains Electrostatic Discharge (ESD) susceptibility data of
electronic devices and is an update to the VZAP-1, the 1983 RAC ESD data compendium.
Detailed susceptibility data is presented along with the ESD classification in
accordance with MIL-HDBK-263 and MIL-STD-1686A for approximately 4,300 devices.
This data is useful in the establishment of an ESD control program. The data
contained in this publication is a product of the Reliability Analysis Center's
VZAP data base, which is intended to be a central repository of ESD Susceptibility
Data.
20 DISTRIBUTION/AVAILABILITY OF ABSTRACT 21 ABSTRACT SECURITY CLASSIFICATION

0 UNCLASSIFIED/UNLIMITED 0 SAME AS RPT 0 DTIC USERS
22a NAME OF RFSPONSIBLE INDIVIDIUAL 22b TELEPHONE (Include Area Code) 22c OFFICE SYMBOL
Steven J. Flint, RAC Technical Director (315) 337-0900
oD Fnrrn 1473, JIN 86 P...- ,;'d itic)satc
arc ubsoi~lE IOIT'Y LASSIr4(.&I r r -,oue
Jii
iv
PREFACE
The purpose of this document is to make available electrostatic discharge (ESD) susceptibility
test and classification data. This data is much needed by industry and government equipment
designers to enable them to assess their equipments' vulnerability to the ESD thrcat, to assist in the
establishment of ESD control programs, and to comply with such requirements as MIL-STD-
1686A, "Electrostatic Discharge Control Program for Protection of Electrical and Electronic Parts
Assemblies and Equipment (Excluding Electrically Initiated Explosives Devices)."
This document was prepared as part of the Reliability Analysis Center's efforts to provide its
user community with new and needcd information in the field of electronic device reliability.
Contributing to this effort were William Denson, David Mahar, John Puleo and Shawn
Gentile.
V
vi
TABLE OF CONTENTS
Pag~e
SECTION 1.0 INTRODUCTION 1
1.0 INTRODUCTION 3
1.1 BACKGROUND 3
1.2 USE OF THIS DATA 3
1.3 INTERPRETATION OF DATA 7
1.4 CONVERSION OF EMP OVERSTRESS TST DATA 9
TO THE ESD HUMAN BODY MODEL
1.5 VARIABILITY ASSOCIATED WITH CONVENTIONAL 11
TEST METHODS
1.6 SUMMARY AND CONCLUSIONS 12
SECTION 2.0 FAILURE VOLTAGE PROFILE 15

2.1 SUSCEPTIBILITY OF VARIOUS TECHNOLOGIES 17
2.2 SUMMARIZED DATA - VOLTAGE VS. TECHNOLOGY 34
2.3 PERCENTAGE OF FAILURES PER TECHNOLOGY 35
SECTION 3.0 DETAILED DEVICE SUSCEPTIBILITY TEST DATA 39

3.1 MICROCIRCUIT SUSCEPTIBILITY TEST DATA 55
3.2 DISCRETE SEMICONDUCTOR SUSCEPTIBILITY 373
TEST DATA (Volume II)
3.3 PASSIVE COMPONENT SUSCEPTIBILITY TEST DATA 519
(Volume II)
SECTION 4.0 PART NUMBER INDEX (Volume 11) 533
SECTION 5.0 DATA SOURCES (Volume 11) 559
SECTION 6.0 REFERENCES (Volume II) 581
APPENDICES (VOLUME II)
APPENDIX A DERIVATION OF DATA CONVERSION FORMULA 589

APPENDIX B REPORTING SENSITIVITY DATA 595
* DEFINITION OF VZAP TEST PARAMETERS 599
APPENDIX C ADDITIONAL RAC SERVICES 603
vii
LIST OF TABLES
Pag~e
TABLE 1 PERCENTAGE OF FAILURE RECORDS PER TECHNOLOGY-IC 37
TABLE 2 PERCENTAGE OF FAILURE RECORDS PER 38
CIRCUIT TYPE-DISCRETE
TABLE 3 MANUFACTURER LISTING 43
TABLE 4 FAILURE CRITERIA LISTING 44
TABLE 5 TEST REMARKS LISTING 47
TABLE 6 GENERAL REMARKS LISTING 53
TABLE 7 DATA ITEM DESCRIPTION DI-RELI-80670 (Volume II) 597
TABLE 8 VZAP TEST PARAMETERS (Volume 11) 601
LIST OF FIGURES
FIGURE 1 EMP VS. ESD DATA COMPARISON 10

FIGURE 2 FAILURE DISTRIBUTION FOR TESTER #1 13
FIGURE 3 FAILURE DISTRIBUTION FOR TESTER #2 13
FIGURE 4 STEP-STRESS RESULTS FOR 74F04 14
FIGURE 5 STEP-STRESS RESULTS FOR 74F175 14
FIGURE 6 FAILURE VOLTAGE PROFILE-TITL 19
FIGURE 7 FAILURE VOLTAGE PROFILE-STI'L 19
FIGURE 8 FAILURE VOLTAGE PROFILE-LTITL 20
FIGURE 9 FAILURE VOLTAGE PROFILE-HT'TL 20
FIGURE 10 FAILURE VOLTAGE PROFILE-LSTIL 21
FIGURE I1 FAILURE VOLTAGE PROFILE-ADVANCED STTL & LSTTL 21
FIGURE 12 FAILURE VOLTAGE PROFILE-MOS 22
FIGURE 13 FAILURE VOLTAGE PROFILE-NMOS 22
FIGURE 14 FAILURE VOLTAGE PROFILE-CMOS 23
FIGURE 15 FAILURE VOLTAGE PROFILE-HMOS 23
FIGURE 16 FAILURE VOLTAGE PROFILE WET 24
FIGURE 17 FAILURE VOLTAGE PROFILE-BIFET 24
FIGURE 18 FAILURE VOLTAGE PROFILE-ALL TITL 25
FIGURE 19 FAILURE VOLTAGE PROFILE-ALL MICROCIRCUIT 25
FIGURE 20 FAILURE VOLTAGE PROFILE-BIPOLAR AND IlL 26
FIGURE 21 FAILURE VOLTAGE PROFILE-BIPOLAR AND MOS 26
vii
LIST OF FIGURES (CONT'D)
FIGURE 22 FAILURE VOLTAGE PROFILE-ALL FET 27

FIGURE 23 FAILURE VOLTAGE PROFILE-ALL MOS 27
FIGURE 24 FAILURE VOLTAGE PROFILE-SMALL SIGNAL DIODE 28
FIGURE 25 FAILURE VOLTAGE PROFILE-RECTIFIER 28
FIGURE 26 FAILURE VOLTAGE PROFILE-ZENER 29
FIGURE 27 FAILURE VOLTAGE PROFILE-MICROWAVE DIODE 29
FIGURE 28 FAILURE VOLTAGE PROFILE-JUNCTION FET 30
FIGURE 29 FAILURE VOLTAGE PROFILE-MOS FET 30
FIGURE 30 FAILURE VOLTAGE PROFILE-LOW POWER TRANSISTOR 31
FIGURE 31 FAILURE VOLTAGE PROFILE-HIGH POWER TRANSISTOR 31
FIGURE 32 FAILURE VOLTAGE PROFILE-MICROWAVE TRANSISTOR 32
FIGURE 33 FAILURE VOLTAGE PROFILE-FIELD EFFECT TRANSISTOR 32
FIGURE 34 FAILURE VOLTAGE PROFILE-THYRISTOR 33
FIGURE 35 FAILURE VOLTAGE PROFILE-OPTOELECTRONIC DEVICE 33
ix
x
SECTION 1.0
INTRODUCTION
i i
ii P2
1.0 INTRODUCTION
This databook makes available ESD susceptibility test data that the RAC has collected from a
variety of sources over the past few years on integrated circuits, discrete semiconductors and
resistors.
The introductory material of this publication is not intended to provide a tutorial on ESD
testing or the physics of ESD failures, but rather to provide enough information to allow the user
of this document to effectively interpret the presented data. This information will also give the user
some insight into the usefulness and limitations of the data.
1.1 BACKGROUND
When VZAP- 1 was published in 1983, ESD was a relatively immature field with a serious
lack of standardization, especially in the area of ESD susceptibility testing. Much of the VZAP-1
data was taken wi:-, non-standard ESD simulator circuits that deviated from the use of a 100 pF,
1500 ohm discharge model. Additionally, it was discovered subsequent to VZAP-1 that many of
these simulators, either commercially available or built in-house, have low degrees of repeatability,
due to many uncontrolled variables. Although many of the reasons for this nonrepeatability have
been studied, understood, and corrected, there potentially still exists sources for large degrees of
variation in the test results. A discussion of typical variability that exist in test results is given in
Section 1.5
VZAP-2 is intended to be an update to VZAP-1. and presents more data of higher quality.
These improvements are possible because much has been learned in the field of electrostatic
discharge since VZAP-1 was issued.
1.2 USEOFTHIS DATA
MIL-STD-1686A covers the requirements for the establishment and implementation of an

ESD control program, including identification of ESD Sensitive (ESDS) parts, assemblies, and
equipments. Any organization that designs, tests, inspects, services, manufacturers, processes,
assembles, installs, packages, labels, or otherwise handles electronic parts, assemblies, and
equipment susceptible to ESD damage should consider implementation of an ESD control program.
3
The first consideration in establishing an ESD control program in a specific application is the
identification of the susceptibility levels of the specific parts being used. This is true whether the
program is being implemented as a result of MIL-STD- I 686A or not. Based on this information,
an effective program can then be designed and implemented without expensive overkill.
MIL-STD-1686A, Paragraph 5.2 states, "The contractor shall identify each ESD Sensitive
(ESDS) part, assembly, and equipment applicable to the contract as Class I or 2." In some cases
Class 3 parts must also be identified. Paragraph 5.2.1.1 further states "ESD sensitivity
classification for parts shall be determined as follows:
(a) ESD sensitivity as specified in the applicable part specification, or
(b) ESD sensitivity in accordance with Appendix A test data contained in the Reliability
Analysis Center (RAC) ESD Sensitive Items List (ESDSIL), or
(c) Classified in accordance with Appendix B, or,
(d) When specified, or at the option of the contractor, determine sensitivity by test (See
Appendix A). ESD sensitivity test data reporting shall be in accordance with the data
ordering document included in the contract or order (See 6.2)."
The data contained in this databook is essentially a compilation of ESD test data taken from a
wide variety of sources. The ESDSIL database referred to in item (b) above is entitled the
"Electrostatic Discharge Sensitive Items List." The intent of the ESDSIL database is to be a central
repository of data taken as a result of the requirements of MIL-STD-1686A and Data Item
Description (DID-RELI-80670). The classification test procedure of MIL-STD- 1686A, Appendix
A, requires the use of the test circuit of MIL-STD-883, Method 3015. At the time MIL-STD-
1686A was issued the MIL-STD-883 test method in effect was Method 3015.6. Since there is no
data in this publication which resulted from testing as required by Method 3015.6 or later, the data
contained herein does not fulfill the requirements of (b) above.
However, the data in this publication is more desirable than the use of (c) above which
generically classifies components based on part type. Since 3015.6 was the first MIL-STD-883
ESD test method to ensure reasonable confidence in test waveform characteristics, it is the most
desirable test data available. The data types, in order of preference, can be summarized as follows:
4
1) MIL-STD-883, Method 3015.6 or later
2) MIL-STD-883, Method 3015.5 or earlier, or other 100pF, 1500 ohm Human Body
Model (HBM) tests, such as DOD-STD-1686
3) Non 100pF, 1500 ohm HBM tests converted to an ESD susceptibility level consistent
with the 100 pF, 1500 ohm model
4) Electromagnetic Pulse (EMP) data converted to an ESD susceptibility level.
The data contained in this document are from items 2, 3 and 4. This is also the order of
preference which was used in determining the ESD classification of each part listed.
A more detailed description of the test method used for each data entry is given in the remarks
field of Section 3 and also in Section 5 (Volume II) of this document.
Before the updates of DOD-STD-1686 to MIL-STD-1686A and MIL-STD-883 Method

3015.5 to 3015.6, there were inconsistencies between DOD-STD-1686 and the MIL-STD-883
method of reporting ESD test results. Specifically, the voltage susceptibility ranges were different,
making it impossible to cross-correlate test data. Both MIL-STD-1686A and MIL-STD-883,
Method 3015.6 have been coordinated, thereby making data taken from either useable for either
purpose. In fact MIL-STD-1686A invokes the procedure of MIL-STD-883 Method 3015.6. The
classification ranges in these documents are as follows:
Class 1 0-1999
Class 2 2000-3999
Class 3 4000-15999
This is the classification scheme that is used in this publication. In addition to these, RAC
has defined Class N to mean devices susceptible to levels above 15999 volts.
Since much of the data in this publication was obtained from tests performed not in
accordance with MIL-STD- 1686A or MIL-STD-883, classification in accordance with these
standards becomes difficult. For example, if testing was performed that yielded devices passing a
test at 1000 volts but failing the test at 3000, although it is known that the susceptibility level is
1000-3000 volts, the MIL-STD-1686A classification cannot be precisely determined. In this
example it is not known whether the device is Class I or 2. The classification criteria used in this
publication was to use the lowest failure voltage or the highest voltage at which the device passed if
5
no failure data existed. For example, if a device was observed to fail when tested at 2000 volts
only, it was classified as Class 1 since the actual threshold voltage is between 1 and 2000 volts.
As stated previously, all data present in this document was not taken from specific test
methods, such as method 3015 of MIL-STD-883 but rather from a variety of test methods.
Contained in this document are the results of tests done in accordance with MIL-STD-883, test
method 3015; tests similar to MIL-STD-883 Method 3015 but not strictly in accordance with it;
tests using nonstandard simulation models and methods; and EMP data that was converted to
reflect ESD susceptibility levels. The EMP data was only used for classification purposes in the
cases in which there was no other empirical ESD susceptibility data. The methodology used to
convert EMP data to ESD susceptibility levels is given in Section 1.5.
In future revisions to this publication, it will be interesting to note the differences in ESD
susceptibility data between Method 3015.6 and earlier versions in which the waveform was not
tightly controlled. However, in general data taken from circuits in which the high frequency (i.e.
> 100 MHz) performance has not been characterized will lower failure thresholds. This potential
exists due to the fact that there can exist high frequency, high amplitude oscillations in some
circuits which yield higher stressing amplitudes than that of the ideal RC discharge waveform.
Additionally, there is a limited amount of Charged Device Model (CDM) test results. Even
though CDM tests are not yet incorporated into the ESD testing standards, there has been some
data included which were taken using this model. Although the device classification schemes are
only applicable for the HBM, the CDM data that was available is included for completeness,
considering that conventional classifications with CDM data cannot be done.
Individuals or firms testing devices for ESD susceptibility are encouraged to submit the
resulting data to the Reliability Analysis Center for inclusion into the database. If desired, the
source of data will be held proprietary by RAC. This data does not need to be taken in accordance
with the MIL-STD-883 test method, but can be any empirical ESD susceptibility data. A
recommended format for this data is given in Appendix B (Volume II). Also given in Appendix B,
for information purposes only, is the Data Item Descriptior (DID) DI-RELI-80670 called out in
MIL-STD- 1686A for submission of ESD sensitivity data.
6
1.3 INTERPRETATION OF DATA
The data contained herein is intended to present the results of empirical tests performed.
Ideally, in addition to voltage susceptibility levels, one would like to know specific failure
mechanisms that caused the device to fail. While manufacturers typically know the manner in
which their part will fail when exposed to an ESD transient, this data is not normally available to
outside organizations. Therefore, the specific failure mechanisms are not known. What is usually
known is the failure mode (that is, the measurable effect of damage), since in any ESD test the:e
must be a means of detecting failure. Examples of typical failure modes (or failure criteria)
included excessive input leakage, input stuck high, functional failure, etc.
The failure criterion used in establishing an ESD failure is critical to the outcome of the
testing. This may be illustrated by the use of two examples. In the first example, let us assume
that the failure criterion for a bipolar device is defined as a certain percentage change in leakage
current. This may be a difficult failure criterion to implement, because the relationship of leakage
current versus stress voltage itself is not well-defined. In the second example, let us assume that
the leakage current specification limits are used as the failure criterion for the same parts. The
device which we are testing is relatively tolerant to ESD and remains within the specification limits
when stressed with a pulse well below the damage threshold. Nevertheless, there is a measurable
change in the leakage current, i.e., the device has been degraded; however, it does not exceed the
specification until it is subsequently pulsed with a much higher energy pulse. Since we know that
some degradation has occurred, we can measure the degradation, but, because of the failure
criterion, the device is not considered susceptible to ESD damage at the lower level. For this
reason, the criterion used to detect device failure must also be selected in accordance with the
device operating characteristics and the manner in which the device is designed into a circuit; that
is, if a certain circuit configuration can tolerate a parameter shift or even an out-of-specification
condition of this component. Since it is impractical to require unique failure criteria based on the
manner in which the part is used in the circuit, MIL-STD-883, Method 3015.6 states the devices
shall be tested for failure following stressing by performing room temperature DC parametric and
functional tests. Performing both parametric and functional tests should identify any degradation
or failure of the device.
It is also recognized that failure modes and mechanisms are highly dependent on the
simulation circuit used to stress the device. There are various circuits being used in industry to
simulate different ESD scenarios. The most standard of these is the Human Body Model, in which
a charged capacitance is discharged through a resistor to the device under test. This Human Body
7
Model is the most commonly used simulation model and is specified in MIL-STD-1686A and MIL-
STD-883 Method 3015. The resistance and capacitance values specified in these standards are 100
pF and 1500 ohms, respectively. Other values are often used and some data in this publication use
these values. The values used are listed in the detailed data (Section 3.0). It should be noted that
devices can exhibit different susceptibility characteristics depending on the values used. Since
there is a need to classify devices in a consistent manner, the RAC derived a conversion method for
data that was taken using a Human Body Model with resistance and capacitance values other than
100 pF, 1500 ohms.
Using semi-empirical methods, the RAC has established the following formula for the
conversion:
V1 = V2 (3.87) L2
where:
V1 = standard human body model damage threshold

R2 = nonstandard value of resistance used (in ohms)
C2 = nonstandard value of capacitance used (in pF)
V2 = measured damage threshold using C2 and R2
The derivation of this equation may be found in Appendix A.
This method is only used so that a classification in accordance with the susceptibility levels
of MIL-STD-1686A can be made. The data in Section 3.0 presents both the classification of each
part and the data as it was obtained, i.e., the failure voltages of the actual model used during
testing.
Other ESD simulation models sometimes used are the charged device model and the machine
model. The charged device model simulates the situation in which a device, after being charged,
contacts a conductive object, thereby causing a high amplitude, short duration discharge pulse.
The machine model simulates a situation in which a device is contacted with a charged capacitance
through a very low resistance. This model is intended to simulate a conductive object, like parts of
a machine, that contact the device.
The purpose of this book is not to provide background on the physics of ESD failures, as
this has been done extensively in the literature, but rather to present the data collected by RAC and
give the reader enough information so that the limitations of the data are fully understood. If
8
further information is required, DOD-HDBK-263, "Electrostatic Discharge Control tand .k fr
the Protection of Electrical and Electronic Parts, Assemblies, and Equipment (Exchmling
Electrically Initiated Explosive Devices)" and the proceedings of the Annual f()SLSI)
Symposium provide much information on all aspects of ESD.
1.4 CONVERSION OF EMP OVERSTRESS TEST DATA TO THE ESD

HUMAN BODY MODEL
A vast amount of electrical overstress data has been compiled from Electromagnceti Pillse
(EMP) studies. It would be negligent to disregard this potential data source. By knowing cetmin
parameters of a device, a theoretical ESD failure can be calculated using the Wunsch-tell moelC]
(Reference 28) as the starting point. The following equation has been established to convert FMP
overstress data to the ESD human body model equivalent:
V 2VD + / 4VD 2 + 1200 K 1 (7.675 x 10-7) - K2 1530 + VD

60150+V
where:
V = ESD threshold voltage
VD = measured overstress breakdown voltage
K1 = failure constant 1
K2 = failure constant 2
The derivation of this equation may be found in Appendix A (Volume II).
To further verify the validity of the calculated ESD levels presented in this book, data was
compared for specific devices which had both empirical ESD threshold data and ESD threshold
levels calculated from EMP data. The log of the ratio of ESD to EMP failure voltages was plotted
such that a given percentage of discrepancy (i.e., if the EMP level was the same percentage higher
or lower than the ESD level) would be equidistant from the 0 line. Figure 1 is a histogram
EMP
illustrating the relationship between the log (E ) and frequency of occurrence. If the datapoints
were randomly distributed about the 0 line and the data did not show a shift in distribution against
any parameter, it could be concluded that the failure levels obtained from EMP data were a fairly
good indication of the actual susceptibility levels of the devices (not taking into account random
9
variations and noise in the data for any given device). Analysis of this data however, indicated that
EMP
the log (t ) datapoints were not randomly distributed but rather correlated to the susceptibility
level. This indicates that the conversion algorithm is not perfectly accurate.
5 -
._9 4
3-
Ii
-1.0 -.9 -.8 -.7 -.6 -.5 -.4 -.3 -.2 -. 1 0 .1 .2 .3 .4 .5 .6 .7 .8 .9 1.0
Log ( EMP
ESD
FIGURE 1: EMP VS. ESD DATA
Based on this information it should be emphasized that the ESD susceptibility levels obtained
from EMP data are necessarily only approximate values. It can be seen from Figure 1 that the
EMP to ESD levels can differ by as much as a factor of 10. There are various sources of error in
converting EMP data to ESD data. Two of these error sources are the uncertainty in the damage
constants and the uncertainty in the device parameters (bulk resistance and breakdown voltage).
These uncertainties can stem from normal lot to lot variations and differences among
manufacturers. Additionally, it is known that damage from EMP test pulses may manifest itself
as different failure mechanisms than damage from an ESD pulse. This is due to the fact that an
ESD pulse may be a shorter duration, higher current pulse relative to an EMP event. These
variations can easily cause a factor of 10 difference in the susceptibility levels. For this reason.
EMP data is used in this publication for classification purposes only in those cases where ESD data
10
is not available. The EMP data is identified as such in the remarks field (field no. 18) of the
detailed data section.
1.5 VARIABILITY ASSOCIATED WITH CONVENTIONAL TEST METHIODS
Since ESD testing began, it has been recognized that there was a certain degree of variability
in test results due to the test apparatus itself. These variations were attributed to:
• Arcing of the high voltage switching relay.

• Errors in calibration of the test voltages.
• Leakage of the capacitor.
• Parasitic inductances and capacitances.
• Inconsistencies in the criteria used to detect failure.
• Incomplete characterization of worst case pin combinations.
Conventional ESD simulators probably effectively simulate a real ESD event from a charged
person or object, since a real ESD would have many of the parasitic R, L, and C values similar to
that of the simulator (Reference 8). The problem is, however, that the discharge waveform
produced is uncontrolled and cannot be used to obtain repeatable results.
To illustrate the repeatability of tests using a conventional circuit, Figures 2 and 3 present the
data RAC has taken from two different conventional ESD simulators. A sampling of 74LS08
devices were obtained of the same date code, attempting to minimize variations in the device under
test population. The most susceptible pin was found by step stressing a small sample of devices
on each pin until failure. Failures were detected with a curve tracer indicating a change in reverse
breakdown voltage characteristics between the pin under test and the substrate of the device.
Once the most susceptible pin was found, a sampling of 30 devices were step stressed to
failure on this pin for each of the two simulators. Voltage step increments of 25 volts were used to
maximize the resolution of failure voltage distributions. The intent of the study was to:
(1) Determine the failure voltage distribution of a typical device stressed with a
conventional test apparatus.
(2) Identify differences in these distributions between two typical simulators.
11
Another study (Reference 26) with similar objectives yielded even a higher degree of
variability. In this study, a sampling of 74F04 and 74F175 devices were tested by three
independent test labs. Figures 4 and 5 summarize these results.
These results were taken when ESD testing technology was less mature and testers were
being built with little regard for the subtleties involved in making an accurate and repeatable test
circuit. Since the data contained in this publication was obtained from a variety of testers, it is
apparent that this inherent variability is present in it.
In addition to the inherent variation in test apparatus and devices themselves, there can also
exist large variations between manufacturers. This is due to the fact that each manufacturer
employs their own unique methodologies and circuitry to protect devices, each with their own
protection capability. If the manufacturer was known, it is reported in the detailed data section of
this publication.
1.6 SUMMARY AND CONCLUSIONS
This publication presents the most comprehensive compendium of electrostatic discharge

susceptibility test data currently available. This data is useful (and mandated by MIL-STD-1686A)
for the establishment of ESD control procedures based on the susceptibility of devices being
handled, assembled, stored, etc. It is important for the users of this information to understand the
limitations of the data contained herein. To accomplish this, previous discussions have addressed
the different types of data included in this publication as well as the variation inherent in it.
RAC also strongly encourages any one performing ESD susceptibility tests to submit the
results of those tests to RAC for inclusion in the database and dissemination in future editions of
this publication. If tests are performed in accordance with MIL-STD-1686A, the results are
required to be submitted to RAC as outlined in the Data Item Description DI-RELI-80670 (given in
Appendix B, Volume II). Also, given in Appendix B is a format for submitting data if not done in
accordance with a specific test method.
12
TESTER
co1
# 1
C) C) C
LCD
1 ti ,(, 15) ;2 450 2750 3050 330 3610 J3950 4250
S 300 C100 2900 3200 3 50) 3600 4100

"
FAILURE VOLTAGI
FIGURE 2: FAILURE DISTRIBUTION FOR TESTER #1
TESTER #2
C ,-
f3
4 .
1650 2150 2450 2750 3050 33b0 365,0 3950 4250

2000 2300 2600 2900 3200 3500 3000 4100
FAILURE VOLTAGE
FIGURE 3: FAILURE DISTRIBUTION FOR TESTER #2
13
STEP STRESS TEST RESULTS
FOR 74F04
70()
CD
C- TESTER &1
IT.StEH &2
TESTER *3
!100
C)
a400
a
-'0
,
*t
a
-'at
Ca Ca
...
C>
:7 C>
*I~
Ca
C3a Ca
S) 300
9 11 13
PIN NUMBER
FIGURE 4: STEP-STRESS RESULTS FOR 74F04
STEP
4 (a 00FOR
STRESS
C>
4
TEST
74F175
RESULTS
TESTER # 1
1
TESTER *'2
........TESTER *3
C>
C>
Ca Ca
or)
Ca O • O OaCaO i
2000 ,3
CDa
lln <D
4 5 g 12 13
PIN NUMBER
. i .l = I Ca
FIGURE 5: STEP-STRESS RESULTS FOR 74FI75
14
SECTION 2.0
FAILURE VOLTAGE PROFILE
15
16
2.1 SUSCEPTIBILITIES OF VARIOUS TECHNOLOGIES
The relative susceptibilities of various technologies can be seen from the following
histograms (Figure 6 through 35). Cases where there are large peaks in the histogram are
indicative of a particular data source or test method. For example, the peaks at 1000-1499 volts for
CMOS, 2000-2499 volts for TTL, 1000-1499 volts for STTL, etc., were primarily from data
contained in Source Code 030 (Section 5.0). However, when observing the histogram (Figure 19)
for failure voltages of all microcircuit technologies combined, a much larger sample size was
available and a fairly well-defined curve was obtained.
17
18
OF TTL DEVICES
CC ,
Lu
-a
cc
0-[---
<C1 199
40- 2CC -2-;99 5000-3499 > 4000
9 1500- 99 2--2 99 500 -3999

FAILURE VOLTAGE
Pe,~Ay4oh.sCe-e-. 1.-e.N~Y,134-0
FIGURE 6

OF STTL DEVICES
cc
-J
co
-- 4 ',IO - 1 411- 2 r:00 - 1' ,1, -7co %(3 O - 3

I !__ I100-
"_
c) > 4 cc)
29"!9
FAILURE VOLTAGE
FIGURE 7
19
OF LTTL DEVICES
100
cr
40
C 30 u499
L11
20 -- ,o --
-99 1000-149 2000-2499 3000-35499 > =4000

500-999 1500-1999 2500-2999 3500-3599q
FAILURE VOLTrAGE
.... ~~~~elhobility
Amolys-s C-et. R - .,Ne Og 3 4
FIGURE 8
2- 401
C)r
FLURE VOLTrAGE PROFILE

OF HTT-L [DEVICES
30
20
- !0
< 49 1000-1499 2000--2409 3000-3499 > =-OO©

I I • I
5 (--999 1500-1999 25E,0(0- 2 9139 3500-3999
FAILUR E VOLTAGE
L ,440
FIGURE 9
20
OF LSTTL DEVICES
220
200 C"-
1(0
'UI
CO,
1 20
100
C>,
60
40-T
20--
<0499 1 000-1499 2000-2499 3000-3499 > -4 000
500-999 1500-1999 2500-2999 3500-3999

FAILURE VOLTAGE
Rao b;lty A-oys$, C e, . Roe. N- ork 13440
FIGURE 10
FAILURE VOLTAGE PROFILE OF

ADVANCED STTL & LSTTL DEVICES
350 i
3001
Lu
, 200#
50 T
FAILURE VOLTAGE
i _-I
~ I2
0FIGURE
li 11 " II
21
OF MOS DEVICES
201
a I -
cc
4.-
SC)00- 1 ,49 20 - 2000 - 349 >=40C

00 - 99 1500-7999 25C,-29q9 3500 - 9 99
FAILURE VOLTAGE
FIGURE 12

OF NMOS DEVICES
140]
Lu
cc 2o
(I
co
cc
0L
FAILURE VOLTAGE
FIGURE 13
22
OF CMOS DEVICES
1000
Booor
GO C,0 I
Lu C)
o I
200990
=49 1000-1499 2000-2499 3000-3499 >=40C0

500-999 1500-1999 2500-2999 3500-3.99
FAILURE VOLTAGE
FIGURE 14

OF HMOS DEVICES
300
250
*-j 200--
Sr-
> '00-
N ,0 04,C cno
1000-1499 2000-2499 3000-3499

500-999 1500-1999 2500-2999 -3500--4"
FAILURE VOLTAGE
FIGURE 15
23
OF JFET DEVICES
6-
-J
500 -99 1500- 199 0-299950- ILL 50
C>', FIGURE 16

C) OF BIFET
D DEVICES
Io
0 1 0 25 29 -35C2 0
I Pri I
FAILURE VOLTAGE
FIGURE 17
24
ALL TTL DEVICES
900
Cr H
CrO
,3 -
<.499 1000-1499 2000-2499 3000-3a99 > -000

500-999 1500-1999 2500-2999 Z500-3999
FAILURE VOLTAGE
t
Rellibih y A.-ayss Cente, Ro,&. Ne- York 13440
FIGURE 18

ALL MICROCIRCUIT DEVICES
C,o
u-
Cr I
a,'
4Q, 0 ,-i
1000-1499 2000-2999 4000-4999 >=6000

500-999 1500-1999 3000-3999 5000-5999
FAILURE VOLTAGE
FIGURE 19
25
OF BIPOLAR & IlL DEVICES
6000
3
La4
a) L u
L.
Uj I
1000 -1499 2000-2999 4000-4999

9 -- 100-1999 -3000-3999 5000-599
FAILURE VOLTAGE
Rei ob ,ly A..Olys, S e r Po . tw o.. 13440
FIGURE 20

I 2400
BIPOLAR AND MOS DEVICES
(--
Lu
L4J
a) :a ;
co
a ' 21 a --- -
FAILURE VOLTAGE
FIGURE 21
26
FET [DEVICES
FAILURE VO>LT7AGE
FIGURE 22
FAILURE VOLTAG3E PROFILE OF

ALL MOS DEVICES
c:)
FAI LURE VOL r AC3K:
FIGURE 23
27
OF SMALL SIGNAL DIODES
C)
C3
cr
FAILURE VOLTAGE
FIGURE 24
FAILURE VOL-[AGE PROFILE

OF RECTIFIER DIODES
co fir
, L :O- _C -~.1 " >= 16000
FAILURE VOLTAGE
FIGURE 25
28
OF ZENER DIODES
C)
FAILURE VOLTAGE
FIGURE 26

MICROWAVE DIODES
co
FAILURE VOLTAGE
FIGURE 27
29
JUNCTION FETS
¢3
u-J C
cc
co
0
1,9 99 Z:,C -999 ,-OOC-15999 > i 6COO-

FAILURE VOLTAGE
FIGURE 28

OF MOS FET DEVICES
UZ
Cm
FAILURE VOLTAGE
FIGURE 29
30
FAILURE VOLTrAGE PROFILE
OF LOW POWER TrRANSISTO(RS
3-423
C-
U3
m
0 r -~z ~ 99 9
- SCI >~=~
FAILURE VOLTAGE
FIGURE 30
FAIUREVOLAGE PROFILE
OF HIGH POWERTRNIOS
57
CC
cn
Lu
C) -
FAILURE VOLTAGE
FIGURE 31
31
FAILURE VOLTG PROFILE
O7F MICROWAVE TrRANSISTORS
cc)
rAIL-URE VOLTAGE
FIGURE 32
FAILUE VOLAGE POFIL

FAILURE VOL-TAGE PROFIL-E
O:F -THYRISTOCRS
c/:)
FAL R CU-A3
FALRLU:LrCE R:FL
LUJ
Ct)
Si
co
FZAILURE VOLTAGE
FIGURE 34
FAILUE VOLAGE POFIL

2.2 SUMMARIZED DATA - VOLTAGE VS. TECHNOLOGY
The data in this section was generated from the failure voltages of each entry in the Detailed
Device Susceptibility Test Data of Section 3.0. Where necessary, the actual test voltages were
converted to levels consistent with the widely recognized 100 pF, 1500 ohm human body model
since mixing failure voltages of data obtained with different resistor-capacitor values and different
discharge models would confound the data significantly. This data conversion methodology was
discussed in Section 1.4.
It should be noted that data was also included which represents an approximate upper bound
of threshold voltages (i.e., one test at one voltage was carried out on a device and a failure
resulted). Thus, although exact damage threshold voltage of the device could not be determined
from that one data point, it is known that the threshold is equal to or less than the test voltage.
The data as presented in this section may be somewhat biased since all data entries from the
detailed data section were used. This bias comes from the fact that where one data source may
have included all of the data (on all pins, for example) another may have only presented the worst-
case failures (i.e., the most sensitive pin).
34
2.3 PERCENTAGE OF FAILURES PER TECHNOLOGY
A total of 5,501 device records were categorized during the preparation of this databook.
Table I and 2 summarizes the percentages of each technology family, (integrated circuits and
discrete semiconductors respectively) in each category of ESD classification. Section 3.0 contains
the complete categorization data by part numbers.
35
36
00~~' 00mr-
r
l - :!- c 1 -
ft C14 00 ~ 0r
0 0N 0O C
-q 0 -c Cl4
CIA
M ~C
C4 C-
Zrt 00 - - C- C - C - C' cn C m-- C
Cl~~~1 - l 0 C ' 00 -~ ~ 0
or, C N- C CD - C - N
CI~ ' Zt - wl - 0 e r I~C D 0 '0 a
CN - - 0
tr'-Cl - m~ Cl .
Cl 0 W.)
C-4. 4l' C4 N "l -
CC
C- C C- C 4 C
M- - - C- - C-
M- %n- - C- C4 C
Cl,
-4 N- C-l - 0 N C1
-'' 'o 0 0
z~2 Cl C
- C C C C C C C
37C C C C C C C C C
r-e - r- O -N -nI
- z r
00 r-
00 ON M , r r
ON1
- 1 1 ~ m
O
1
r- z:§
O0 0
z m kn \C - -,C
00 00
3-
SECTION 3.0
DETAILED DEVICE SUSCEPTIBILITY TEST DATA
39
40
0 C
.0r >
C).U
LL. (4.E
0J cc-
-~~c - c
-
'.4~0 -I
00 ~-41
- •
- -- ",-
• .. " ,,.0
- "-,0
,v, " )
-.. *.- 0 <
- -e " , ,,
:_. . ,.),
•"- " -;,i . =.
~o
0 2
- -
- i
RAC ESD DATABASE
Table 3 -MANUFACTURER LISTING
OGGE MANUFACTURER NAME CODE MANUFACTURER NAME
ALP Alpha Industries MOT Motorola Semi

AM American Microcircuits MPI Micropac Industries
AMD Advanced Micro Devices MSC Microwave Semi Corp
AMP Amperex Electronics MSI Microsystems International
ANA Analog Devices N/R Not Reported
ANZ Anzac Electronics NCR National Cash Register
ATM ATMEL NEC Nippon Electric Company (NEC)
BEC Beckman Instruments NIT Nitron
EE. Bendix NSC National Semi
E- Craven Crystal Ltd. NUC Nucleonic Prod
CEN Centratab PLE Plessey
YLCompcne nt Device Inc. PPC PPC Products
CC Codi Semiccnductar PPI Precision Products Inc.
::Contine-ntal Semi. Inc. PRE Precision Manalithics
C Cypress Semicanductcr RAY Raytheon
A-Dale Etectrcon'ct RCA RCA
CZDynamic Cantrol Carp RI Rockwell Intl (Includes Collins)
Ct Delco ELectronics SCN Semicon
:CDickson Etec. Carp. SEM Semtech Corp.
-Elec. Transistor Carp. SEN Sensitron Semi.
F -C Fairchild SEC SEED
Genera. Electric SGS SGS ATES
GNGeneral Semiconductor SIE Siemans
0: General instruments SIG Signetics
CTL Gilway Technical Lamp 511. Silicon General
HAP Harris SIX Siliconix
HAj Hauti~aon SOL SoLitron Devices
ri.W Hewlett Packard SPR Sprague Electric
HiIT Hitachi SSD Solid State Devices
HON Honeywell SSS Solid State Scientific
HfB Hybrid Systems. SUP Supertex
HfC Hycamp Inc. SYN Syntron
1'T InternatianaL Device Technolagies TEC Teledyne Crystalanics
1: ITT Semiconductor TEK Tektronix
1P.M INMOS TEL Teledyne
CInse~ek TEX Texas Instruments
Intel THC Thermametrics
or Intl. Rectifier Carp. TRC Transition ELec. Carp.
!SL Intersil TRW TRW
IVT !ntech UDT United Detector Technology
K'% KSC Semiconductor Corp. ULT Ultronix Inc.
LEA Lear S;egler UNI Unitrade
LTC Lirear Tcchnolo qy Co)rp. VAR Various
MAC MACGM VIS Vishay
"AS Micrewaive AooitsWES Westinghouse
YCC McCoy Electronic; XIC Xicur
Micrc Pose4r Sy-,ttm,; ZIL Zileg
V,'onoI
j h i c IMe r) os
43
RAC ESD DATABASE
Table 4 - FAILURE CRITERIA LISTING
CODE FAILURE CRITERIA
1 1 UA LEAKAGE AT 1Ov.
2 1 UA LEAKAGE AT 20V.
3 10 UA INPUT LEAKAGE PREVIOUSLY MEASURED TO BE 1 UA.
4 10% CHANGE IN ELECTRICAL PARAMETERS.
5 10% CHANGE IN LEAKAGE CURRENT.
6 10% PARAMETER CHANGE.
7 110= 4 UA.
8 2 MA LEAKAGE CURRENT OR OPEN CONDUCTOR LINES.
9 2 UA LEAKAGE CURRENT OR OPEN CONDUCTOR LINES.
10 2% CHANGE OF VOUT AT IL= 50UA.
11 20 UA LEAKAGE CURRENT OR OPEN CONDUCTOR LINES.
12 200 NA LEAKAGE CURRENT OR OPEN CONDUCTOR LINES.
13 25% LEAKAGE, luA LEAKAGE, FUNCTION FAILS.
14 50,;DROP IN REVERSE VOLTAGE AT IR= 5UA.
15 50% DROP IN V(BR) CBO AT IB= 5UA.
16 50% DROP IN V(BR) GSS AT IG= 5UA.
17 50% INCREASE IN GATE LEAKAGE CURRENT.
18 A 10% CHANGE IN INPUT OFFSET VOLTAGE AND INPUT BIAS CURRENT.
19 A 10% OR > CHANGE IN ANY MEASURED ELECTRICAL PARAMETER WAS CONSIDERED A FAILURE.
20 A 10% OR > INC. IN MEAS. LEAKAGE CURRENT @OR < A VOLT 10% < THE INITIAL BRKDWN VOLT.
21 A CHANCE OF 0.5% OR GREATER TOLERANCE.
22 A SHIFT OF 10% OF INPUT OFFSET VOLTAGE AND INPUT BIAS CURRENT.
23 ANY MEASURABLE CHANGE IN AN ELECTRICAL PARAMETER.
24 BVBE AT IR: lOONA.
25 CATASTROPHIC FAILURE (INPUT CURRENT).
26 CATASTPOPHIC.
27 CHANGE IN IGSS.
28 CHANGE IN IIH OF 10.
29 CHANGE IN IIH OF 20NA AT VCC= 5.5V AND VIN= 2.4V.
30 CHANGE IN IIH OF 500% AT VIN= 2.7V.
31 CHANGE IN IIL OF *500% AT VIN= .45V.
32 CHANGE IN IIL OF 500% AT VIN= 5V.
33 CHANGE IN 110 OF 500%.
34 CHANGE IN IL OF +500% AT VIN= 1V.
35 CHANGE IN IR OF +500% AT VBR= 30V.
36 CHANGE IN IR OF +500% AT VR= 50V.
37 CHANGE IN IR OF 500% AT VBR= 1OV.
38 CHANGE IN IR OF 500% AT VR= 35V.
39 CHANGE IN IS OF 500% AT VS= -TOY.
40 CHANGE IN RESISTANCE OF .1%.
41 CHANGE IN RESISTANCE OF 2%.
42 CHANGE IN VOL OF .050V AT VCCz 4.5V,IOL= 2MA AND VIN= 2 0V.
43 CHANGE OF 0.5% OR GREATER TOLERANCE.
44 CHANGED IN IV CHARACTERISTICS WITH INPUTS HIGH.
45 CHECK FOR ANY CHANGE IN FORWARD VOLTAGE AND REVERSE LEAKAGE CURRENT.
46 CUMULATIVE LEAKAGE CURRENT.
47 D.C. PARAMETER OUT OF SPEC.
48 DAMAGE TO INPUT DIODE.
49 DEGRADATION OF V-I CURVE OR FUNCTIONAL FAILURE.
51 DEVICE CONSIDERED ESD SENSITIVE WHEN A 1O%CHANGE IN ELECT. CHAR. WAS OBSERVED.
51 ELECTRICAL PARAMETERS OUT OF SPEC.
52 EXCESSI'E LEAKAGE CURRENT OR OPEN CONDUCTOR LINES.
53 FAILEO THE DC ELECTRICAL PARAMETERS TEST LIMITS.
44
RAC ESD DATABASE
Table 4 - FAILURE CRITERIA LISTING (Cont'd)
54 FAILED VOLTAGE IS THE AVERAGE OF PARTS SAMPLED.

55 FAILS TO MEET ELECTRICAL SPECIFICATION.
56 FUNCTION FAILURE OR D.C. PARAMETER OUT OF SPEC.
57 FUNCTIONAL FAILURE.
58 GATE CURRENT GREATER THAN 5UA AT A GATE/SOURCE VOLTAGE OF 22 VOLTS.
59 GREATER THAN .5UA INPUT AT 1OV.
60 GREATER THAN IuA LEAKAGE CURRENT AT 1.5 VOLTS.
61 GREATER THAN 5uA LEAKAGE CURRENT AT 0.5 VOLTS.
62 ID= SHORT.
63 IDSS OUT OF SPEC.
64 IEB AT VEB= +6V +1000% CHANGE.
65 IEBO AT VEB= -6V +1000% CHANGE.
66 IEBO AT VEB= 2.5V +1000% CHANGE.
67 IEBO AT VEB= 3.5V 1000% CHANGE.
68 IF AC,DC,OR FUNCTIONAL PARAMETERS FAILS THE MIN. OR MAX. LIMITS.
69 IGSS AND V(BR)GSS OUT OF SPEC.
70 IGSS AT VGS= -20V +1000% CHANGE.
71 IGSS OUT OF SPEC.
72 IGSSR >25PA AT VGS= 8V AND VDS= OV.
73 IGSSR AND IDSS OUT OF SPEC.
74 IGSSR AND VGS(TH) OUT OF SPEC.
75 IGSSR OUT OF SPEC.
76 IGSSR,VGS(TH) OR IDSS OUT OF SPEC.
77 IIH AND VR OUT OF SPEC.
78 IIH AND/OR VOL OUT OF SPEC.
79 IIH AND/OR VR OUT OF SPEC.
80 IIH OUT OF SPEC.
81 IIH, IIL, OR ISS OUT OF SPEC AT VDD=15V.
82 IIH,IIL,ISS OUT OF SPEC.
83 IIH,IIL,OR ISS OUT OF SPEC.
84 IIH,VF,OR VR OUT OF SPEC.
85 IIH= lOMA.
86 IIH= 16MA.
87 IIH= 97UA.
88 IIL OUT OF SPEC.
89 IL AT VR= .5V 300%.
90 IL AT VR= 50V +1000% CHANGE.
91 INPUT BREAKDOWN OF 5MV.
92 INPUT SHORTED TO VCC.
93 INPUTS SHORTED TO GROUND.
9. IR AND VB OUT OF SPEC.
95 IR GREATER THAN 100% CHANGE.
96 IR OUT OF SPEC.
97 IR= 300UA AT 50 VOLTS.
98 IZ AT VR= 5V +1000% CHANGE.
99 IZ AT VR= 6.5V +1000% CHANGE.
100 LEAKAGE CURRENT.
101 LIGHT OUTPUT DEGRADAIION AT CONSTANT CURRENT.
102 N/R.
103 PARAMETER CHANGE OF GREATER THAN 10%.
104 PARAMETER SHIFT OF GREATER THAN 10%.
105 PASSED FUNCTIONALLY OR DC ELECTRICAL PARAMETERS.
106 RESISTANCE CHANGE OF 1%.
45
RAC ESD DATABASE
Table 4 - FAILURE CRITERIA LISTING (Cont'd)
107 RESISTANCE OUT OF SPEC.

108 SIGNIFICANT AMOUNT OF DEGRADATION TO V-I CURVE.
109 SIGNIFICANT CHANGE IN THE +INPUT -GROUND V-I CURVE.
110 STUDY OF BREAKDOWN CHARACTERISTIC OF INPUT AND OUTPUT PINS.
111 TEST LEAKAGE CURRENT.
112 TESTED TO 2000 VOLTS PER METHOD 3015.2 OF MIL-STD-883.
113 V(BR)GSS OUT OF SPEC.
114 VB OUT OF SPEC.
115 VEBO= IV. TYPICALLY 5 VOLTS.
116 VGS(OFF) OUT OF SPEC AND IGSSR >25PA AT VGS= 8V AND VDS= OV.
117 VGS(OFF) OUT OF SPEC AND/OR IGSSR >2SPA AT VGS= 8V AND VDS= OV.
118 VGS(OFF) OUT OF SPEC AT VDS= 15V AND ID= 50UA.
119 VGS(TH) AND ISS OUT OF SPEC.
120 VGS(TH) OUT OF SPEC.
121 VR OUT OF SPEC.
122 WHEN ONE PULSE RESULTED IN DECREASE REV. LEAKAGE OR DECREASE IN JUNC. BRKDWN. VOLT.
123 WHEN ONE PULSE RESULTED IN INCREASE REV. LEAKAGE OR DECREASE IN JUNC. BRKDWN. VOLT.
46
RAC ESD DATABASE
Table 5 - TEST REMARKS LISTING
CODE TEST REMARKS
1 1-DEV. IR SHORT, 3-100% CHANGE, 1-25% CHANGE, 5- NO CHANGE. 5 PULSES FWD & REV.
2 1.13M OHM MODEL.
3 1.1M OHM MODEL.
4 1.21M OHM MODEL.
5 1.58M OHM MOOEL.
6 1.69M OHM MODEL.
7 1.78M OHM MODEL.
8 10 MHZ CRYSTAL OSCILLATOR.
9 10 OHM MODEL.
10 10000 VOLTS IS AN AVERAGE OF AN UNKNOWN NUMBER OF DEVICES.
11 107 OHM MODEL.
12 11.8 OHM MODEL.
14 133K OHM MODEL.
15 1400 VOLTS IS AN AVERAGE OF 3 DEVICES.
16 140K OHM MODEL.
18 150K OHM MODEL.
23 IM OHM MODEL.
24 2 DEVICES INCREASED IR FROM .09, .095 TO .85, .65uA. 5 PULSES FWD & REVERSE.
25 2 OUT OF 9 DEVICES TESTED FAILED.
26 2.1M OHM MODEL.
27 2.49M OHM MODEL.
28 2.6% OF TOTAL NUMBER OF PINS FAILED.
29 2.94M OHM MODEL.
30 20.5 OHM MODEL.
31 220 OHM MODEL.
32 232K OHM MODEL.
33 24.9 OHM MODEL.
34 240K OHM MODEL.
35 250 OHM MODEL.
36 250K OHM MODEL.
38 270K OHM MODEL.
39 294K OHM MODEL.
40 d97K OHM MODEL.
41 3.01M OHM MODEL.
42 301 OHM MODEL.
44 330 OHM MODEL.
45 360.1K OHM MODEL.
46 38/PIN DEVICE CMOS, GATE ARRAY, SEMICUSTOM, MONOLITHIC.
47 383 OHM MODEL.
48 392K OHM MODEL.
49 4.37 OHM MODEL.
51 400K OHM MODEL.
53 47.5 OHM MODEL.
47
RAC ESD DATABASE
Table 5 - TEST REMARKS LISTING (Cont'd)
CODE TEST REMARKS

55 475K OHM MODEL.
56 49.9 OHM MODEL.
57 499 OHM MODEL.
58 5 PULSES APPLIED AT BOTH FORWARD AND REVERSE POLARITIES.
59 5 PULSES FORWARD, 5 PULSES REVERSE.
60 5 PULSES PER POLARITY. DEVICES HAD METAL LID.
61 50 OHM MODEL.
62 50% FAILURE RATE WITH ARCING BETWEEN LEADS.
64 511K OHM RESISTOR.
66 57.6 OHM MODEL.
67 590 OHM MODEL.
69 604K OHM MODEL.
70 665K OHM MODEL.
71 7 OUT OF 10 DEVICES FAILED COLLECTOR TO BASE.
72 768K OHM MODEL.
75 ALL 10 INPUTS FAILED TO VSS AT 800 VOLTS.
76 ALL UNUSED INPUTS AT 5.5 VOLTS.
77 ALL UNUSED INPUTS AT GROUND.
78 ALSO DEGRADATION FROM COMMON TO OUTPUT OF 4000 VOLTS.
79 ALSO FAILED 4,5,7-13 TO VDD AT 500 VOLTS.
80 ALSO FAILED FROM 5,6 & 7 TO VSS AT 800 VOLTS.
81 ALSO FAILED FROM ALL OTHER INPUTS TO VSS AT 800 VOLTS.
82 ALSO FAILED FROM INPUT PINS 5,6,8-13 TO VSS AT 800 VOLTS.
83 ALSO FAILED FROM PIN 7 TO OUTPUT AT 1000 VOLTS.
84 ALSO FAILED FROM PINS 4-8 AND 11-13 TO VSS AT 800 VOLTS.
85 ALSO FAILED FROM PINS 5,6,7,11 TO VDD AT 1000 VOLTS.
86 ALSO FAILED FROM PINS 5-13 TO VSS AT 800 VOLTS.
87 ALSO FAILED FROM PINS 8-13 TO VSS AT 800 VOLTS.
88 ALSO FAILED PIN 12 TO VDD AT 500 VOLTS.
89 ALSO FAILED PIN 4 TO VDD, 5-7,9-13 TO OUTPUT AT 500 VOLTS
90 ALSO FAILED PIN 9 TO OUTPUT AT 800 VOLTS.
91 ALSO FAILED PIN 9 TO VOD AND 8 TO OUTPUT AT 1000 VOLTS.
92 ALSO FAILED PIN 9 TO VSS AT 800 VOLTS.
93 ALSO FAILED PINS 4,5 & 9 TO VSS AT 800 VOLTS.
94 ALSO FAILED PINS 5 AND 10 TO VDD AT 800 VOLTS.
95 ALSO FAILED PINS 5-13 TO OUTPUT AT 500 VOLTS
96 ALSO FAILED PINS 5-13 TO VSS AT 800 VOLTS
97 ALSO INPUT TO GND DEGRADED AT 1800 VOLTS.
98 ALSO SHOWED DEGRADATION ON INPUT TO INPUT AT 2000 VOLTS.
99 AVERAGE FAILURE VOLTAGE FOR ALL PINS IS 100OV.
100 AVERAGE FA!IURE VOLTAGE FOR ALL PINS IS 1020V.
101 AVERAGE FAILLRr ."LTAGE FOR ALL PINS IS 1025V.
102 AVERAGE FAILUmE VOLTAGE FOR ALL PINS IS 1060V.
103 AVERAGE FAILURE VOLTAGE FOR ALL PINS IS 1070V.
48
RAC ESD DATABASE
CODE TEST REMARKS

124 AVERAGE FAILURE VOLTAGE FOR ALL PINS IS 300OV.
142 AVG OF ALL INPUTS 940V, PINS 1,2,15 MOST SUSCEPTIBLE.
143 AVG OF ALL INPUTS 960V, PIN 15 MOST SUSCEPTIBLE.
144 AVG OF ALL INPUTS 960V, PINS 11,14 MOST SUSCEPTIBLE.
145 BOTH POLARITIES WERE TESTED.
146 BREAKDOWN VOLTAGE CHARACTERISTICS WERE DEGRADED.
147 CARRY LOOK AHEAD GENERATOR.
148 CATASTROPHIC FAILURES OBSERVED ARE DUE TO EMIT. CONTACT PENETRATING THE SILICON.
149 CHARGED DEVICE MODEL.
150 COLLECTOR TO BASE FOUND TO BE MOST SENSITIVE (BOTH POLARITIES).
151 COMMON TO OUTPUT SHOWED DEGRADATION AT 4000 VOLTS.
152 CRYSTAL (4 Mnz).
153 DAMAGE OBSERVED AT -700 VOLTS, FAILED AT 1100 VOLTS.
154 DAMAGE OBSERVED AT 1000 VOLTS, ALL PINS FAILED AT OR BEFORE 3500 VOLTS.
155 DAMAGE OBSERVED AT 1050 VOLTS, ALL INPUT PINS FAILED AT OR BEFORE 2000 VOLTS.
156 DAMAGE OBSERVED AT 150 VOLTS, ALL DEVICES FAILED AT OR BEFORE 400 VOLTS.
157 DATE CODE TESTED WERE BETWEEN 8134 TO 8715.
158 DEGRADATION OCCURRED AT 1000V.
49
RAC ESD DATABASE
CODE TEST REMARKS
160 DEGRADATION OCCURRED AT 200OV.

164 DEGRADATION OCCURRED AT THE APPLIED VOLTAGE.
165 DELAY LINE, PULSE, ELECTROMAGNETIC, LUMPED CONSTANT, 16 PIN DIP.
166 DEVICE PASSED THE REVERSE V-I CURVE AFTER TESTING.
167 DIFFERENT PIN COMB. TESTED AT EACH VOLTAGE STEP.
168 DRIVER / RECEIVER.
169 DUAL PNP TRANSISTOR.
170 EACH PIN STRESSED WITH ALL OTHER PINS CONNECTED TO GROUND.
171 EACH PIN TESTED TO ALL OTHERS TIED TOGETHER.
172 EMITTER TO BASE FAILED AT 3500 VOLTS.
173 FAILED FROM PINS 4,8,13 TO VDD AND 10 TO OUTPUT AT 500 V.
174 FAILED INPUTS TO GND. VOLT IS AVG. OF 4 DEV. MEAN ENGY=16UJ.
175 FAILED PIN 13 TO VDD AT 500 V, 8 TO VSS, 6 TO VDD AT 800 V.
176 FAILED PIN 16 TO VDD AT 500 V & PIN 5 TO VSS AT 800 V.
177 FAILED PINS 13 TO VDD AND PIN 4 TO OUTPUT AT 800 VOLTS.
178 FAILED PINS 5-6,11-13 TO VSS 7 TO VDD & 8-10 TO OUTPUT 50OV.
179 FAILED PINS 5-7,9,11 TO VSS 8,10,12 TO VDD AT 500 VOLTS.
180 FAILED PINS 5-8 & 10-13 TO VSS & PIN 9 TO VDD AT 500 VOLTS.
181 FAILED PINS 5-8 & 10-13 TO VSS AT 500V & 9 TO VSS AT 800 V.
182 FAILED PINS 8,13 TO VSS, 15 TO VSS AND 6 TO VDD, ALL AT 80OV.
183 FAILED PINS 8-13 TO VSS AT 300V & PINS 4,6 TO OUTPUT AT 500V
184 FAILURE VOLTAGE FROM EMP DATA & WUNSCH MODEL. (SUPERSAP 2).
185 FAILURE VOLTAGE GIVEN IS APPROXIMATE VALUE ONLY.
186 FAILURE VOLTAGE IS AN AVERAGE OF 15 DEVICES.
187 FAILURE VOLTAGE IS AN AVERAGE.
188 FAILURE VOLTAGE OBTAINED FROM EMP DATA AND EXPONENTIAL MODEL.
189 FAILURE VOLTAGF .AINED FROM EMP DATA AND WUNSCH MODEL.
190 FAILURE VOLTAGE OBTAINED FROM EMP DATA.
191 FAILURES WERE DUE TO INCREASED CONTACT RESISTANCE.
192 FIVE PULSES BOTH POLARITY ACROSS EACH PIN COMBINATION.
193 FREQUENCY SYNTHESIZER.
194 HEX SCHMIDTT TRIGGER.
195 HYBRID, OSCILLATOR.
196 IMCS TO >17.5KV, PAL TESTER TO >43KV. PAL IS A MOTOROLA IN HOUSE BUILT TESTER.
197 IN MOST FAILURES, Vos STARTS FAILING FIRST. THEN, Ios,IB,AND Icc.
198 INITIAL IGSS IS 0.1uA AND FINAL IGSS IS lOuA.
199 INITIAL IGSS IS 3.8uA AND FINAL IGSS IS 1OuA.
200 INITIAL IGSS WAS O.luA AND FINAL IGSS WAS 1.OuA.
201 INITIAL IGSS WAS O. IA A,.: THE IiNAL luo: wAS .
202 INITIAL IGSS WAS 1.OuA AND FINAL IGSS WAS 3.4uA.
203 INITIAL IGSS WAS 1uA AND FINAL IGSS WAS 10uA.
204 INPUT AND CLAMPING DIODES WERE TYPICAL FAILURES.
205 INPUT fkILED AT 2500 AND 3000 VOLTS, OUTPUT DID NOT FAIL.
206 INPUT PIN 1 FAILED AT 200V AND INPUT PIN 8 FAILED AT 30OV.
207 INPUT PIN I FAILED AT 200V AND INPUT PIN 8 FAILED AT 400V.
208 INPUT PIN 1 FAILED AT 200V.
209 INPUT PIN 1 FAILED AT 30OV.
210 INPUT PIN 1 FAILED AT 400V AND INPUT PIN 8 FAILED AT 50OV.
211 INPUT PIN 1 FAILED AT 50OV.
50
RAC ESD DATABASE
CODE TEST REMARKS

215 INPUT PIN 2 FAILED AT 40Ov.
220 INPUT PINS 1 AND 8 FAILED AT 300V.
222 INPUT PINS 1 AND 8 FAILED AT 50OV.
229 INPUT TO COM. 3000 V, OUTPUT TO COMMON FAIL AT 1600 VOLTS.
230 INPUT TO OUTPUT DEGRADATED AT 600 VOLTS.
231 INPUTS STRESSED NO PINS GND CAP. OF PACKAGE TO GND IS 290PF.
232 INPUTS STRESSED NO PINS GND CAP. OF PACKAGE TO GND IS 3.5PF.
235 INPUTS STRESSED NO PINS GNO CAP. OF PACKAGE TO GND IS 6.5PF.
236 INTEL METHOD.
237 INTEL MODEL.
238 IR CHANGED FROM .045uA TO 22.JuA ON ONE DEVICE. 5 PULSES FORWARD AND REVERSE.
239 IR CHANGED FROM .l03uA, 200V TO .4uA, 80 VOLTS. 5 PULSES FORWARD & REVERSE.
240 IR DOUBLED AFTER 400 VOLTS, SHORTED AFTER 500 VOLTS.
241 IR INCREASED FROM .05uA TO 148uA. 5 PULSES FORWARD, 5 PULSES REVERSE.
242 IR INCREASED FROM .19MA TO .23MA. 5 PULSES FORWARD, 5 PULSES REVERSE.
243 IR INCREASED ON 3 DEVICES; 5.4 TO 6.2uA, 3.7 TO 4.1uA, AND 4.6 TO 5.6uA.
244 JUNCTION IS DAMAGED BEFORE DEVICE FAILS ELECTRICALLY.
245 LED DEVICES WHICH HAVE REV BRKDWN DAMAGE CAUSED BY ESD MAY FUNC NORM IN FWD DIR.
246 MICROCONTROLLER.
247 MIL-STD-8838 METHOD 3015 (CAT 8), DEVICE PASSED 2000V TEST.
248 MIMIMUM OBSERVED DAMAGE WAS 200 VOLTS ALL DEVICES FAILED AT OR BELOW 300 VOLTS.
249 MIMIMUM OBSERVED DAMAGE WAS 500 VOLTS ALL INPUT PINS FAILED AT OR BEFORE 700 V.
250 MINIMUM OBSERVED WAS 2600 VOLTS, ALL DEVICES FAILED AT OR BEFORE 3000 VOLTS.
251 MODULATOR.
252 N/R.
253 NO DEGRADATION TO OUTPUT AT 4000 VOLTS.
254 NO DEGRADATION TO OUTPUT PINS.
255 NO FAILURES OBSERVED GATE TO CATHODE.
256 OF 4 DEVICES FAILURE VOLTAGE WAS FROM 1400V TO 6000 VOLTS.
257 OF THE FOUR DEVICES TESTED TWO DEVICE DATE CODES WERE GIVEN AS 8615 AND 8501.
258 ONE DEVICE IR SHORTED. 5 PULSES FORWARD, 5 PULSES REVERSE.
259 OTHER PINS OPEN.
260 OTHER PINS TIED TO GND.
261 PAL TESTER IS A MOTOROLA IN HOUSE BUILT IMCS TO >17.5KV, PAL TO >43KV.
262 PIN UNDER TEST STRESSED WITH ALL OTHERS TIED TOGETHER FLOATING.
263 PINS 1 AND 2 FAILED AT 1100 VOLTS.
264 PINS 11-14 TO VSS,15 TO VDD AT 800V,8,13 TO OUTPUT AT 1000V.
265 PINS 13 TO VSS, 9 TO VSS AT 1000V, 8 TO VDD AT 1000 VOLTS.
51
RAC ESD DATABASE
Table 5 - TEST REMARKS LISTING (Con'.i
TEST REMARKS
266 PINS 3,4,5, AND 22 FAILED AT 1200 VOLTS.

267 PINS 8-15 TO VSS AT 500V, 11 TO OUTPUT AT 500 VOLTS.
268 PINS THAT FAILED 3,6-8,11,14,15,17-21, AND 23.
26V PRECISION MOTION CONTROLLER.
270 PROGRAMMABLE BAND PASS FILTER.
271 PROGRAMMABLE INTERVAL TIMER.
272 QUAD DEVICE, ONE DIODE PER DEVICE TESTED.
273 SEMI-CUSTOM GATE ARRAY.
274 SERIAL INPUT PLL FREQUENCY SYNTHESIZER.
275 TEST PREPARED AT 25 DEGREES C.
276 THE MOST SENSITIVE PIN TESTED IS B.
277 THE MOST SENSITIVE PIN TESTED IS G.
278 THE MOST SENSITIVP PINS TESTED ARE C TO B.
279 THE MOST SENSITIVE PINS TESTED ARE C TO E.
280 THE MOST SENSITIVE PINS TESTED ARE E TO B.
281 THE MOST SENSITIVE PINS TESTED ARE G AND D TO S.
282 THE MOST SENSITIVE PINS TESTED ARE S AND D TO G.
283 THE MOST SENSITIVE PINS TESTED ARE S AND G TO D.
284 VOLTAGE IS AN AVERAGE OF 12 RESISTORS. MEAN ENERGY OF 48UJ.
285 VOLTAGE IS AN AVERAGE OF 4 DEVICES.
286 VOLTAGE IS AN AVERAGE OF ALL INPUTS.
287 WORST CASE PINS (+) 1-4,9,10,20,23-27(-)1,1O.LOT # (413,410-1).
2d8 WORST CASE PINS (+) 4-6,22,23,25-27 (-) 20,21. LOT # (284/006,285/008,416-3).
289 ZERO OHMS MODEL.
52
RAC ESD DATABASE
Table 6 - GENERAL REMARKS LISTING
CoL CNERAL REMARKS
1 5 PULSES /-.
2 ALL PINS BUT PIN UNDER TEST CONNECTED TO GND VIA RESISTOR. VDD AND VSS GROUNDED.
3 5EGIN WITH 20OV, INCR. 1OV TO 1000V, INCR. 200V TO 200OV, INCR 500V TO 4000V.
CHARGED DEVICE MODEL.
S DATA OBTAINED FROM WEIBULL PLOTS. STEPS WERE 20% OF AN UNKNOWN STARTING VOLTAGE.
6 -EVICE PASSED REVERSE V-I CURVE. FORWARD AND REVERSE POLARITY TESTED.
7 FAI'ED vOLTAGE IS THE AVERAGE OF PARTS SAMPLED.
S FAILURE VOLTAGE OBTAINED FROM EMP DATA AND EXPONENTIAL MODEL.
9 FAILURE VOLTAGES GIVEN ARE VOLTAGE TO CAUSE 30% FAILURE. DETAILS UNKNOWN.
10 !MCS TESTER TO >17.5KV, PAL TESTER TO >43KV. ONE PULSE PER VOLTAGE INCREMENT.
11 IN ACCORDANCE WITH MIL-STD-883B METHOD 3015 (CAT B), DEVICE PASSED 2000V TESTING.
12 MODEL 900.
13 N/R.
14 PIN COMBINATIONS AND POLARITY DIFFER FOR EACH OF THE FOUR PULSES.
15 P'N UNDER TEST STRESSED WITH ALL OTHER PINS TIED TOGETHER GROUNDED.
16 PIN UNDER TEST STRESSED WITH ALL OTHER PINS.
17 START 100V WITH INCREMENTS OF 100V TO IO00V. THEN INCREMENTS OF 250V TO FAILURE.
18 STEP STRESS TEST WAS PERFORMED HOWEVER ACTUAL VOLTAGE STEPS WERE UNKNOWN.
19 STEPPED FROM 1800 VOLTS TO FAILURE IN 25 VOLT INCREMENTS.
20 STEPPED IN 100 VOLT INCREMENTS STARTING AT 400 VOLTS.
21 STEPPED IN 2.5 VOLT INCREMENTS.
22 STEPPED IN 25 VOLT INCREMENTS.
23 STRESSED IN INCREMENTS OF 20% STARTING AT 16V FOR MOS DEVICES AND 70V FOR OTHERS.
24 TEST VOLTAGE WAS INCREMENTED FROM 100V TO 5500V IN 100V STEPS.
25 TESTED TO 2000 VOLTS PER METHOD 3015.2 OF MIL-STD-883.
26 TESTER IS A MARTIN MARIETTA IN HOUSE BUILT.
27 THERE WERE ALSO 100V INCREMENTS STEPPED FROM 100V TO 800V.
28 VOLT INCREMENTS AS FOLLOWS:100V TO 1KV,250V TO 3KV,500V TO 6KV,AND 1KV TO 16KV.
29 VOLTAGE STEP LEVELS 100 VOLT INCREMENTS UP TO 4000 VOLTS.
53
54
SECTION 3.1
MICROCIRCUIT SUSCEPTIBILITY TEST DATA
55
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RAC ESD Database
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1 ELECTROSTATIC

l Reliability Analysis Center

Publication of this information is not an expression of the opinion of The

A\,a!. " Ior

Under contract to:

Rome Air Development Center

Reliability Analysis Center

REQUEST FOR TECHNICAL ALL OTHER REQUESTS

Reliability Analysis Center Rome Air Development Center

Technical Inquiries: (315) 337-9933 Telephone: (315) 330-4920

C 1989, lIT Research Institute

Reliability Analysis Ctr. RADC/RBE

ORGANIZATION (If applicable)

DLA/DTIC I DTIC/DF F30602-87-C-0228

Alexandria, VA 22314-6145 65802S 1.0

Electrostatic Discharge Susceptibility Data

20 DISTRIBUTION/AVAILABILITY OF ABSTRACT 21 ABSTRACT SECURITY CLASSIFICATION

SECTION 2.0 FAILURE VOLTAGE PROFILE 15

SECTION 3.0 DETAILED DEVICE SUSCEPTIBILITY TEST DATA 39

APPENDICES (VOLUME II)

APPENDIX A DERIVATION OF DATA CONVERSION FORMULA 589

FIGURE 1 EMP VS. ESD DATA COMPARISON 10

FIGURE 22 FAILURE VOLTAGE PROFILE-ALL FET 27

1.2 USEOFTHIS DATA

MIL-STD-1686A covers the requirements for the establishment and implementation of an

(a) ESD sensitivity as specified in the applicable part specification, or

(c) Classified in accordance with Appendix B, or,

Before the updates of DOD-STD-1686 to MIL-STD-1686A and MIL-STD-883 Method

V1 = standard human body model damage threshold

The derivation of this equation may be found in Appendix A.

1.4 CONVERSION OF EMP OVERSTRESS TEST DATA TO THE ESD

V 2VD + / 4VD 2 + 1200 K 1 (7.675 x 10-7) - K2 1530 + VD

The derivation of this equation may be found in Appendix A (Volume II).

FIGURE 1: EMP VS. ESD DATA

1.5 VARIABILITY ASSOCIATED WITH CONVENTIONAL TEST METHIODS

• Arcing of the high voltage switching relay.

(2) Identify differences in these distributions between two typical simulators.

1.6 SUMMARY AND CONCLUSIONS

This publication presents the most comprehensive compendium of electrostatic discharge

1 ti ,(, 15) ;2 450 2750 3050 330 3610 J3950 4250

S 300 C100 2900 3200 3 50) 3600 4100

FIGURE 2: FAILURE DISTRIBUTION FOR TESTER #1

1650 2150 2450 2750 3050 33b0 365,0 3950 4250

FIGURE 3: FAILURE DISTRIBUTION FOR TESTER #2

FIGURE 4: STEP-STRESS RESULTS FOR 74F04

FIGURE 5: STEP-STRESS RESULTS FOR 74FI75

FAILURE VOLTAGE PROFILE

9 1500- 99 2--2 99 500 -3999

FAILURE VOLTAGE PROFILE

-- 4 ',IO - 1 411- 2 r:00 - 1' ,1, -7co %(3 O - 3

-99 1000-149 2000-2499 3000-35499 > =4000

FLURE VOLTrAGE PROFILE

< 49 1000-1499 2000--2409 3000-3499 > =-OO©

<0499 1 000-1499 2000-2499 3000-3499 > -4 000

500-999 1500-1999 2500-2999 3500-3999

FAILURE VOLTAGE PROFILE OF

SC)00- 1 ,49 20 - 2000 - 349 >=40C

FAILURE VOLTAGE PROFILE

=49 1000-1499 2000-2499 3000-3499 >=40C0

FAILURE VOLTAGE PROFILE