The Processor

Lecture # 11
Course Instructor: Dr. Afshan Jamil
Outline
• Pipelined datapath
• Single cycle datapath-steps
• Bug in the datapath
• Corrected datapath
• Pipeline example
• Pipeline control
Pipelined Datapath
• We now move to building a pipelined datapath
• First recall the 5 steps in instruction execution
1. Instruction Fetch & PC Increment (IF)
2. Instruction Decode and Register Read (ID)
3. Execution or calculate address (EX)
4. Memory access (MEM)
5. Write result into register (WB)
• Review: single-cycle processor
– all 5 steps done in a single clock cycle
– dedicated hardware required for each step
Pipelined Datapath – Key Idea

• What happens if we break the execution into

multiple cycles, but keep the extra hardware?
– Answer: We may be able to start executing
a new instruction at each clock cycle -
pipelining
• …but we shall need extra registers to hold
data between cycles – pipeline registers
Single-Cycle Datapath “Steps”
Pipelined Datapath
Pipeline registers wide enough to hold data coming in
 Pipelined Datapath

Only data flowing right to left may cause hazard…, why?

Bug in the Datapath

Write register number comes from another later

instruction!
Corrected Datapath

Destination register number is also passed through ID/EX, EX/MEM

and MEM/WB registers, which are now wider by 5 bits
Pipelined Example

• Consider the following instruction sequence:

ld x3, 10(x22)
sd x6, 20(x22)
add x19, x20, x21
sub x5, x7, x8
Clock Cycle 1
ld

<<
1

32 6
4
Clock Cycle 2
SW LW

<<
1

32 6
4
Clock Cycle 3
ADD SW LW

<<
1

32 6
4
Clock Cycle 4
SUB ADD SD
LD

<<
1

32 6
4
Clock Cycle 5
SUB ADD SD LD

<<
1

32 6
4
Clock Cycle 6
SUB ADD SW

<<
1

32 6
4
Clock Cycle 7
SUB ADD

<<
1

32 6
4
Clock Cycle 8
SUB

<<
1

32 6
4
Alternative View – Multiple-
Clock-Cycle Diagram
CC 1 CC 2 CC 3 CC 4 CC 5 CC 6 CC 7 CC 8
Time axis
ld x3, 10(x22) IM REG ALU DM REG

sw x6, 20(x22) IM REG ALU DM REG

add 19, x20, x21 IM REG ALU DM REG

sub x5, x7, x8 IM REG ALU DM REG

Example
• Consider the following five instruction sequence:
– ld x10, 40(x1)
– sub x11, x2, x3
– add x12, x3, x4
– ld x13, 48(x1)
– add x14, x5, x6
Multiple clock cycle Pipeline diagram
CONTD…
Clock cycle 5
Recall Single-Cycle Control – the Datapath
Pipeline Control

• Initial design – motivated by single-cycle datapath control – use

the same control signals
• Observe:
– No separate write signal for the PC as it is written every cycle
– No separate write signals for the pipeline registers as they
are written every cycle
– No separate read signal for instruction memory as it is read
every clock cycle
– No separate read signal for register file as it is read every
clock cycle
CONTD…

• Need to set control signals during each

pipeline stage
• Since control signals are associated with
components active during a single pipeline
stage, can group control lines into five
groups according to pipeline stage
Pipelined Datapath with Control I
Pipeline Control Signals

Write-back
Execution/Address Calculation Memory access stage stage control
stage control lines control lines lines
Reg ALU ALU ALU Mem Mem Reg Mem to
Instruction Dst Op1 Op0 Src Branch Read Write write Reg
R-format 1 1 0 0 0 0 0 1 0
ld 0 0 0 1 0 1 0 1 1
sd X 0 0 1 0 0 1 0 X
beq X 0 1 0 1 0 0 0 X
Pipelined Control
• Control signals derived from instruction
– As in single-cycle implementation
Pipelined Control