MODULE 2

INTRODUCTION TO 16 BIT PROCESORS

The 16 bit Microprocessor means that it has 16 address lines.
A 16 bit microprocessor is having 16bit register set. It have 16 address and data
lines to transfer address and data both. Hence it is 16 address lines. The
maximum addresses are 2^16 means 65536.
The term is often applied to the following: microprocessor: indicates the width of
the registers. A 16-bit microprocessor can process data and memory addresses
that are represented by 16 bits. bus : indicates the number of wires in the bus. A
16-bit bus transmits 16 bits in parallel.
8086 Microprocessor is an enhanced version of 8085Microprocessor that was designed by
Intel in 1976. It is a 16-bit Microprocessor having 20 address lines and16 data lines that
provides up to 1MB storage. It consists of powerful instruction set, which provides operations
like multiplication and division easily.
It supports two modes of operation, i.e. Maximum mode and Minimum mode. Maximum
mode is suitable for system having multiple processors and Minimum mode is suitable for
system having a single processor.

8086 microprocessor
Intel 8086 FEATURES
o Intel 8086 microprocessor is the enhanced version of Intel 8085 microprocessor. It
was designed by Intel in 1976.
o The 8086 microprocessor is a16-bit, N-channel, HMOS microprocessor. Where the
HMOS is used for "High-speed Metal Oxide Semiconductor".
o Intel 8086 is built on a single semiconductor chip and packaged in a 40-pin IC
package. The type of package is DIP (Dual Inline Package).
o Intel 8086 uses 20 address lines and 16 data- lines. It can directly address up to 2 20 =
1 Mbyte of memory.
o It consists of a powerful instruction set, which provides operation like division and
multiplication very quickly.
o 8086 is designed to operate in two modes, i.e., Minimum and Maximum mode.

Difference between 8085 and 8086 Microprocessor

 8085 Microprocessor 8086 Microprocessor

It is an 8-bit microprocessor. It is a 16-bit microprocessor.

It has a 16-bit address line. It has a 20-bit address line.

It has a 8-bit data bus. It has a 16-bit data bus.

The memory capacity is 64 KB. The memory capacity is 1 MB.

The Clock speed of this microprocessor is 3 MHz. The Clock speed of this microprocessor v
between 5, 8 and 10 MHz for different versions.

It has five flags. It has nine flags.

8085 microprocessor does not support memory 8086 microprocessor supports memory segmenta
segmentation.

It does not support pipelining. It supports pipelining.

It is accumulator based processor. It is general purpose register based processor.

It has no minimum or maximum mode. It has minimum and maximum modes.

In 8085, only one processor is used. In 8086, more than one processor is used
additional external processor can also be employe

It contains less number of transistors compare to 8086 It contains more number of transistors compa
microprocessor. It contains about 6500 transistor. 8085 microprocessor. It contains about 29000 in s

The cost of 8085 is low. The cost of 8086 is high.

8086 has two operating Modes:  

1. Minimum mode
2. Maximum mode
Minimum mode:
 In this 8086 is the only processor in the system . In a minimum
mode 8086 system.
 8086 is operated in minimum mode when MN/MX’ pin to logic 1.
  In this mode, all the control signals are given out by the 8086 itself.
  Maximum mode: 
 In this we can connect more processors to 8086 (8087/8089).
 8086 max mode is basically for implementation of allocation of
global resources and passing bus control to other coprocessor(i.e.
second processor in the system), because two processors can not
access system bus at same instant.
 All processors execute their own program.
 The resources which are common to all processors are known as
global resources.
 The resources which are allocated to a particular processor are
known as local or private resources.

Architecture of 8086
The following diagram depicts the architecture of a 8086 Microprocessor −

8086 Microprocessor is divided into two functional units, i.e., EU (Execution Unit)

and BIU (Bus Interface Unit).

EU (Execution Unit)
Execution unit gives instructions to BIU stating from where to fetch the data and then decode
and execute those instructions. Its function is to control operations on data using the
instruction decoder & ALU. EU has no direct connection with system buses as shown in the
above figure, it performs operations over data through BIU.
Let us now discuss the functional parts of 8086 microprocessors.
ALU
It handles all arithmetic and logical operations, like +, −, ×, /, OR, AND, NOT operations.
Flag Register
It is a 16-bit register that behaves like a flip-flop, i.e. it changes its status according to the
result stored in the accumulator. It has 9 flags and they are divided into 2 groups −
Conditional Flags and Control Flags.
Conditional Flags
It represents the result of the last arithmetic or logical instruction executed. Following is the
list of conditional flags −
 Carry flag − This flag indicates an overflow condition for arithmetic
operations.
 Auxiliary flag − When an operation is performed at ALU, it results in a
carry/barrow from lower nibble (i.e. D0 – D3) to upper nibble (i.e. D4 – D7),
then this flag is set, i.e. carry given by D3 bit to D4 is AF flag. The processor
uses this flag to perform binary to BCD conversion.
 Parity flag − This flag is used to indicate the parity of the result, i.e. when the
lower order 8-bits of the result contains even number of 1’s, then the Parity
Flag is set. For odd number of 1’s, the Parity Flag is reset.
 Zero flag − This flag is set to 1 when the result of arithmetic or logical
operation is zero else it is set to 0.
 Sign flag − This flag holds the sign of the result, i.e. when the result of the
operation is negative, then the sign flag is set to 1 else set to 0.
 Overflow flag − This flag represents the result when the system capacity is
exceeded.
Control Flags
Control flags controls the operations of the execution unit. Following is the list of control
flags −
 Trap flag − It is used for single step control and allows the user to execute one
instruction at a time for debugging. If it is set, then the program can be run in a
single step mode.
 Interrupt flag − It is an interrupt enable/disable flag, i.e. used to
allow/prohibit the interruption of a program. It is set to 1 for interrupt enabled
condition and set to 0 for interrupt disabled condition.
 Direction flag − It is used in string operation. As the name suggests when it is
set then string bytes are accessed from the higher memory address to the lower
memory address and vice-a-versa.
General purpose register
There are 8 general purpose registers, i.e., AH, AL, BH, BL, CH, CL, DH, and DL. These
registers can be used individually to store 8-bit data and can be used in pairs to store 16bit
data. The valid register pairs are AH and AL, BH and BL, CH and CL, and DH and DL. It is
referred to the AX, BX, CX, and DX respectively.
 AX register − It is also known as accumulator register. It is used to store
operands for arithmetic operations.
 BX register − It is used as a base register. It is used to store the starting base
address of the memory area within the data segment.
 CX register − It is referred to as counter. It is used in loop instruction to store
the loop counter.
 DX register − This register is used to hold I/O port address for I/O instruction.
Stack pointer register
It is a 16-bit register, which holds the address from the start of the segment to the memory
location, where a word was most recently stored on the stack.

BIU (Bus Interface Unit)

BIU takes care of all data and addresses transfers on the buses for the EU like sending
addresses, fetching instructions from the memory, reading data from the ports and the
memory as well as writing data to the ports and the memory. EU has no direction connection
with System Buses so this is possible with the BIU. EU and BIU are connected with the
Internal Bus.
It has the following functional parts −
 Instruction queue − BIU contains the instruction queue. BIU gets upto 6
bytes of next instructions and stores them in the instruction queue. When EU
executes instructions and is ready for its next instruction, then it simply reads
the instruction from this instruction queue resulting in increased execution
speed.
 Fetching the next instruction while the current instruction executes is
called pipelining.
 Segment register − BIU has 4 segment buses, i.e. CS, DS, SS& ES. It holds
the addresses of instructions and data in memory, which are used by the
processor to access memory locations. It also contains 1 pointer register IP,
which holds the address of the next instruction to executed by the EU.
o CS − It stands for Code Segment. It is used for addressing a
memory location in the code segment of the memory, where the
executable program is stored.
o DS − It stands for Data Segment. It consists of data used by the
program andis accessed in the data segment by an offset address
or the content of other register that holds the offset address.
o SS − It stands for Stack Segment. It handles memory to store
data and addresses during execution.
o ES − It stands for Extra Segment. ES is additional data segment,
which is used by the string to hold the extra destination data.
  Instruction pointer − It is a 16-bit register used to hold the address of the next
instruction to be executed.

8086 was the first 16-bit microprocessor available in 40-pin DIP (Dual Inline Package) chip.
Let us now discuss in detail the pin configuration of a 8086 Microprocessor.

8086 Pin Diagram

Here is the pin diagram of 8086 microprocessor −

Let us now discuss the signals in detail −

Power supply and frequency signals
It uses 5V DC supply at VCC pin 40, and uses ground at VSS pin 1 and 20 for its operation.
Clock signal
Clock signal is provided through Pin-19. It provides timing to the processor for operations. Its
frequency is different for different versions, i.e. 5MHz, 8MHz and 10MHz.
Address/data bus
AD0-AD15. These are 16 address/data bus. AD0-AD7 carries low order byte data and
AD8AD15 carries higher order byte data. During the first clock cycle, it carries 16-bit
address and after that it carries 16-bit data.
Address/status bus
A16-A19/S3-S6. These are the 4 address/status buses. During the first clock cycle, it carries
4-bit address and later it carries status signals.
S7/BHE
BHE stands for Bus High Enable. It is available at pin 34 and used to indicate the transfer of
data using data bus D8-D15. This signal is low during the first clock cycle, thereafter it is
active.
Read($\overline{RD}$)
It is available at pin 32 and is used to read signal for Read operation.
Ready
It is available at pin 22. It is an acknowledgement signal from I/O devices that data is
transferred. It is an active high signal. When it is high, it indicates that the device is ready to
transfer data. When it is low, it indicates wait state.
RESET
It is available at pin 21 and is used to restart the execution. It causes the processor to
immediately terminate its present activity. This signal is active high for the first 4 clock
cycles to RESET the microprocessor.
INTR
It is available at pin 18. It is an interrupt request signal, which is sampled during the last
clock cycle of each instruction to determine if the processor considered this as an interrupt or
not.
NMI
It stands for non-maskable interrupt and is available at pin 17. It is an edge triggered input,
which causes an interrupt request to the microprocessor.
$\overline{TEST}$
This signal is like wait state and is available at pin 23. When this signal is high, then the
processor has to wait for IDLE state, else the execution continues.
MN/$\overline{MX}$
It stands for Minimum/Maximum and is available at pin 33. It indicates what mode the
processor is to operate in; when it is high, it works in the minimum mode and vice-aversa.
INTA
It is an interrupt acknowledgement signal and id available at pin 24. When the
microprocessor receives this signal, it acknowledges the interrupt.
ALE
It stands for address enable latch and is available at pin 25. A positive pulse is generated each
time the processor begins any operation. This signal indicates the availability of a valid
address on the address/data lines.
DEN
It stands for Data Enable and is available at pin 26. It is used to enable Transreceiver 8286.
The transreceiver is a device used to separate data from the address/data bus.
DT/R
It stands for Data Transmit/Receive signal and is available at pin 27. It decides the direction
of data flow through the transreceiver. When it is high, data is transmitted out and vice-a-
versa.
M/IO
This signal is used to distinguish between memory and I/O operations. When it is high, it
indicates I/O operation and when it is low indicates the memory operation. It is available at
pin 28.
WR
It stands for write signal and is available at pin 29. It is used to write the data into the
memory or the output device depending on the status of M/IO signal.
HLDA
It stands for Hold Acknowledgement signal and is available at pin 30. This signal
acknowledges the HOLD signal.
HOLD
This signal indicates to the processor that external devices are requesting to access the
address/data buses. It is available at pin 31.
QS1 and QS0
These are queue status signals and are available at pin 24 and 25. These signals provide the
status of instruction queue. Their conditions are shown in the following table −

QS0 QS1 Status

0 0 No operation

0 1 First byte of opcode from the queue

1 0 Empty the queue

1 1 Subsequent byte from the queue

S 0, S 1, S 2
These are the status signals that provide the status of operation, which is used by the Bus
Controller 8288 to generate memory & I/O control signals. These are available at pin 26, 27,
and 28. Following is the table showing their status −
 S2 S1 S0 Status

0 0 0 Interrupt acknowledgement

0 0 1 I/O Read

0 1 0 I/O Write

0 1 1 Halt

1 0 0 Opcode fetch

1 0 1 Memory read

1 1 0 Memory write

1 1 1 Passive

LOCK
When this signal is active, it indicates to the other processors not to ask the CPU to leave the
system bus. It is activated using the LOCK prefix on any instruction and is available at pin
29.
RQ/GT1 and RQ/GT0
These are the Request/Grant signals used by the other processors requesting the CPU to
release the system bus. When the signal is received by CPU, then it sends acknowledgment.
RQ/GT0 has a higher priority than RQ/GT1.

Register organization OF 8086

➢ 8086 has a powerful set of registers known as general purpose registers and special
purposeregisters.

➢ All of them are 16-bit registers.

➢ General purpose registers:

o These registers can be used as either 8-bit registers or 16-bitregisters.

o They may be either used for holding data, variables and intermediate results temporarily or for
other

purposes like a counter or for storing offset address for some particular addressing modes etc.

➢ Special purpose registers:

o These registers are used as segment registers, pointers, index registers or as offset storage
registers

for particular addressing modes.

➢ The 8086 registers are classified into the following types:

o General Data Registers

o Segment Registers

o Pointers and Index Registers

o Flag Register

General Data Registers:

➢ The registers AX, BX, CX and DX are the general purpose 16-bit registers.

➢ AX is used as 16-bit accumulator. The lower 8-bit is designated as AL and higher 8-bit is
designated as AH.AL

can be used as an 8-bit accumulator for 8-bit operation.

➢ All data register can be used as either 16 bit or 8 bit. BX is a 16 bit register, but BL indicates the
lower 8-bitof

BX and BH indicates the higher 8-bit of BX.

➢ The register BX is used as offset storage for forming physical address in case of certain addressing
modes.

➢ The register CX is used default counter in case of string and loop instructions.

➢ DX register is a general-purpose register which may be used as an implicit operand or destination

in case of

a few instructions.

Segment Registers:

➢ There are 4 segment registers. They are:

o Code Segment Register (CS)

o Data Segment Register (DS)

o Extra Segment Register (ES)

o Stack Segment Register (SS)

➢ The 8086 architecture uses the concept of segmented memory. 8086 able to address a memory
capacity of 1

megabyte and it is byte organized. This 1-megabyte memory is divided into 16 logical segments.
Each segment

contains 64 Kbytes of memory.

➢ Code segment register (CS): is used for addressing memory location in the code segment of the
memory,

where the executable program is stored.

➢ Data segment register (DS): points to the data segment of the memory where the data isstored.
➢ Extra Segment Register (ES) : also refers to a segment in the memory which is another data
segment in the

memory.

➢ Stack Segment Register (SS): is used for addressing stack segment of the memory. The stack
segment is that

segment of memory which is used to store stack data.

➢ While addressing any location in the memory bank, the physical address is calculated from two
parts:

Physical address= segment address + offset address

➢ The first is segment address, the segment registers contain 16-bit segment base addresses,
related to different

segment.

➢ The second part is the offset value in that segment.

Pointers and Index Registers:

➢ The index and pointer registers are given below:

o IP—Instruction pointer-store memory location of next instruction to be executed

o BP—Base pointer

o SP—Stack pointer

o SI—Source index

o DI—Destination index

➢ The pointers registers contain offset within the particular segments.

o The pointer register IP contains offset within the code segment.

o The pointer register BP contains offset within the data segment.

o Thee pointer register SP contains offset within the stack segment.

➢ The index registers are used as general purpose registers as well as for offset storage in case of
indexed, base

indexed and relative base indexed addressing modes.

➢ The register SI is used to store the offset of source data in data segment.

➢ The register DI is used to store the offset of destination in data or extra segment.

➢ The index registers are particularly useful for string manipulation.

8086 flag register and its functions:

➢ The 8086 flag register contents indicate the results of computation in the ALU. It also contains
some flag bits

to control the CPU operations.

➢ A 16 bit flag register is used in 8086. It is divided into two parts .

o Condition code or status flags

o Machine control flags

➢ The condition code flag register is the lower byte of the 16-bit flag register. The condition code
flag register is

identical to 8085 flag register, with an additional overflow flag.

➢ The control flag register is the higher byte of the flag register. It contains three flags namely
direction flag (D),

interrupt flag (I) and trap flag (T).

Flag register configuration

The description of each flag bit is as follows:

SF- Sign Flag: This flag is set, when the result of any computation is negative. For signed
computations the sign flag

equals the MSB of the result.

ZF- Zero Flag: This flag is set, if the result of the computation or comparison performed by the
previous instruction is

zero.

PF- Parity Flag: This flag is set to 1, if the lower byte of the result contains even number of 1’s.

CF- Carry Flag: This flag is set, when there is a carry out of MSB in case of addition or a borrow in
case of subtraction.

AF-Auxilary Carry Flag: This is set, if there is a carry from the lowest nibble, i.e, bit three during
addition, or borrow for

the lowest nibble, i.e, bit three, during subtraction.

OF- Over flow Flag: This flag is set, if an overflow occurs, i.e, if the result of a signed operation is
large enough to

accommodate in a destination register. The result is of more than 7-bits in size in case of 8-bit signed
operation and

more than 15-bits in size in case of 16-bit sign operations, and then the overflow will be set.
TF- Tarp Flag: If this flag is set, the processor enters the single step execution mode. The processor
executes the

current instruction and the control is transferred to the Trap interrupt service routine.

IF- Interrupt Flag: If this flag is set, the mask able interrupts are recognized by the CPU, otherwise
they are ignored.

D- Direction Flag: This is used by string manipulation instructions. If this flag bit is ‘0’, the string is
processed beginning

from the lowest address to the highest address, i.e., auto incrementing mode. Otherwise, the string
is processed from

the highest address towards the lowest address, i.e., auto decrementing mode

Memory Segmentation in 8086 Microprocessor

Segmentation is the process in which the main memory of the computer is
logically divided into different segments and each segment has its own base
address. It is basically used to enhance the speed of execution of the
computer system, so that the processor is able to fetch and execute the data
from the memory easily and fast.
Need for Segmentation –
The Bus Interface Unit (BIU) contains four 16 bit special purpose registers
(mentioned below) called as Segment Registers.
 Code segment register (CS): is used for addressing memory
location in the code segment of the memory, where the executable
program is stored.
 Data segment register (DS): points to the data segment of the
memory where the data is stored.
 Extra Segment Register (ES): also refers to a segment in the
memory which is another data segment in the memory.
 Stack Segment Register (SS): is used for addressing stack
segment of the memory. The stack segment is that segment of
memory which is used to store stack data.
The number of address lines in 8086 is 20, 8086 BIU will send 20bit address,
so as to access one of the 1MB memory locations. The four segment
registers actually contain the upper 16 bits of the starting addresses of the
four memory segments of 64 KB each with which the 8086 is working at that
instant of time. A segment is a logical unit of memory that may be up to 64
kilobytes long. Each segment is made up of contiguous memory locations. It
is an independent, separately addressable unit. Starting address will always
be changing. It will not be fixed.
Note that the 8086 does not work the whole 1MB memory at any given time.
However, it works only with four 64KB segments within the whole 1MB
memory.Below is the one way of positioning four 64 kilobyte segments within
he 1M byte memory space of an 8086.

Types Of Segmentation –
1. Overlapping Segment – A segment starts at a particular address
and its maximum size can go up to 64kilobytes. But if another
segment starts along with this 64kilobytes location of the first
segment, then the two are said to be Overlapping Segment.
2. Non-Overlapped Segment – A segment starts at a particular
address and its maximum size can go up to 64kilobytes. But if
another segment starts before this 64kilobytes location of the first
segment, then the two segments are said to be Non-Overlapped
Segment.
Rules of Segmentation Segmentation process follows some rules as
follows:
 The starting address of a segment should be such that it can be
evenly divided by 16.
 Minimum size of a segment can be 16 bytes and the maximum can
be 64 kB.

Advantages of the Segmentation The main advantages of

segmentation are as follows:
  It provides a powerful memory management mechanism.
 Data related or stack related operations can be performed in
different segments.
 Code related operation can be done in separate code
segments.
 It allows to processes to easily share data.
 It allows to extend the address ability of the processor, i.e.
segmentation allows the use of 16 bit registers to give an
addressing capability of 1 Megabytes. Without segmentation,
it would require 20 bit registers.
 It is possible to enhance the memory size of code data or
stack segments beyond 64 KB by allotting more than one
segment for each area.

What is Memory Mapped IO

Memory mapped IO uses one address space for memory and input and output
devices. In other words, some addresses are assigned to memory while others
are assigned to store the addresses of IO devices. There is one set of read and
write instruction lines. The same set of instructions work for both memory and
IO operations. Therefore, the instructions used to manipulate memory can be
used for IO devices too.  Hence, it can lessen the addressing capability of
memory because some are occupied by the IO. 

Figure 1: IO Devices and Memory in Computer

What is IO Mapped IO
IO mapped IO uses two separate address spaces for memory locations and for
IO devices. There are two separate control lines for both memory and IO
transfer. In other words, there are different read-write instruction for both IO
and memory. IO read and IO write are for IO transfer whereas memory read and
memory write are for memory transfer. IO mapped IO is also called port-
mapped IO or isolated IO.

Difference between Memory-Mapped I/O Interfacing and I/O Mapped I/O

Interfacing :
Features Memory Mapped IO IO Mapped IO
IO devices are accessed like They cannot be accessed like
Addressing any other memory location. any other memory location.

They are assigned with 16-bit They are assigned with 8-bit
Address Size address values. address values.

The instruction used are LDA The instruction used are IN

Instructions Used and STA, etc. and OUT.

Cycles involved during

Cycles involved during operation are IO read and IO
operation are Memory Read, writes in the case of IO
Cycles Memory Write. Mapped IO.

Any register can Only Accumulator can

communicate with the IO communicate with IO
Registers device in case of Memory devices in case of IO
Communicating Mapped IO. Mapped IO.

216 IO ports are possible to be Only 256 I/O ports are

used for interfacing in case of available for interfacing in
Space Involved Memory Mapped IO. case of IO Mapped IO.

During writing or read cycles During writing or read cycles

(IO/M` = 0 ) in case of (IO/M` = 1) in case of IO
IO/M` signal Memory Mapped IO. Mapped IO.

No separate control signal

required since we have Special control signals are
unified memory space in the used in the case of IO
Control Signal case of Memory Mapped IO. Mapped IO.
 Arithmetic and logical
operations cannot be
Arithmetic and logical performed directly on the
operations are performed data in the case of IO
Arithmetic and directly on the data in the Mapped IO.
Logical operations case of Memory Mapped IO.

General bus operation of 8086

 The 8086 has a combined address and data bus commonly referred as a time
multiplexed address and data bus.
 The main reason behind multiplexing address and data over the same pins is the
maximum utilisation of processor pins and it facilitates the use of 40 pin standard DIP
package.
 The bus can be demultiplexed using a few latches and transreceivers, when ever
required.
 Basically, all the processor bus cycles consist of at least four clock cycles. These
are referred to as T1, T2, T3, T4. The address is transmitted by the processor during T1.
It is present on the bus only for one cycle.
 The negative edge of this ALE pulse is used to separate the address and the data
or status information. In maximum mode, the status lines S0, S1 and S2 are used to
indicate the type of operation.
 Status bits S3 to S7 are multiplexed with higher order address bits and the BHE
signal. Address is valid during T1 while status bits S3 to S7 are valid during T2 through
T4.

Maximum mode
 In the maximum mode, the 8086 is operated by strapping the MN/MX pin to
ground.
 In this mode, the processor derives the status signal S2, S1, S0. Another chip
called bus controller derives the control signal using this status information .
 In the maximum mode, there may be more than one microprocessor in the
system configuration.
Minimum mode
 In a minimum mode 8086 system, the microprocessor 8086 is operated in
minimum mode by strapping its MN/MX pin to logic 1.
 In this mode, all the control signals are given out by the microprocessor chip
itself.
 There is a single microprocessor in the minimum mode system.

I/O ADDRESSING CAPABILITY

 The 8086/8088 processor can address up to 64K byte I/O registers or 32K word registers. The I/O
address appears on the address lines A0 to A15 for one clock cycle (T1). It may then be latched using
the ALE signal. The upper address lines (A16 - A19) are at logic 0 level during the I/O operations.
The 16-bitregister DX is used as 16-bit I/O address pointer, with full capability to address up to 64K
devices. In memory mapped I/O interfacing, the I/O device addresses are treated as memory
locations in page 0, i.e. segment address 0000H.Even addressed bytes are transferred on D7-Do and
odd addressed bytes are transferred on D8-D15 lines.