CHAPTER 5

© 2008 Pearson Education, Inc.

5-1. S_n

R_n

Q_n

0 ps 20 ns 40 ns 60 ns 80 ns

5-2. C
S
R
Q
Q_n

0 ps 50 ns 100 ns 150 ns 200 ns

5-3. C

Q_n

0 ps 50 ns 100 ns 150 ns

5-4.

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 Problem Solutions – Chapter 5

5-5.

Unknown

5-6.

X
Y A
D
Clock C
X
B Z
D
Clock C

Present Next S0 - 00
state Inputs state Output S1 - 01
A B X Y A B Z
S2 - 10
S3 - 11
0 0 0 0 0 0 0
0 0 0 1 0 0 0 Format: XY/Z (X = unspecified)
0 0 1 0 0 0 0 0X/0, X0/0
10/1
0 0 1 1 1 0 0 0X/0
0 1 0 0 0 1 0 S0 S1
0 1 0 1 0 1 0 11/0
0 1 1 0 0 0 1 11/1
0 1 1 1 1 0 1
10/0
1 0 0 0 1 0 0
1 0 0 1 1 0 0 10/1
1 0 1 0 0 1 0 S2 S3
11/0
1 0 1 1 1 1 0 0X/0 0X/0, 11/1
1 1 0 0 1 1 0
1 1 0 1 1 1 0
1 1 1 0 0 1 1
1 1 1 1 1 1 1

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 Problem Solutions – Chapter 5

5-7.*
Present state Input Next state X=0

000 100 110 011

A B C X A B C
0 0 0 0 1 0 0
0 0 0 1 0 0 0 111
001 010 101
0 0 1 0 0 0 0
0 0 1 1 1 0 0
0 1 0 0 0 0 1
0 1 0 1 1 0 1 X=1
0 1 1 0 1 0 1
0 1 1 1 0 0 1 001 100 010 101
1 0 0 0 1 1 0
1 0 0 1 0 1 0
1 0 1 0 0 1 0 000
011 111 110
1 0 1 1 1 1 0
1 1 0 0 0 1 1
1 1 0 1 1 1 1 State diagram is the combination of the above two diagrams.
1 1 1 0 1 1 1
1 1 1 1 0 1 1

5-8.

01/1, 10/1
Present state Inputs Next state Output 00/1, 11/1
00/0, 11/0
Q X Y Q S 0 1

0 0 0 0 0
0 0 1 1 0 01/0, 10/0
0 1 0 1 0
0 1 1 0 0 Format: XY/S
1 0 0 1 1
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

5-9.
Present State 00 01 00 00 01 11 00 01 11 10 10
Input 1 0 0 1 1 0 1 1 1 1 0
Output 0 1 0 0 0 1 0 0 0 0 1
Next State 01 00 00 01 11 00 01 11 10 10 00

5-10.
01/0 00/1
00/0

0 11/0 1
10/1
x0/0, 01/1 11/1 01/1, 10/0

11/1

3 2
x0/1, 01/0
11/0
Format: XY/Z

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 Problem Solutions – Chapter 5

5-11.*
SA = B SB = X ⊕ A
RA = B RB = X ⊕ A 1/1
0/0
0 1
Present state Input Next state Output

A B X A B Y 1/0
0/1 0/1
0 0 0 0 1 0
1/0
0 0 1 0 0 1
0 1 0 1 1 1 2 3
0 1 1 1 0 0 0/0
1/1
1 0 0 0 0 1
1 0 1 0 1 0
Format: X/Y
1 1 0 1 0 0
1 1 1 1 1 1

5-12.
a)

X S
D A

C
A
R

Reset

S
D B
Clock C
B
R

b)

X
D A

C
A

Reset

D B
Clock C
B

63
 Problem Solutions – Chapter 5

5-13.*
DA B DB B
Present state Input Next state
1 1
A B X A B
A 1 1 1 A 1 1 1
0 0 0 0 0
0 0 1 1 0 X X
0 1 0 0 1
0 1 1 0 0 DA = AX + BX DB = AX + BX
1 0 0 1 0
1 0 1 1 1 Logic diagram not given.
1 1 0 1 1
1 1 1 0 1

5-14.
For part a) results, replace codes in table below with state name, e.g., 00 with A.
Present state Inputs Next state Output

Q1 Q2 X1 X2 Q1(t+1) Q2(t+1) Z Encoding:

0 0 0 0 0 0 0
State Code (Q1Q2)
0 0 0 1 0 1 0 A 00
0 0 1 0 0 1 1 B 01
0 0 1 1 0 0 0 C 10
0 1 0 0 0 0 0 D 11
0 1 0 1 0 0 0
0 1 1 0 1 1 1
0 1 1 1 1 1 1
1 0 0 0 0 0 1
1 0 0 1 0 0 0
1 0 1 0 1 0 1
1 0 1 1 1 0 0
1 1 0 0 1 0 1
1 1 0 1 0 1 1
1 1 1 0 0 1 0
1 1 1 1 1 0 1

Q1
Q2

Q1
Q1 Q2

Q2

Q1

Q2

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 Problem Solutions – Chapter 5

5-15.
Encoding:
Next State Q(t+1) State Code (Q1Q2Q3)
Present state For Input Output A 010
Q(t) X=0 X= 1 Z B 100
A B D 0 C 110
B D C 0 D 001
E 011
C A F 0
F 101
D F C 1
E C E 1 Unused states: 000, 111. The state assignment
F E F 1 could be different. E.g. states A, B or C could be 000
and states D, E or F could be 111.

Q1

Q2

Q3

5-16.
Encoding:
Next State
State Code (Q1Q2Q3) Q(t+1)
A 000 Present state For Input Output
B 001
Q(t) X=0 X=1 Z
C 010
D 011 A C E 0
E 101 B E D 1
F 110 C C E 0
D F A 1
E B D 1
F C E 0

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 Problem Solutions – Chapter 5

Next State States A, C, F are equivalent and merged to get state M.

Output
Q(t+1) States B and E are equivalent and merged to get state N.
Present state For Input State D becomes state O.
Q(t) X=0 X=1 X
Encoding: Z is a state variable and an output, and
M M N 0 Y is a state variable.
N N O 1
O M M 0 State Code (Y Z)
M 00
N 01
DY = YZX DZ = ZX + YZ O 11
Gate input cost of the original circuit: 21 + 42 = 63
Gate input cost of the new circuit: 9 + 28 = 37

5-17.
Present state Inputs Next state Output DA = AXA + BX B + CXC + DX D
ABCDE Xa Xb Xc Xd ABCDE U DB = AX A
10000 0 x x x 10000 0 DC = BX B
10000 1 x x x 01000 0 DD = CX C
01000 x 0 x x 10000 0 DE = E + DXD
01000 x 1 x x 00100 0 U=E
00100 x x 0 x 10000 0 Signal L is applied to the asynchronous
00100 x x 1 x 00010 0 set/reset inputs on the flip-flops to implement
00010 x x x 0 10000
0 0 locking.
00010 x x x 1 00001 0
00001 x x x x 00001 1

E
U

66
 Problem Solutions – Chapter 5

5-18.*
Format: XY/Z (x = unspecified)
Present state Inputs Next state Output
x1/x
00/0 00/1 Q(t) X Y Q(t+1) Z
x1/x 10/0
0 1 0 0 0 0 0
0 0 1 0 X
0 1 0 1 1
10/1 0 1 1 0 X
1 0 0 1 1
1 0 1 0 X
1 1 0 1 0
1 1 1 0 X

5-19.
E=0

0/0 1/0 2/0 3/0 4/0 5/0 6/0 7/1

E=1

The state assignment could be different.

Next State
Present state For Input Output
E. g., state 7 could be 000 with state 0
001. This would permit use of R inputs
D2 D1 D0 E=0 E=1 Z on the D flip-flops for RESET.
000 001 001 0
001 010 010 0
010 011 011 0
011 100 100 0
100 101 101 0
101 110 110 0
110 111 111 0
111 111 000 1

RESET
S D0
E D

S D1
D Z

S D2
D

C
CLK

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 Problem Solutions – Chapter 5

5-20.
E=0

0/0 1/1 2/1 3/1 4/1 5/1 6/1 7/0

E=1

Assumes for E = 0, the output remains

at 0.
Next State
Present state For Input Output

D2 D1 D0 E=0 E=1 Z
000 001 001 0
001 010 010 1
010 011 011 1
011 100 100 1
100 101 101 1
101 110 110 1
110 111 111 1
111 111 000 0

RESET
S
E D

S
D Z
C

S
D

C
CLK

5-21.+
X=0/Z=0,S=0

X=1/Z=1,S=0
0 1 Present state Input Next state Output
X=x/
Z=0,S=1 X=0/Z=0,S=0 X=1/
Z=1,S=0 A B C X A B C Z S
X=0/ 0 0 0 0 0 0 0 0 0
Z=0, X=0/ 0 0 0 1 0 0 1 1 0
5 S=0 Z=0,S=0 2
0 0 1 0 0 0 0 0 0
0 0 1 1 0 1 0 1 0
X=0/ X=1/
X=1/ Z=0,S=0 0 1 0 0 0 0 0 0 0
Z=1,S=0
Z=1,S=0 0 1 0 1 0 1 1 1 0
0 1 1 0 0 0 0 0 0
4 3 0 1 1 1 1 0 0 1 0
X=1/Z=1,S=0
1 0 0 0 0 0 0 0 0
1 0 0 1 1 0 1 1 0
1 0 1 0 0 0 0 0 1
1 0 1 1 0 0 0 0 1

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 Problem Solutions – Chapter 5

D Z
X C

D S
C

C
CLK

5-22.
X=1 / Z=1 X=1 / Z=0
X=0 / Z=0 Present Next
0 1 state Input state Output

X=0 / Z=1 A X A Z
0 0 1 0
0 1 0 1
1 0 0 1
1 1 1 0

X
D

CR
Z
CLK
RESET

5-23.+
X=1 / Z=1 X=0 / Z=1
X=1 / Z=0 Present Next
0 1 state Input state Output

X=0 / Z=0 A X A Z
0 0 1 0
0 1 0 1
1 0 1 1
1 1 0 0

X
D
Z

CR
CLK
RESET

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 Problem Solutions – Chapter 5

5-24.
Format: RA/E (x = unspecified) xx/1

x1/1 100
0x/1 1x/1
00/0 10/0 x0/1 01/0
11/0

Reset 000 10/0 001 11/0 010 01/0 011

00/0

Present state Inputs Next state Output Present state Inputs Next state Output

B C D R A B C D E B C D R A B C D E
0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0
0 0 0 0 1 1 0 0 1 0 1 1 0 1 0 1 1 0
0 0 0 1 0 0 0 1 0 0 1 1 1 0 1 0 0 1
0 0 0 1 1 1 0 0 1 0 1 1 1 1 1 0 0 1
0 0 1 0 0 1 0 0 1 1 0 0 0 0 1 0 0 1
0 0 1 0 1 1 0 0 1 1 0 0 0 1 1 0 0 1
0 0 1 1 0 0 0 1 0 1 0 0 1 0 1 0 0 1
0 0 1 1 1 0 1 0 0 1 0 0 1 1 1 0 0 1
0 1 0 0 0 1 0 0 1
0 1 0 0 1 0 1 1 0
0 1 0 1 0 1 0 0 1
0 1 0 1 1 0 1 0 0

5-25.
Format: XY/Z (x = unspecified)
Present state Input Next state Output

A X Y A Z 11/1
0x/0 10/1
0 0 0 0 0 x0/0
0 0 1 0 0
0 1
0 1 0 1 1
0 1 1 0 1
x1/0
1 0 0 1 0
1 0 1 0 0
1 1 0 1 0
1 1 1 0 0

70
 Problem Solutions – Chapter 5

5-26.*
To use a one-hot assignment, the two flip-flops A and B
No Reset State Specified.
need to be replaced with four flip-flops Y4, Y3, Y2. Y1.
D1 = Y1’= X·Y1 + X·Y4
Present State Input Next State Output
D2 = Y2’ = X·Y1 + X·Y2
AB Y4 Y3 Y2 Y1 X A’ B" Y4’Y3’Y2’Y1 Z D3 = Y3’ = X·Y2 + X·Y3
0 0 0 0 0 1 0 0 1 0 0 1 0 1 D4 = Y4’ = X·Y3 + X·Y4
0 0 0 0 0 1 1 0 0 0 0 0 1 1
0 1 0 0 1 0 0 0 1 0 0 1 0 0
0 1 0 0 1 0 1 1 0 0 1 0 0 0
1 0 0 1 0 0 0 1 1 1 0 0 0 0
1 0 0 1 0 0 1 1 0 0 1 0 0 0
1 1 1 0 0 0 0 1 1 1 0 0 0 0
1 1 1 0 0 0 1 0 0 0 0 0 1 0

Y1
D Y

Y2
D
C

Y3
D
C

Y4
D

Clock

5-27.*
a) b) Format: SR
S R Q
0 0 Q No Change 10,11
0 1 0 Reset 00,01 00, 10, 11
1 0 1 Set 0 1
1 1 1 Set
01

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 Problem Solutions – Chapter 5

c)
Present state Input Next state

Q S R Q(t+1) A B
0 0 0 0 0 x
0 0 1 0 0 x
0 1 0 1 1 0
0 1 1 1 1 0
1 0 0 1 x 0
1 0 1 0 0 1
1 1 0 1 x 0
1 1 1 1 x 0

A=S
B = SR
A Q
S
S B
R
R
Clock

5-28.+
Present State Next State a) DA = C c, d, e, f) The circuit is suitable for child’s toy, but not for life criti-
cal applications. In the case of the child’s toy, it is the
ABC ABC DB = A
cheapest implementation. If an error occurs the child just
000 100 DC = B needs to reset it. In life critical applications, the immedi-
001 000 ate detection of errors is critical. The circuit above enters
b) Clear A = Reset
010 XXX invalid states for some errors. For a life critical applica-
011 001 Clear B = Reset tion, additional circuitry is needed for immediate detec-
100 110 Clear C = Reset tion of the error (Error = ABC + ABC). This circuit using
101 XXX
the design in a), does return from the invalid states to a
110 111
111 011 valid state automatically after one or two clock periods.

5-29.
Verification
Specification

Present state Input Next state Next state

Q S R Q(t+1) A B A B Q(t+1)
0 0 0 0 0 x 0 0 0
0 0 1 0 0 x 0 1 0
0 1 0 1 1 0 1 0 1
0 1 1 1 1 0 1 0 1
1 0 0 1 x 0 0 0 1
1 0 1 0 0 1 0 1 0
1 1 0 1 x 0 1 0 1
1 1 1 1 x 0 1 0 1

72
 Problem Solutions – Chapter 5

5-30.
Clock
Reset
X
Y
A
B

0 ps 20 ns 40 ns 60 ns 80 ns

5-31.*
2 8 3 Reset, 00, 01, 00, 01, 11, x0, x0, 01, 10,
1 00/1
00/0 01/0 01, 01, 11, 11, 11, 10.
RESET 0 11/0 1
14
7 11 10/1
4 9
x0/0, 01/1 12 11/1 01/1, 10/0
15
11/1

3
13 2
x0/1, 01/0
11/0
6 10 5
Format: XY/Z

5-32.

Z
X A
D

Y C

B
D
C
Clock

Clock
Reset
X
Y
A
B

0 ps 20 ns 40 ns 60 ns 80 ns

73
 Problem Solutions – Chapter 5

5-33.*
Clock

0 ps 50 ns 100 ns 150 ns

This simulation was performed without initializing the state of the latches of the flip-flop beforehand.
Each gate in the flip-flop implementation has a delay of 1 ns. The interaction of these delays with the
input change times produced a narrow pulse in Y at about 55 ns. In this case, the pulse is not harmful
since it dies out well before the positive clock edge occurs. Nevertheless, a thorough examination of such
a pulse to be sure that it does not represent a design error or important timing problem is critical.

5-34.
Function table for the LH flip-flop.

C L D Q(t+1) S R
0 X X No change X X
1 0 X No change 0 0
1 1 0 0 0 1
1 1 1 1 1 0

LH flip-flop and SR latch in a master-slave circuit:

5-35.

Y1

State table:

State State Transition Next State Non-zero

Code Condition State Code Outputs
A 00 X A 00
X B 01
Y2
B 01 X/Z
Y A 00
Y C 10
C 10 Y/Z
X D 11
X A 00
D 11 Z
XY + XY D 11
XY + XY C 10

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 Problem Solutions – Chapter 5

5-36.
Constraint 1 checks on the transition conditions (TC):
Init: There is one pair of TCs to check: (STA R T + STOP ) S
· TART· S T O P = 0
Fill_1: There are three pairs of TCs to check: L 1 · S T O P · STOP = 0,
L 1 · S T O P · L1· S T O P = 0,
STOP · L1· S T O P = 0
Fill_2: There are six pairs of TCs to check: L2 · N I · S T O P · STOP = 0,
L2 · N I · S T O P · L 2 · S T O P = 0,
L2 · N I · S T O P · L2· NI · S T O P = 0,
STOP · L 2 · S T O P = 0,
STOP · L2· NI · S T O P = 0,
L 2 · S T O P · L2· NI · S T O P = 0
Fill_3: There are three pairs of TCs to check: L 3 · S T O P · STOP = 0,
L 3 · S T O P · L3· S T O P = 0,
STOP · L3· S T O P = 0
Mix: There are three pairs of TCs to check: T Z · S T O P · STOP = 0,
T Z · S T O P · TZ· S T O P = 0,
STOP · TZ· S T O P = 0
Empty: There is one pair of TCs to check: L 0 · S T O P · ( L0 + STOP) = 0

Constraint 2 checks on the transition conditions (TC):

Init: S T A R T + STOP + START· S T O P = 1
Fill_1: L 1 · S T O P + STOP + L1· S T O P = 1
Fill_2: L2 · N I · S T O P + STOP + L 2 · S T O P + L2· NI · S T O P = 1
Fill_3: L 3 · S T O P + STOP + L3· S T O P = 1
Mix: T Z · S T O P + STOP + TZ· S T O P = 1
Empty: L 0 · S T O P + L0 + STOP = 1

5-37.*

( )

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 Problem Solutions – Chapter 5

5-38. State Transition Next State Non-zero

State Code Condition State Code Outputs
Init 1000000 N 5¢ 0010000
D 10¢ 0001000
Q Dispense 0000001
N ·D ·Q Init 1000000
Coin_Return RC
0100000 1 Init 1000000
5¢ 0010000 N 10¢ 0001000
D 15¢ 0000100
Q Dispense 0000001
CR Coin_Return 0100000
CR · N · D · Q 5¢ 0010000
10¢ 0001000 N 15¢ 0000100
D 20¢ 0000010
Q Dispense 0000001
CR Coin_Return 0100000
CR · N · D · Q 10¢ 0001000
15¢ 0000100 N 20¢ 0000010
D+Q Dispense 0000001
CR Coin_Return 0100000
CR · N · D · Q 15¢ 0000100
20¢ 0000010 N+D+Q Dispense 0000001
CR Coin_Return 0100000
CR · N · D · Q 20¢ 0000010
Dispense DJ
0000001 1 Init 1000000

D flip-flop inputs:

Init (t + 1) = Init · N · D · Q + Coin_Return + Dispense

Coin_Return (t + 1) = 5¢ · CR + 10¢ · CR + 15¢ · CR + 20¢ · CR

5¢ (t + 1) = Init · N + 5¢ · C R · N · D · Q

10¢ (t + 1) = Init · D + 5¢ · N + 10¢ · C R · N · D · Q

15¢ (t + 1) = 5¢ · D + 10¢ · N + 15¢ · C R · N · D · Q

20¢ (t + 1) = 10¢ · D + 15¢ · N + 20¢ · C R · N · D · Q

Dispense (t + 1) = Q + 15¢ · D + 20¢ · D + 20¢ · N

Outputs:

RC = Coin_Return

DJ = Dispense

5-39.
(a) No_Change
D
D DR
LT2Q
D

DR DR NoCh
DR DR CLOR
D
Q
Q Q Q Q Q Q
Init 25c 50c 75c 100c 125c 150c 200c
Return_2_Quarters
LED
DR DR
Reset
C
L
O
Disp_Orange R Disp_Cola
Disp_Root_Beer Disp_Lemon

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 Problem Solutions – Chapter 5

(b) Some possible changes to the specification follow. 1. Provide appropriate change and dispense soda for the cases
in which 75 cents and 125 cents followed by a dollar have been deposited. Provide a coin return button for the event
that the user is out of quarters and dollars before the 150c state is reached. 3. Change the No Change warning to cover
all added cases in 1.

5-40.*
library IEEE; architecture mux_4to1_arch of mux_4to1 is
use IEEE.std_logic_1164.all; begin

entity mux_4to1 is process (S, D)

port ( begin
S: in STD_LOGIC_VECTOR (1 downto 0); case S is
D: in STD_LOGIC_VECTOR (3 downto 0); when "00" => Y <= D(0);
Y: out STD_LOGIC when "01" => Y <= D(1);
); when "10" => Y <= D(2);
end mux_4to1; when "11" => Y <= D(3);
when others => null;
-- (continued in the next column) end case;

end process;
end mux_4to1_arch;

5-41.
library IEEE; architecture mux_4to1_arch of mux_4to1 is
use IEEE.std_logic_1164.all; begin
entity mux_4to1 is process (S, D)
port ( begin
S: in STD_LOGIC_VECTOR (1 downto 0);
D: in STD_LOGIC_VECTOR (3 downto 0); if S = "00" then Y <= D(0);
Y: out STD_LOGIC elsif S = "01" then Y <= D(1);
); elsif S = "10" then Y <= D(2);
end mux_4to1; elsif S = "11" then Y <= D(3);
else null;
-- (continued in the next column) end if;

end process;
end mux_4to1_arch;

5-42.+
library IEEE; -- Process 2 - next state function
use IEEE.std_logic_1164.all; next_state_func: process (X, state)
entity serial_BCD_Ex3 is begin
port (clk, reset, X : in STD_LOGIC; case state is
Z : out STD_LOGIC); when Init =>
end serial_BCD_Ex3; if (X = '0') then
next_state <= B10;
architecture process_3 of serial_BCD_Ex3 is else
type state_type is (Init, B10, B11, B20, B21, B2X, next_state <= B11;
B3X0, B31); end if;
signal state, next_state: state_type; when B10 =>
begin if (X = '0') then
-- Process 1 - state register next_state <= B20;
state_register: process (clk, reset) else
begin next_state <= B21;
if (reset = '1') then end if;
state <= Init; when B11 =>
else if (CLK'event and CLK='1') then next_state <= B2X;
state <= next_state; when B20 =>
end if; next_state <= B3X0;
end if; when B21 =>
end process; if (X = '0') then
-- (continued in the next column) next_state <= B3X0;

77
 Problem Solutions – Chapter 5

else if (X = '0') then

next_state <= B31; Z <= '1';else
end if; Z<= '0';
when B2X => end if;
if (X = '0') then when B11 =>
next_state <= B3X0; Z <= X;
else when B20 =>
next_state <= B31; Z <= X;
end if; when B21 =>
when B3X0 => if (X = '0') then
next_state <= Init; Z <= '1';
when B31 => else
next_state <= Init; Z <= '0';
end case; end if;
end process; when B2X =>
if (X = '0') then
-- Process 3 -output function Z <= '1';
output_func: process (X, state) else
begin Z <= '0';
case state is end if;
when Init => when B3X0 =>
if (X = '0') then Z <= X;
Z <= '1'; when B31 =>
else Z <= '1';
Z <= '0'; end case;
end if; end process;
when B10 =>
-- (continued in the next column) end process_3;

clk
reset
x
z
state init b10 b20 b3x0 init b10 b20 b3x0 init b10 b21 b3x0 init

0 50 100 150 200 250

clk
reset
x
z
state init b10 b21 b31 init b11 b2x b3x0 init b11 b2x b31 init

250 300 350 400 450 500

5-43.
library IEEE; -- Process 1 - state register
use IEEE.std_logic_1164.all; state_register: process (clk, reset)
entity prob_5_43 is begin
port (clk, reset : in STD_LOGIC; if (reset = '1') then
X : in STD_LOGIC_VECTOR(2 downto 1) ; state <= A;
Z : out STD_LOGIC); elsif (clk'event and clk = '1') then
end prob_5_43; state <= next_state;
end if;
architecture process_3 of prob_5_43 is end process;
type state_type is (A, B, C, D);
signal next_state, state : state_type; -- Process 2 - next state function
begin next_state_func: process (X, state)
begin
-- Continued in next column -- Continued on next page

78
 Problem Solutions – Chapter 5

case state is -- Process 3 -output function

when A => output_func: process (X, state)
case X is begin
when "00" => case state is
next_state <= A; when A =>
when "01" => case X is
next_state <= B; when "00" =>
when "10" => Z <= '0';
next_state <= B; when "01" =>
when "11" => Z <='0';
next_state <= A; when "10" =>
when others => next_state <= A; Z <= '1';
end case; when "11" =>
when B => Z <= '0';
case X is when others => Z <= 'X';
when "00" => end case;
next_state <= A; when B =>
when "01" => case X is
next_state <= A; when "00" =>
when "10" => Z <= '0';
next_state <= D; when "01" =>
when "11" => Z <='0';
next_state <= D; when "10" =>
when others => next_state <= A; Z <= '1';
end case; when "11" =>
when C => Z <= '1';
case X is when others => Z <= 'X';
when "00" => end case;
next_state <= A; when C =>
when "01" => case X is
next_state <= A; when "00" =>
when "10" => Z <= '1';
next_state <= C; when "01" =>
when "11" => Z <='0';
next_state <= C; when "10" =>
when others => next_state <= A; Z <= '1';
end case; when "11" =>
when D => Z <= '0';
case X is when others => Z <= 'X';
when "00" => end case;
next_state <= C; when D =>
when "01" => case X is
next_state <= B; when "00" =>
when "10" => Z <= '1';
next_state <= B; when "01" =>
when "11" => Z <='1';
next_state <= C; when "10" =>
when others => next_state <= A; Z <= '0';
end case; when "11" =>
end case; Z <= '1';
end process; when others => Z <= 'X';
end case;
-- Continued in next column end case;
end process;
end process_3;

79
 Problem Solutions – Chapter 5

5-44.
library IEEE; else
use IEEE.std_logic_1164.all; next_state <= F;
entity prob_5_44 is end if;
port (clk, reset, when D =>
X : in STD_LOGIC; if X = '0' then
Z : out STD_LOGIC); next_state <= F;
end prob_5_44; else
next_state <= C;
architecture process_3 of prob_5_44 is end if;
type state_type is (A, B, C, D, E, F); when E =>
signal state, next_state: state_type; if X = '0' then
begin next_state <= C;
else
-- Process 1 - state register next_state <= E;
state_register: process (clk, reset) end if;
begin when F =>
if (reset = '1') then if X = '0' then
state <= A; next_state <= E;
else if (CLK'event and CLK='1') then else
state <= next_state; next_state <= F;
end if; end if;
end if; end case;
end process; end process;
-- Process 2 - next state function -- Process 3 -output function
next_state_func: process (X, state) output_func: process (X, state)
begin begin
case state is case state is
when A => when A =>
if X = '0' then Z <= '0';
next_state <= B; when B =>
else Z <= '0';
next_state <= D; when C =>
end if; Z <= '0';
when B => when D =>
if X = '0' then Z <= '1';
next_state <= D; when E =>
else Z <= '1';
next_state <= C; when F =>
end if; Z <= '1';
when C => end case;
if X = '0' then end process;
next_state <= A; end process_3;
-- Continued in next column

5-45.*
library IEEE; case J is
use IEEE.std_logic_1164.all; when '0' =>
entity jkff is if K = '1' then
port ( q_out <= '0';
J,K,CLK: in STD_LOGIC; end if;
Q: out STD_LOGIC when '1' =>
); if K = '0' then
end jkff; q_out <= '1';
else
architecture jkff_arch of jkff is q_out <= not q_out;
signal q_out: std_logic; end if;
begin when others => null;
end case;
state_register: process (CLK) end if;
begin end process;
if CLK'event and CLK='0' then --CLK falling edge
Q <= q_out;
-- (continued in the next column) end jkff_arch;

80
 Problem Solutions – Chapter 5

5-46. (Errata: Replace "5-10" with "5-11")

library IEEE; when Fill_3 =>
use IEEE.std_logic_1164.all; if L3 = '1' then
entity prob_5_46 is next_state <= Mix;
port (clk, reset, NI, Start, Stop, L0, L1, L2, L3, TZ : else
in STD_LOGIC; next_state <= Fill_3;
MX, PST, TM, V1, V2, V3, VE : out end if;
STD_LOGIC); when Mix =>
end prob_5_46; if TZ = '1' then
next_state <= Empty;
architecture process_3 of prob_5_46 is else
type state_type is (Init, Fill_1, Fill_2, Fill_3, Mix, next_state <= Mix;
Empty); end if;
signal state, next_state: state_type; when Empty =>
begin if L0 = '1' then
next_state <= Init;
-- Process 1 - state register else
state_register: process (clk, reset) next_state <= Empty;
begin end if;
if (reset = '1') then end case;
state <= Init; end if;
else if (CLK'event and CLK='1') then end process;
state <= next_state;
end if; -- Process 3 - output function
end if; output_func: process (L2, L3, NI, TZ, Stop, state)
end process; begin
MX <= '0';
-- Process 2 - next state function PST <='0';
next_state_func: process (NI, Start, Stop, L0, L1, L2, TM <='0';
L3, TZ, state) V1 <='0';
begin V2 <='0';
if Stop = '1' then V3 <='0';
next_state <= Init; VE <='0';
else case state is
case state is when Init =>
when Init => when Fill_1 =>
if Start = '1' then V1 <= '1';
next_state <= Fill_1; when Fill_2 =>
else V2 <= '1';
next_state <= Init; if ((L2 and not NI and not Stop) = '1') then
end if; PST <= '1';
when Fill_1 => end if;
if L1 = '1' then when Fill_3 =>
next_state <= Fill_2; V3 <= '1';
else if ((L3 and not Stop) = '1') then
next_state <= Fill_1; PST <= '1';
end if; end if;
when Fill_2 => when Mix =>
if L2 = '1' then MX <= '1';
if NI = '1'then if ((not TZ and not Stop) = '1') then
next_state <= Fill_3; TM <= '1';
else end if;
next_state <= Mix; when Empty =>
end if; VE <= '1';
else end case;
next_state <= Fill_2; end process;
end if; end process_3;
-- Continued in next column

81
 Problem Solutions – Chapter 5

5-47.
library IEEE; when S15 =>
use IEEE.std_logic_1164.all; if CR = '1' then
entity prob_5_47 is next_state <= RT;
port (clk, reset, CR, N, D, Q : in STD_LOGIC; elsif N = '1' then
DJ, RC : out STD_LOGIC); next_state <= S20;
end prob_5_47; elsif D = '1' then
next_state <= S25;
architecture process_3 of prob_5_47 is elsif Q = '1' then
type state_type is (S0, S5, S10, S15, S20, S25, RT); next_state <= S25;
signal state, next_state: state_type; else
begin next_state <= S15;
end if;
-- Process 1 - state register when S20 =>
state_register: process (clk, reset) if CR = '1' then
begin next_state <= RT;
if (reset = '1') then elsif N = '1' then
state <= S0; next_state <= S25;
else if (CLK'event and CLK='1') then elsif D = '1' then
state <= next_state; next_state <= S25;
end if; elsif Q = '1' then
end if; next_state <= S25;
end process; else
next_state <= S20;
-- Process 2 - next state function end if;
next_state_func: process (CR, N, D, Q, state) when S25 =>
begin next_state <= S0;
case state is when RT =>
when S0 => next_state <= S0;
if N = '1' then end case;
next_state <= S5; end process;
elsif D = '1' then
next_state <= S10; -- Process 3 - output function
elsif Q = '1' then output_func: process (CR, N, D, Q, state)
next_state <= S25; begin
else DJ <= '0';
next_state <= S0; RC <= '0';
end if; case state is
when S5 => when S25 =>
if CR = '1' then DJ <= '1';
next_state <= RT; when RT =>
elsif N = '1' then RC <= '1';
next_state <= S10; when others => null;
elsif D = '1' then end case;
next_state <= S15; end process;
elsif Q = '1' then end process_3;
next_state <= S25;
else
next_state <= S5;
end if;
when S10 =>
if CR = '1' then
next_state <= RT;
elsif N = '1' then
next_state <= S15;
elsif D = '1' then
next_state <= S20;
elsif Q = '1' then
next_state <= S25;
else
next_state <= S10;
end if;
-- Continued in next column

82
 Problem Solutions – Chapter 5

5-48.
module problem_6_38 (S, D, Y) ; always @(S or D)
begin
input [1:0] S ; case (S)
input [3:0] D ; 2'b00 : Y <= D[0] ;
output Y; 2'b01 : Y <= D[1] ;
reg Y ; 2'b10 : Y <= D[2] ;
2'b11 : Y <= D[3] ;
// (continued in the next column) endcase;
end
endmodule

5-49.*
module problem_6_39 (S, D, Y) ; always @(S or D)
begin
input [1:0] S ; if (S == 2'b00) Y <= D[0];
input [3:0] D ; else if (S == 2'b01) Y <= D[1];
output Y; else if (S == 2'b10) Y <= D[2];
reg Y ; else Y <= D[3];

// (continued in the next column) end

endmodule

5-50.+
//Serial BCD to Excess 3 Converter B2X: if (X ==0)
module serial_BCD_Ex3(clk, reset, X, Z); next_state <= B3X0;
input clk, reset, X; else
output Z; next_state <= B31;
reg[2:0] state, next_state; B3X0: next_state <= Init;
parameter Init = 3'b000, B10 = 3'b001, B31: next_state <= Init;
B11=3'b011, B20= 3'b010, B21 = 3'b110, endcase
B2X = 3'b111, B3X0 = 3'b100, B31 = 3'b101; end
reg Z;

// State Register // Output Function

always@(posedge clk or posedge reset) always@(X or state)
begin begin
if (reset == 1) case (state)
state <= Init; Init: if (X == 0)
else Z <= 1;
state <= next_state; else
end Z <= 0;
B10: if (X == 0)
// Next StateFunction Z <= 1 ;
always@(X or state) else
begin Z <= 0;
case (state) B11: Z <= X;
Init: if (X == 0) B20: Z <= X;
next_state <= B10; B21: if (X == 0)
else Z <= 1;
next_state <= B11; else
B10: if (X == 0) Z <= 0;
next_state <= B20; B2X: if (X == 0)
else Z <= 1;
next_state <= B21; else
B11: next_state <= B2X; Z <= 0;
B20: next_state <= B3X0; B3X0: Z <= X;
B21: if (X == 0) B31: Z <= 1;
next_state <= B3X0; endcase
else end
next_state <= B31; endmodule
// (continued in the next column)

83
 Problem Solutions – Chapter 5

clk
State Assignment
reset
State State X
Code Name Z

000 Init state 000 001 010 100 000 001 010 100 000 001 110 100 000

001 B10
0 50 100 150 200 250
010 B20 clk
011 B11 reset
X
100 B3X0
Z
101 B31 state 000 001 110 101 000 011 111 100 000 011 111 101 000

110 B21
250 300 350 400 450 500
111 B2X

5-51.
// State Diagram in Figure 5-40 using Verilog next_state <= A;
module prob_5_51 (clk, reset, X, Z); else
input clk, reset; next_state <= C;
input[1:2] X; D: if (X == 2'b00 | X == 2'b11)
output Z; next_state <= C;
else
reg[1:0] state, next_state; next_state <= B;
parameter A = 2'b00, B = 2'b01, C = 2'b11, D = 2'b10; endcase
reg Z; end
// State Register // Output Function
always@(posedge clk or posedge reset) always@(X or state)
begin begin
if (reset == 1) case (state)
state <= A; A: if (X == 2'b01 | X == 2'b00 | X == 2'b11)
else Z <= 0;
state <= next_state; else
end Z <= 1;
B: if (X == 2'b10 | X == 2'b11)
// Next StateFunction Z <= 1;
always@(X or state) else
begin Z <= 0;
case (state) C: if (X == 2'b00 | X == 2'b10)
A: if (X == 2'b01 | X == 2'b10) Z <= 1;
next_state <= B; else
else Z <= 0;
next_state <= A; D: if (X == 2'b00 | X == 2'b11 | X == 01)
B: if (X == 2'b10 | X == 2'b11) Z <= 1;
next_state <= D; else
else Z = 0;
next_state <= A; endcase
C: if (X == 2'b00 | X == 2'b01) end
// (continued in the next column) endmodule

84
 Problem Solutions – Chapter 5

5-52.
// State Diagram in Figure 5-41 using Verilog next_state <= F;
module prob_5_52 (clk, reset, X, Z); else
input clk, reset; next_state <= A;
input X; D: if (X == 1)
output Z; next_state <= C;
reg[2:0] state, next_state; else
parameter A = 3'b000, B = 3'b001, next_state <= F;
C = 3'b010, D = 3'b011, E = 3'b100, E: if (X == 1)
F = 3'b101; next_state <= E;
reg Z; else
// State Register next_state <= C;
always@(posedge clk or posedge reset) F: if (X == 1)
begin next_state <= F;
if (reset == 1) else
state <= A; next_state <= E;
else endcase
state <= next_state; end
end
// Next StateFunction // Output Function
always@(X or state) always@(X or state)
begin begin
case (state) case (state)
A: if (X == 1) A: Z <= 0;
next_state <= D; B: Z <= 0;
else C: Z <= 0;
next_state <= B; D: Z <= 1;
B: if (X == 1) E: Z <= 1;
next_state <= C; F: Z <= 1;
else endcase
next_state <= D; end
C: if (X == 1) endmodule
(continued in the next column)

5-53.*
module JK_FF (J, K, CLK, Q) ; always @(negedge CLK)
case (J)
input J, K, CLK ; 0'b0: Q <= K ? 0: Q;
output Q; 1'b1: Q <= K ? ~Q: 1;
reg Q; endcase
endmodule

5-54.
// State Machine for Batch Mixing System (Figure 5-29) if (reset == 1)
module batch_mixing_system (clk, reset, START, STOP, L0, state <= Init;
L1, L2, L3, NI, TZ, V1, V2, V3, PST, MX, TM, VE); else
input clk, reset, START, STOP, L0, L1, L2, L3, NI, TZ; state <= next_state;
output V1, V2, V3, PST, MX, TM, VE; end
reg V1, V2, V3, PST, MX, TM, VE; // Next StateFunction
reg[2:0] state, next_state; always@( START or STOP or L0 or L1 or L2 or L3 or TZ or
parameter Init = 3'b000, Fill_1 = 3'b001, state)
Fill_2 = 3'b010, Fill_3 = 3'b011, Mix = 3'b100, begin
Empty = 3'b101; case (state)
// State Register Init: if (START == 1 & STOP == 0)
always@(posedge clk or posedge reset) next_state <= Fill_1;
begin else
// (continued in the next column) next_state <= Init; // (continued on the next page)

85
 Problem Solutions – Chapter 5

Fill_1: if (STOP == 1) endcase

next_state <= Init; end
else if (L1 == 1) // Output Function
next_state <= Fill_2; always@(L2 or NI or STOP or L3 or TZ or state)
else begin
next_state <= Fill_1; case (state)
Fill_2: if (STOP == 1) Fill_1: V1 <= 0;
next_state <= Init; Fill_2: begin
else if (L2 == 1) V2 <= 0;
if (NI == 1) if (L2 & ~ NI & ~STOP)
next_state <= Fill_3; PST <= 1;
else else
next_state <= Mix; PST <= 0;
else end
next_state <= Fill_2; Fill_3: begin
Fill_3: if (STOP == 1) V3 <= 0;
next_state <= Init; if (L3 & ~STOP)
else if (L3 == 1) PST <= 1;
next_state <= Mix; else
else PST <= 0;
next_state <= Fill_2; end
Mix: if (STOP == 1) Mix: begin
next_state <= Init; MX <= 1;
else if (TZ == 1) if (~TZ & ~STOP)
next_state <= Empty; TM <= 1;
else else
next_state <= Mix; TM <= 0;
Empty: if (STOP == 1 | L0 == 1) end
next_state <= Init; Empty: VE <= 1;
else endcase
next_state <= Empty; end
// (continued in the next column) endmodule

5-55.
// State Machine for Jawbreaker Vending Machine S5c: if (N == 1)
module jawbreaker_vending_machine (clk, reset, CR, N, D, Q, next_state <= S10c;
RC, DJ); else if (D == 1)
input clk, reset, CR, N, D, Q; next_state <= S15c;
output RC, DJ; else if (Q == 1)
reg RC, DJ; next_state <= Dispense;
reg[6:0] state, next_state; else if (CR == 1)
parameter Init = 7'b0000001, S5c = 7'b0000010, next_state <= Coin_Return;
S10c = 7'b0000100, S15c = 7'b0001000, S20c = 7'b0010000, else
Dispense = 7'b0100000, Coin_Return = 7'b1000000; next_state <= S5c;
S10c: if (N == 1)
// State Register next_state <= S15c;
always@(posedge clk or posedge reset) else if (D == 1)
begin next_state <= S20c;
if (reset == 1) else if (Q == 1)
state <= Init; next_state <= Dispense;
else else if (CR == 1)
state <= next_state; next_state <= Coin_Return;
end else
// Next StateFunction next_state <= S10c;
always@(CR or N or D or Q or state) S15c: if (N == 1)
begin next_state <= S20c;
case (state) else if (D == 1)
Init: if (N == 1) next_state <= Dispense;
next_state <= S5c; else if (Q == 1)
else if (D == 1) next_state <= Dispense;
next_state <= S10c; else if (CR == 1)
else if (Q == 1) next_state <= Coin_Return;
next_state <= Dispense; else
else next_state <= S15c;
next_state <= Init; S20c: if (N == 1)
// (continued in the next column) next_state <= Dispense;

86
 Problem Solutions – Chapter 5

;
else if (D == 1) // Output Function
next_state <= Dispense; always@(state)
else if (Q == 1) begin
next_state <= Dispense; RC <= 0;
else if (CR == 1) DJ <= 0;
next_state <= Coin_Return; case (state)
else Dispense: DJ <= 1;
next_state <= S20c; Coin_Return: RC <= 1;
Dispense: next_state <= Init; endcase
Coin_Return: next_state <= Init; end
endcase endmodule
end
(continued in the next column)

87