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NV3029C v0.2

NV3029C 240RGB x 320dot, 262,144-color TFT Controller Driver with Internal RAM NV3029C is a 262,144-color single-chip SOC driver for a-TFT liquid crystal display with resolution of 240RGBx320 dots, comprising a 720-channel source driver, a 320-channel gate driver, GRAM for graphic display data of 240RGBx320 dots, and power supply circuit.

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0% found this document useful (0 votes)

198 views182 pages

NV3029C v0.2

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New Vision Microelectronics Inc.

NV3029C Data Sheet

240RGB x 320dot, 262,144-color

TFT Controller Driver with Internal RAM

Preliminary Version 0.2

December 07, 2012

Dec. 2012 Confidential Information Ver.0.2

Contents

1. Introduction ...................................................................................................................... 4

2. Features ........................................................................................................................... 5

3. Pin Function ..................................................................................................................... 7

4. Pad Arrangement .......................................................................................................... 12

6. Pad Coordinates ............................................................................................................ 14

7. Bump Size...................................................................................................................... 23

8. Command....................................................................................................................... 24

8.1. Command list ................................................................................................................... 24

8.2. Command description....................................................................................................... 30

9. Functional description .................................................................................................. 125

9.1 Module CPU interface ..................................................................................................... 125

9.2 Display Data RAM........................................................................................................... 136

9.3 Tearing effect output line ................................................................................................. 145

9.4 Power On/Off Sequence.................................................................................................. 147

9.5 Power Level Definition..................................................................................................... 150

9.6 8-color Display Mode....................................................................................................... 152

9.7 OTP Operation ................................................................................................................ 152

9.8 Gamma Correction .......................................................................................................... 156

9.9 Voltage Generation ......................................................................................................... 171

9.10 Reset ........................................................................................................................... 173

10. Application.................................................................................................................. 176

New Vision Microelectronics Inc. Page 2

11. Electrical Characteristics............................................................................................ 177

11.1 Absolute Maximum Ratings ........................................................................................... 177

11.2 DC Characteristic .......................................................................................................... 177

11.3 AC Characteristics......................................................................................................... 178

11.4 Timing Characteristics Diagram..................................................................................... 180

Revision history................................................................................................................ 182

New Vision Microelectronics Inc. Page 3

1. Introduction

NV3029C is a 262,144-color single-chip SOC driver for a-TFT liquid crystal display with resolution of
240RGBx320 dots, comprising a 720-channel source driver, a 320-channel gate driver, GRAM for
graphic display data of 240RGBx320 dots, and power supply circuit.

NV3029C supports parallel 8-/9-/16-/18-bit data bus MCU interface, 6-/16-/18-bit data bus RGB
interface and 3-/4-line serial peripheral interface (SPI). The moving picture area can be specified in
internal GRAM by window address function. The specified window area can be updated selectively,
so that moving picture can be displayed simultaneously independent of still picture area.

NV3029C can operate with 1.65V ~ 3.3V I/O interface voltage and an incorporated voltage follower
circuit to generate voltage levels for driving an LCD. NV3029C supports full color, 8-color display
mode and sleep mode for precise power control by software and these features make the NV3029C
an ideal LCD driver for medium or small size portable products such as digital cellular phones,
smart phone, MP3 and PMP where long battery life is a major concern.

New Vision Microelectronics Inc. Page 4

2. Features

¾ One-chip controller driver for 240RGB x 320-dot graphics display in 262,144 colors on TFT
panel
¾ One-chip solution for a-Si TFT panel
¾ System interface
– High-speed interface via 8-, 9-, 16-, 18-bit parallel ports
– Clock synchropadus serial interface
¾ Moving picture display interface
– RGB interface (VSYNC, HSYNC, DOTCLK, ENABLE, DB17-0) via 6-, 16-, 18-bit ports
– VSYNC interface
¾ Window address function to specify a rectangular area in the internal RAM to write data
– Writes data within a rectangular area on the internal RAM via moving picture interface
– Reduces data transfer by specifying the area on the RAM to rewrite data
– Enables displaying the data in the still picture RAM area with a moving picture simultaneously
¾ Color display control functions
– correction function to display in 262k colors
– 1-line unit vertical scroll function
¾ Low -power consumption architecture (allowing direct input of interface I/O power supply)
– 8-color display function
– Input power supply voltages: IOVcc = 1.65V ~ 3.6 V (interface I/O power supply)
Vci = 2.5V ~ 3.3 V (liquid crystal analog circuit power supply)
(Vci-VCL ≤ 6.0V)
¾ Incorporates a liquid crystal drive power supply circuit
– Source driver liquid crystal drive/Vcom power supply: DDVDH-AGND = 4.5V ~ 6.0V
– Gate drive power supply: VGH-VGL ≤ 28.0V
– Vcom drive (Vcom power supply): VcomH = 2.5V ~(DDVDH-0.5)V
VcomL = (VCL+0.5)V ~ GND
¾ Internal liquid crystal drive circuit: 720-channel source output and 320-channel gate output
¾ N-line-inversion liquid crystal drive to invert polarity of liquid crystal in a cycle of arbitrary line
period
¾ Internal oscillator, Hardware and software Reset
¾ TFT storage capacitor: Cst only

New Vision Microelectronics Inc. Page 5

Block Diagram

18 Index
register
IOVCC (IR)
MPU I/F
IM[3:0]
-18 bit 7
CS -16 bit
-9 bit Address
DC 18 Control LCD
-8 bit Counter
Register Source
WR (AC) S1~720
(CR) Driver
RD
SDI SPI I/F
18
SDO RGB I/F Graphics
18
18 bit Operation
DB0-17
16 bit
VSYNC
6 bit
HSYNC 18
Read Write Grayscale VREG1OUT
Latch Latch Reference
DOTCLK
VSYNC I/F 18
Voltage VGS
18
ENABLE
Graphics RAM
(GRAM)

CABC
VDD
Block
VCI Regulator
GND Brightness
Control
BC_CTRL

LCD
VCI Gate G1~G320
VCI1 Timing
RC-OSC Driver
Controller
GND

VCOM
Charge-pump Power Circuit
Generator VCOM
C11P

VCL
C22P
C12N

C21N

DDVDH
C22N

C13N
C11N

VGL
VGH
C13P
C21P
C12P

New Vision Microelectronics Inc. Page 6

3. Pin Function
Power supply
Signal Connect to Function

Low voltage power supply for interface logic

IOVCC I/O voltage
circuits(1.65~3.3V)
LED driver Power supply for LED driver interface.(1.65~3.3V)
VDD3-P
Power If LED driver is not used, fix this pin at IOVCC.
Analog Power supply to liquid crystal power supply analog circuit.
VCI
Power Connect to an external power supply of 2.5V ~ 3.3V.
Regulated Digital circuit power pad.
VDD Voltage Connect these pins with the 1uF capacitor.
GNDR I/O Ground System ground level for I/O circuits.

GND Logic Ground System ground level for logic blocks

Analog System ground level for analog circuit blocks
GNDA
Ground Connect to GND on the FPC to prevent noise
Regulated Digital circuit power pad.
VDDR
Voltage Connect these pins with VDD.

Test pins
Signal I/O Function
TREGB I Dummy pin. Connect this pad to GND.
DUMMYR1
I Dummy pin. Leave these pads open.
DUMMYR2
TMODE[3:0] - Dummy pin. Leave these pads open.
TMUX[2:0] - Dummy pin. Leave these pads open.
EXCLK - Dummy pin. Leave these pads open.
DB[23:18] - Dummy pin. Leave these pads open.
VCIR_EXIN - Dummy pin. Leave these pads open.
DUMMY - Dummy pin. Leave these pads open.
VCI1 Dummy pin. Leave these pads open.

New Vision Microelectronics Inc. Page 7

Interface logic pins

Signal I/O Function

Select the MPU system interface mode. EXTC is connected to IOVCC.
DB pins
IM3 IM2 IM1 IM0 MPU interface Mode
Register Gram
i80-system
0 0 0 0 DB[7:0] DB[7:0]
8 bit interface I
i80-system
0 0 0 1 DB[7:0] DB[15:0]
16-bit interface I
i80-system
0 0 1 0 DB[7:0] DB[8:0]
9-bit interface I
i80-system
0 0 1 1 DB[7:0] DB[17:0]
18-bit interface I
3-wire 9-bit data
0 1 0 1 SDA: in/out
Serial interface I
IM[3:0] I 4-wire 8-bit data
0 1 1 0 SDA: in/out
Serial interface I
i80-system DB[8:1],
1 0 0 0 DB[8:1]
16-bit interface II DB[17:10]
i80-system
1 0 0 1 DB[17:10] DB[17:10]
8 bit interface II
i80-system
1 0 1 0 DB[8:1] DB[17:0]
18-bit interface II
i80-system
1 0 1 1 DB[17:10] DB[17:9]
9-bit interface II
3-wire 9-bit data SDI: in
1 1 0 1
Serial interface II SDO: out
4-wire 8-bit data SDI: in
1 1 1 0
Serial interface II SDO: out
If pad not used, please fix this pin to IOVCC or VSS level.
This signal will reset the device and must be applied to properly initialize the chip.
RESET I
Signal is active low.
Interface select pin. If EXTC is connected to VSS, MPU system interface mode is
defined as follow.
EXTC I Select the MPU system interface mode. EXTC is connected to VSS.
DB pins
IM3 IM2 IM1 IM0 MPU interface Mode
Register Gram

New Vision Microelectronics Inc. Page 8

i80-system
0 0 0 0 DB[7:0] DB[15:0]
16-bit interface I
i80-system
0 0 0 1 DB[7:0] DB[7:0]
8 bit interface I
i80-system DB[8:1],
0 0 1 0 DB[8:1]
16-bit interface II DB[17:10]
i80-system
0 0 1 1 DB[17:10] DB[17:10]
8 bit interface II
3-wire 9-bit data
0 1 0 1 SDA: in/out
Serial interface
4-wire 8-bit data
0 1 1 0 SDA: in/out
Serial interface
i80-system
1 0 0 0 DB[7:0] DB[17:0]
18-bit interface I
i80-system
1 0 0 1 DB[7:0] DB[8:0]
9-bit interface I
i80-system
1 0 1 0 DB[8:1] DB[17:0]
18-bit interface II
i80-system
1 0 1 1 DB[17:10] DB[17:9]
9-bit interface II
3-wire 9-bit data SDI: in
1 1 0 1
Serial interface II SDO: out
4-wire 8-bit data SDI: in
1 1 1 0
Serial interface II SDO: out
If not used, please fix this pin to IOVCC or VSS level.
A chip select signal.
Low: the NV3029C is selected and accessible.
CS I
High: the NV3029C is not selected and not accessible.
Fix to the GND level when not in use.
This pin is used to select “Data or Command” in the parallel interface
or 4-wire 8-bit serial data interface.
When DCX = ’1’, data is selected.
DC I When DCX = ’0’, command is selected.
This pin is used serial interface clock in 3-wire 9-bit / 4-wire 8-bit
serial data interface.
If not used, this pin should be connected to VDDI or VSS.
A write strobe signal and enables an operation to write data when the signal is low.
WR I Fix to either IOVCC or GND level when not in use.
SPI Mode: Synchronizing clock signal in SPI mode.

New Vision Microelectronics Inc. Page 9

A read strobe signal and enables an operation to read out data when the signal is
RD I
low.Fix to either IOVCC or GND level when not in use.
SPI interface input pin.The data is latched on the rising edge of the SCL signal.
SDA I
If not used, fix this pin at IOVCC or GND.
SPI interface output pin.
SDO O The data is outputted on the falling edge of the SCL signal.
Let SDO as floating when not used. If not used, open this pin
Tearing effect output pin to synchronize MPU to frame writing, activated by S/W
TE O command. When this pin is not activated, this pin is low.
If not used, open this pin
Pixel clock signal in RGB I/F mode.
DOTCLK I
If not used, fix this pin at IOVCC or GND.
Vertical sync. Signal in RGB I/F mode.
VSYNC I
If not used, fix this pin at IOVCC or GND.
Horizontal sync. Signal in RGB I/F mode.
HSYNC I
If not used, fix this pin at IOVCC or GND.
ENABLE I Data enable signal in RGB I/F mode. If not used, fix this pin at IOVCC or GND.
18-bit parallel bi-directional data bus for MPU system interface and RGB interface
DB0-
I/0 mode.
DB17
If not used, fix this pin at IOVCC or GND

Driver input/output pins

Signal I/O Function

S1 to S720 O Source driver output pads.

G1 to G320 O Gate driver output pads.

Output voltage of 1st step up circuit. Input voltage to 2nd step up circuit.
DDVDH O Generated power output PAD for source driver block. Connect this PAD to the
capacitor for stabilization.

VGH O Power supply for the gate driver.

VGL O Power supply for the gate driver.

Power supply for generating VCOM low level. 3rd step up circuit output voltage.
VCL O
Connect a capacitor for stabilization.
C11P,
C11N
- Connect the charge-pumping capacitor for generating DDVDH level.
C12P,
C12N
C21P,
- Connect the charge-pumping capacitor for generating VGH,VGL level.
C21N

New Vision Microelectronics Inc. Page 10

C22P,
C22N
C31P,
- Connect the charge-pumping capacitor for generating VCL level.
C31N
Output voltage generated from the reference voltage.
The voltage level is set with the VRH bits.
VREG1 VREG1OUT is (1) a source driver grayscale reference voltage,
OUT (2) high reference voltage,
(3) Vcom amplitude reference voltage.
VREG1OUT = 3.0 ~ (DDVDH – 0.5)V.
Low reference voltage for grayscale voltage generator.
VGS I
Connect an external resistor or to system ground.
Power supply PAD for the TFT-display counter electrode.
VCOM O Charge recycling method is used with VCI and IOGND voltage.
Connect this PAD to the TFT-display counter electrode.
VCOMH O Dummy pin. Leave these pads open.

VCOML O Dummy pin. Leave these pads open.

Output pin for PWM(Pulse width modulation)signal of LED driving.
BC O
If not used, open this pad.
Output pin for enabling LED driving.
BC_CTRL O
If not used, open this pad.

New Vision Microelectronics Inc. Page 11

4. Pad Arrangement

New Vision Microelectronics Inc. Page 12

5. Chip Size

size
Item PAD Pad. Unit
X Y
Chip size - 15770 650
Input Side 85/72.5/60
PAD Pitch
Output Side 14
Input Side 40 50.5
Bumped PAD Top Size
Output Side 14 100 um
Height In Wafer 12
Bumped PAD Height Tolerance In Chip Under 2
Dimple Height Under 2
Chip Thickness - 280
note:
1. scribe lane 60um included in this die size
2. wafer thickness can be varied with the customer’s needs.

Alignment mark

Left COG Align key Right COG Align key

10 30 30 30 10 30 30 30 30
30
20 20 10
10
20 20
30 30

110
30 110 30

30 30

10 10

110
110
unit:um

New Vision Microelectronics Inc. Page 13

6. Pad Coordinates

NO. Pad_name X Y NO. Pad_name X Y NO. Pad_name X Y

1 DUMMY1 -7292.5 -248 51 C12N -4292.5 -248 101 GNDA -1292.5 -248
2 DUMMY2 -7232.5 -248 52 C12N -4232.5 -248 102 GNDA -1232.5 -248
3 VCOM -7172.5 -248 53 C11P -4172.5 -248 103 GNDA -1172.5 -248
4 VCOM -7112.5 -248 54 C11P -4112.5 -248 104 GNDA -1112.5 -248
5 VCOM -7052.5 -248 55 C11P -4052.5 -248 105 GNDA -1052.5 -248
6 VCOM -6992.5 -248 56 C11P -3992.5 -248 106 TREGB -992.5 -248
7 VCOM -6932.5 -248 57 C11P -3932.5 -248 107 VGS -932.5 -248
8 VCOM -6872.5 -248 58 C11P -3872.5 -248 108 VGS -872.5 -248
9 VCOM -6812.5 -248 59 C11P -3812.5 -248 109 EXTC -812.5 -248
10 VCOM -6752.5 -248 60 C11N -3752.5 -248 110 IM3 -752.5 -248
11 DUMMY3 -6692.5 -248 61 C11N -3692.5 -248 111 IM2 -692.5 -248
12 C22P -6632.5 -248 62 C11N -3632.5 -248 112 IM1 -632.5 -248
13 C22P -6572.5 -248 63 C11N -3572.5 -248 113 IM0 -572.5 -248
14 C22N -6512.5 -248 64 C11N -3512.5 -248 114 RESET -512.5 -248
15 C22N -6452.5 -248 65 C11N -3452.5 -248 115 CS -452.5 -248
16 C21P -6392.5 -248 66 C11N -3392.5 -248 116 DC -392.5 -248
17 C21P -6332.5 -248 67 VCI1 -3332.5 -248 117 WR -332.5 -248
18 C21N -6272.5 -248 68 VCI1 -3272.5 -248 118 RD -272.5 -248
19 C21N -6212.5 -248 69 VCI1 -3212.5 -248 119 TMODE2 -212.5 -248
20 VGH -6152.5 -248 70 VCI1 -3152.5 -248 120 VSYNC -152.5 -248
21 VGH -6092.5 -248 71 VCI1 -3092.5 -248 121 HSYNC -92.5 -248
22 VGH -6032.5 -248 72 VCI1 -3032.5 -248 122 ENABLE -32.5 -248
23 VGH -5972.5 -248 73 VCI1 -2972.5 -248 123 DOTCLOCK 27.5 -248
24 VGH -5912.5 -248 74 VCI -2912.5 -248 124 TMODE1 87.5 -248
25 DUMMY4 -5852.5 -248 75 VCI -2852.5 -248 125 SDA 160 -248
26 VGL -5792.5 -248 76 VCI -2792.5 -248 126 DB0 245 -248
27 VGL -5732.5 -248 77 VCI -2732.5 -248 127 DB1 330 -248
28 VGL -5672.5 -248 78 VCI -2672.5 -248 128 DB2 415 -248
29 VGL -5612.5 -248 79 VCI -2612.5 -248 129 DB3 500 -248
30 VGL -5552.5 -248 80 VCI -2552.5 -248 130 TMODE0 572.5 -248
31 VGL -5492.5 -248 81 VCI -2492.5 -248 131 DB4 645 -248
32 DDVDH -5432.5 -248 82 GNDR -2432.5 -248 132 DB5 730 -248
33 DDVDH -5372.5 -248 83 GNDR -2372.5 -248 133 DB6 815 -248
34 DDVDH -5312.5 -248 84 GNDR -2312.5 -248 134 DB7 900 -248
35 DDVDH -5252.5 -248 85 GNDR -2252.5 -248 135 TMUX2 972.5 -248
36 DDVDH -5192.5 -248 86 GNDR -2192.5 -248 136 DB8 1045 -248
37 DDVDH -5132.5 -248 87 GNDR -2132.5 -248 137 DB9 1130 -248
38 DDVDH -5072.5 -248 88 GNDR -2072.5 -248 138 DB10 1215 -248
39 C12P -5012.5 -248 89 GNDR -2012.5 -248 139 DB11 1300 -248
40 C12P -4952.5 -248 90 GND -1952.5 -248 140 TMUX1 1372.5 -248
41 C12P -4892.5 -248 91 GND -1892.5 -248 141 DB12 1445 -248
42 C12P -4832.5 -248 92 GND -1832.5 -248 142 DB13 1530 -248
43 C12P -4772.5 -248 93 GND -1772.5 -248 143 DB14 1615 -248
44 C12P -4712.5 -248 94 GND -1712.5 -248 144 DB15 1700 -248
45 C12P -4652.5 -248 95 GND -1652.5 -248 145 TMUX0 1772.5 -248
46 C12N -4592.5 -248 96 GND -1592.5 -248 146 DB16 1845 -248
47 C12N -4532.5 -248 97 GND -1532.5 -248 147 DB17 1930 -248
48 C12N -4472.5 -248 98 GNDA -1472.5 -248 148 EXCLK 2002.5 -248
49 C12N -4412.5 -248 99 GNDA -1412.5 -248 149 TE 2075 -248
50 C12N -4352.5 -248 100 GNDA -1352.5 -248 150 SDO 2160 -248

New Vision Microelectronics Inc. Page 14

NO. Pad_name X Y NO. Pad_name X Y NO. Pad_name X Y

151 BC 2245 -248 201 C31P 5432.5 -248 251 G32 7147 224
152 BC_CTRL 2330 -248 202 C31P 5492.5 -248 252 G34 7133 93
153 VDD3_P 2402.5 -248 203 C31P 5552.5 -248 253 G36 7119 224
154 VDD3_P 2462.5 -248 204 C31P 5612.5 -248 254 G38 7105 93
155 DB18 2535 -248 205 C31P 5672.5 -248 255 G40 7091 224
156 DB19 2620 -248 206 C31N 5732.5 -248 256 G42 7077 93
157 DB20 2705 -248 207 C31N 5792.5 -248 257 G44 7063 224
158 DB21 2790 -248 208 C31N 5852.5 -248 258 G46 7049 93
159 DB22 2875 -248 209 C31N 5912.5 -248 259 G48 7035 224
160 DB23 2960 -248 210 C31N 5972.5 -248 260 G50 7021 93
161 TMODE3 3032.5 -248 211 C31N 6032.5 -248 261 G52 7007 224
162 IOVCC 3092.5 -248 212 C31N 6092.5 -248 262 G54 6993 93
163 IOVCC 3152.5 -248 213 C31N 6152.5 -248 263 G56 6979 224
164 IOVCC 3212.5 -248 214 DUMMYR 6212.5 -248 264 G58 6965 93
165 IOVCC 3272.5 -248 215 DUMMYR 6272.5 -248 265 G60 6951 224
166 IOVCC 3332.5 -248 216 DUMMY16 6332.5 -248 266 G62 6937 93
167 IOVCC 3392.5 -248 217 DUMMY17 6392.5 -248 267 G64 6923 224
168 IOVCC 3452.5 -248 218 DUMMY18 6452.5 -248 268 G66 6909 93
169 VDD 3512.5 -248 219 DUMMY19 6512.5 -248 269 G68 6895 224
170 VDD 3572.5 -248 220 DUMMY20 6572.5 -248 270 G70 6881 93
171 VDD 3632.5 -248 221 DUMMY21 6632.5 -248 271 G72 6867 224
172 VDD 3692.5 -248 222 DUMMY22 6692.5 -248 272 G74 6853 93
173 VDD 3752.5 -248 223 VCOM 6752.5 -248 273 G76 6839 224
174 VDD 3812.5 -248 224 VCOM 6812.5 -248 274 G78 6825 93
175 VDD 3872.5 -248 225 VCOM 6872.5 -248 275 G80 6811 224
176 VDD 3932.5 -248 226 VCOM 6932.5 -248 276 G82 6797 93
177 VDDR 3992.5 -248 227 VCOM 6992.5 -248 277 G84 6783 224
178 VDDR 4052.5 -248 228 VCOM 7052.5 -248 278 G86 6769 93
179 VDDR 4112.5 -248 229 VCOM 7112.5 -248 279 G88 6755 224
180 VDDR 4172.5 -248 230 VCOM 7172.5 -248 280 G90 6741 93
181 VDDR 4232.5 -248 231 VCOMH 7232.5 -248 281 G92 6727 224
182 VDDR 4292.5 -248 232 VCOML 7292.5 -248 282 G94 6713 93
183 DUMMY14 4352.5 -248 233 DUMMY25 7399 224 283 G96 6699 224
184 VREG1OU 4412.5 -248 234 DUMMY26 7385 93 284 G98 6685 93
185 VREG1OU 4472.5 -248 235 DUMMY27 7371 224 285 G100 6671 224
186 VREG1OU 4532.5 -248 236 G2 7357 93 286 G102 6657 93
187 VREG1OU 4592.5 -248 237 G4 7343 224 287 G104 6643 224
188 VCIR_EXI 4652.5 -248 238 G6 7329 93 288 G106 6629 93
189 DUMMY15 4712.5 -248 239 G8 7315 224 289 G108 6615 224
190 VCL 4772.5 -248 240 G10 7301 93 290 G110 6601 93
191 VCL 4832.5 -248 241 G12 7287 224 291 G112 6587 224
192 VCL 4892.5 -248 242 G14 7273 93 292 G114 6573 93
193 VCL 4952.5 -248 243 G16 7259 224 293 G116 6559 224
194 VCL 5012.5 -248 244 G18 7245 93 294 G118 6545 93
195 VCL 5072.5 -248 245 G20 7231 224 295 G120 6531 224
196 VCL 5132.5 -248 246 G22 7217 93 296 G122 6517 93
197 VCL 5192.5 -248 247 G24 7203 224 297 G124 6503 224
198 C31P 5252.5 -248 248 G26 7189 93 298 G126 6489 93
199 C31P 5312.5 -248 249 G28 7175 224 299 G128 6475 224
200 C31P 5372.5 -248 250 G30 7161 93 300 G130 6461 93

New Vision Microelectronics Inc. Page 15

NO. Pad_name X Y NO Pad_name X Y NO Pad_name X Y

301 G132 6447 224 351 G232 5747 224 401 S715 5005 224
302 G134 6433 93 352 G234 5733 93 402 S714 4991 93
303 G136 6419 224 353 G236 5719 224 403 S713 4977 224
304 G138 6405 93 354 G238 5705 93 404 S712 4963 93
305 G140 6391 224 355 G240 5691 224 405 S711 4949 224
306 G142 6377 93 356 G242 5677 93 406 S710 4935 93
307 G144 6363 224 357 G244 5663 224 407 S709 4921 224
308 G146 6349 93 358 G246 5649 93 408 S708 4907 93
309 G148 6335 224 359 G248 5635 224 409 S707 4893 224
310 G150 6321 93 360 G250 5621 93 410 S706 4879 93
311 G152 6307 224 361 G252 5607 224 411 S705 4865 224
312 G154 6293 93 362 G254 5593 93 412 S704 4851 93
313 G156 6279 224 363 G256 5579 224 413 S703 4837 224
314 G158 6265 93 364 G258 5565 93 414 S702 4823 93
315 G160 6251 224 365 G260 5551 224 415 S701 4809 224
316 G162 6237 93 366 G262 5537 93 416 S700 4795 93
317 G164 6223 224 367 G264 5523 224 417 S699 4781 224
318 G166 6209 93 368 G266 5509 93 418 S698 4767 93
319 G168 6195 224 369 G268 5495 224 419 S697 4753 224
320 G170 6181 93 370 G270 5481 93 420 S696 4739 93
321 G172 6167 224 371 G272 5467 224 421 S695 4725 224
322 G174 6153 93 372 G274 5453 93 422 S694 4711 93
323 G176 6139 224 373 G276 5439 224 423 S693 4697 224
324 G178 6125 93 374 G278 5425 93 424 S692 4683 93
325 G180 6111 224 375 G280 5411 224 425 S691 4669 224
326 G182 6097 93 376 G282 5397 93 426 S690 4655 93
327 G184 6083 224 377 G284 5383 224 427 S689 4641 224
328 G186 6069 93 378 G286 5369 93 428 S688 4627 93
329 G188 6055 224 379 G288 5355 224 429 S687 4613 224
330 G190 6041 93 380 G290 5341 93 430 S686 4599 93
331 G192 6027 224 381 G292 5327 224 431 S685 4585 224
332 G194 6013 93 382 G294 5313 93 432 S684 4571 93
333 G196 5999 224 383 G296 5299 224 433 S683 4557 224
334 G198 5985 93 384 G298 5285 93 434 S682 4543 93
335 G200 5971 224 385 G300 5271 224 435 S681 4529 224
336 G202 5957 93 386 G302 5257 93 436 S680 4515 93
337 G204 5943 224 387 G304 5243 224 437 S679 4501 224
338 G206 5929 93 388 G306 5229 93 438 S678 4487 93
339 G208 5915 224 389 G308 5215 224 439 S677 4473 224
340 G210 5901 93 390 G310 5201 93 440 S676 4459 93
341 G212 5887 224 391 G312 5187 224 441 S675 4445 224
342 G214 5873 93 392 G314 5173 93 442 S674 4431 93
343 G216 5859 224 393 G316 5159 224 443 S673 4417 224
344 G218 5845 93 394 G318 5145 93 444 S672 4403 93
345 G220 5831 224 395 G320 5131 224 445 S671 4389 224
346 G222 5817 93 396 S720 5075 93 446 S670 4375 93
347 G224 5803 224 397 S719 5061 224 447 S669 4361 224
348 G226 5789 93 398 S718 5047 93 448 S668 4347 93
349 G228 5775 224 399 S717 5033 224 449 S667 4333 224
350 G230 5761 93 400 S716 5019 93 450 S666 4319 93

New Vision Microelectronics Inc. Page 16

NO Pad_name X Y NO Pad_name X Y NO Pad_name X Y

451 S665 4305 224 501 S615 3605 224 551 S565 2905 224
452 S664 4291 93 502 S614 3591 93 552 S564 2891 93
453 S663 4277 224 503 S613 3577 224 553 S563 2877 224
454 S662 4263 93 504 S612 3563 93 554 S562 2863 93
455 S661 4249 224 505 S611 3549 224 555 S561 2849 224
456 S660 4235 93 506 S610 3535 93 556 S560 2835 93
457 S659 4221 224 507 S609 3521 224 557 S559 2821 224
458 S658 4207 93 508 S608 3507 93 558 S558 2807 93
459 S657 4193 224 509 S607 3493 224 559 S557 2793 224
460 S656 4179 93 510 S606 3479 93 560 S556 2779 93
461 S655 4165 224 511 S605 3465 224 561 S555 2765 224
462 S654 4151 93 512 S604 3451 93 562 S554 2751 93
463 S653 4137 224 513 S603 3437 224 563 S553 2737 224
464 S652 4123 93 514 S602 3423 93 564 S552 2723 93
465 S651 4109 224 515 S601 3409 224 565 S551 2709 224
466 S650 4095 93 516 S600 3395 93 566 S550 2695 93
467 S649 4081 224 517 S599 3381 224 567 S549 2681 224
468 S648 4067 93 518 S598 3367 93 568 S548 2667 93
469 S647 4053 224 519 S597 3353 224 569 S547 2653 224
470 S646 4039 93 520 S596 3339 93 570 S546 2639 93
471 S645 4025 224 521 S595 3325 224 571 S545 2625 224
472 S644 4011 93 522 S594 3311 93 572 S544 2611 93
473 S643 3997 224 523 S593 3297 224 573 S543 2597 224
474 S642 3983 93 524 S592 3283 93 574 S542 2583 93
475 S641 3969 224 525 S591 3269 224 575 S541 2569 224
476 S640 3955 93 526 S590 3255 93 576 S540 2555 93
477 S639 3941 224 527 S589 3241 224 577 S539 2541 224
478 S638 3927 93 528 S588 3227 93 578 S538 2527 93
479 S637 3913 224 529 S587 3213 224 579 S537 2513 224
480 S636 3899 93 530 S586 3199 93 580 S536 2499 93
481 S635 3885 224 531 S585 3185 224 581 S535 2485 224
482 S634 3871 93 532 S584 3171 93 582 S534 2471 93
483 S633 3857 224 533 S583 3157 224 583 S533 2457 224
484 S632 3843 93 534 S582 3143 93 584 S532 2443 93
485 S631 3829 224 535 S581 3129 224 585 S531 2429 224
486 S630 3815 93 536 S580 3115 93 586 S530 2415 93
487 S629 3801 224 537 S579 3101 224 587 S529 2401 224
488 S628 3787 93 538 S578 3087 93 588 S528 2387 93
489 S627 3773 224 539 S577 3073 224 589 S527 2373 224
490 S626 3759 93 540 S576 3059 93 590 S526 2359 93
491 S625 3745 224 541 S575 3045 224 591 S525 2345 224
492 S624 3731 93 542 S574 3031 93 592 S524 2331 93
493 S623 3717 224 543 S573 3017 224 593 S523 2317 224
494 S622 3703 93 544 S572 3003 93 594 S522 2303 93
495 S621 3689 224 545 S571 2989 224 595 S521 2289 224
496 S620 3675 93 546 S570 2975 93 596 S520 2275 93
497 S619 3661 224 547 S569 2961 224 597 S519 2261 224
498 S618 3647 93 548 S568 2947 93 598 S518 2247 93
499 S617 3633 224 549 S567 2933 224 599 S517 2233 224
500 S616 3619 93 550 S566 2919 93 600 S516 2219 93

New Vision Microelectronics Inc. Page 17

NO Pad_name X Y NO Pad_name X Y NO Pad_name X Y

601 S515 2205 224 651 S465 1505 224 701 S415 805 224
602 S514 2191 93 652 S464 1491 93 702 S414 791 93
603 S513 2177 224 653 S463 1477 224 703 S413 777 224
604 S512 2163 93 654 S462 1463 93 704 S412 763 93
605 S511 2149 224 655 S461 1449 224 705 S411 749 224
606 S510 2135 93 656 S460 1435 93 706 S410 735 93
607 S509 2121 224 657 S459 1421 224 707 S409 721 224
608 S508 2107 93 658 S458 1407 93 708 S408 707 93
609 S507 2093 224 659 S457 1393 224 709 S407 693 224
610 S506 2079 93 660 S456 1379 93 710 S406 679 93
611 S505 2065 224 661 S455 1365 224 711 S405 665 224
612 S504 2051 93 662 S454 1351 93 712 S404 651 93
613 S503 2037 224 663 S453 1337 224 713 S403 637 224
614 S502 2023 93 664 S452 1323 93 714 S402 623 93
615 S501 2009 224 665 S451 1309 224 715 S401 609 224
616 S500 1995 93 666 S450 1295 93 716 S400 595 93
617 S499 1981 224 667 S449 1281 224 717 S399 581 224
618 S498 1967 93 668 S448 1267 93 718 S398 567 93
619 S497 1953 224 669 S447 1253 224 719 S397 553 224
620 S496 1939 93 670 S446 1239 93 720 S396 539 93
621 S495 1925 224 671 S445 1225 224 721 S395 525 224
622 S494 1911 93 672 S444 1211 93 722 S394 511 93
623 S493 1897 224 673 S443 1197 224 723 S393 497 224
624 S492 1883 93 674 S442 1183 93 724 S392 483 93
625 S491 1869 224 675 S441 1169 224 725 S391 469 224
626 S490 1855 93 676 S440 1155 93 726 S390 455 93
627 S489 1841 224 677 S439 1141 224 727 S389 441 224
628 S488 1827 93 678 S438 1127 93 728 S388 427 93
629 S487 1813 224 679 S437 1113 224 729 S387 413 224
630 S486 1799 93 680 S436 1099 93 730 S386 399 93
631 S485 1785 224 681 S435 1085 224 731 S385 385 224
632 S484 1771 93 682 S434 1071 93 732 S384 371 93
633 S483 1757 224 683 S433 1057 224 733 S383 357 224
634 S482 1743 93 684 S432 1043 93 734 S382 343 93
635 S481 1729 224 685 S431 1029 224 735 S381 329 224
636 S480 1715 93 686 S430 1015 93 736 S380 315 93
637 S479 1701 224 687 S429 1001 224 737 S379 301 224
638 S478 1687 93 688 S428 987 93 738 S378 287 93
639 S477 1673 224 689 S427 973 224 739 S377 273 224
640 S476 1659 93 690 S426 959 93 740 S376 259 93
641 S475 1645 224 691 S425 945 224 741 S375 245 224
642 S474 1631 93 692 S424 931 93 742 S374 231 93
643 S473 1617 224 693 S423 917 224 743 S373 217 224
644 S472 1603 93 694 S422 903 93 744 S372 203 93
645 S471 1589 224 695 S421 889 224 745 S371 189 224
646 S470 1575 93 696 S420 875 93 746 S370 175 93
647 S469 1561 224 697 S419 861 224 747 S369 161 224
648 S468 1547 93 698 S418 847 93 748 S368 147 93
649 S467 1533 224 699 S417 833 224 749 S367 133 224
650 S466 1519 93 700 S416 819 93 750 S366 119 93

New Vision Microelectronics Inc. Page 18

NO. Pad_name X Y NO. Pad_name X Y NO. Pad_name X Y

751 S365 105 224 801 S315 -679 224 851 S265 -1379 224
752 S364 91 93 802 S314 -693 93 852 S264 -1393 93
753 S363 77 224 803 S313 -707 224 853 S263 -1407 224
754 S362 63 93 804 S312 -721 93 854 S262 -1421 93
755 S361 49 224 805 S311 -735 224 855 S261 -1435 224
756 S360 -49 93 806 S310 -749 93 856 S260 -1449 93
757 S359 -63 224 807 S309 -763 224 857 S259 -1463 224
758 S358 -77 93 808 S308 -777 93 858 S258 -1477 93
759 S357 -91 224 809 S307 -791 224 859 S257 -1491 224
760 S356 -105 93 810 S306 -805 93 860 S256 -1505 93
761 S355 -119 224 811 S305 -819 224 861 S255 -1519 224
762 S354 -133 93 812 S304 -833 93 862 S254 -1533 93
763 S353 -147 224 813 S303 -847 224 863 S253 -1547 224
764 S352 -161 93 814 S302 -861 93 864 S252 -1561 93
765 S351 -175 224 815 S301 -875 224 865 S251 -1575 224
766 S350 -189 93 816 S300 -889 93 866 S250 -1589 93
767 S349 -203 224 817 S299 -903 224 867 S249 -1603 224
768 S348 -217 93 818 S298 -917 93 868 S248 -1617 93
769 S347 -231 224 819 S297 -931 224 869 S247 -1631 224
770 S346 -245 93 820 S296 -945 93 870 S246 -1645 93
771 S345 -259 224 821 S295 -959 224 871 S245 -1659 224
772 S344 -273 93 822 S294 -973 93 872 S244 -1673 93
773 S343 -287 224 823 S293 -987 224 873 S243 -1687 224
774 S342 -301 93 824 S292 -1001 93 874 S242 -1701 93
775 S341 -315 224 825 S291 -1015 224 875 S241 -1715 224
776 S340 -329 93 826 S290 -1029 93 876 S240 -1729 93
777 S339 -343 224 827 S289 -1043 224 877 S239 -1743 224
778 S338 -357 93 828 S288 -1057 93 878 S238 -1757 93
779 S337 -371 224 829 S287 -1071 224 879 S237 -1771 224
780 S336 -385 93 830 S286 -1085 93 880 S236 -1785 93
781 S335 -399 224 831 S285 -1099 224 881 S235 -1799 224
782 S334 -413 93 832 S284 -1113 93 882 S234 -1813 93
783 S333 -427 224 833 S283 -1127 224 883 S233 -1827 224
784 S332 -441 93 834 S282 -1141 93 884 S232 -1841 93
785 S331 -455 224 835 S281 -1155 224 885 S231 -1855 224
786 S330 -469 93 836 S280 -1169 93 886 S230 -1869 93
787 S329 -483 224 837 S279 -1183 224 887 S229 -1883 224
788 S328 -497 93 838 S278 -1197 93 888 S228 -1897 93
789 S327 -511 224 839 S277 -1211 224 889 S227 -1911 224
790 S326 -525 93 840 S276 -1225 93 890 S226 -1925 93
791 S325 -539 224 841 S275 -1239 224 891 S225 -1939 224
792 S324 -553 93 842 S274 -1253 93 892 S224 -1953 93
793 S323 -567 224 843 S273 -1267 224 893 S223 -1967 224
794 S322 -581 93 844 S272 -1281 93 894 S222 -1981 93
795 S321 -595 224 845 S271 -1295 224 895 S221 -1995 224
796 S320 -609 93 846 S270 -1309 93 896 S220 -2009 93
797 S319 -623 224 847 S269 -1323 224 897 S219 -2023 224
798 S318 -637 93 848 S268 -1337 93 898 S218 -2037 93
799 S317 -651 224 849 S267 -1351 224 899 S217 -2051 224
800 S316 -665 93 850 S266 -1365 93 900 S216 -2065 93

New Vision Microelectronics Inc. Page 19

NO. Pad_name X Y NO. Pad_name X Y NO. Pad_name X Y

901 S215 -2079 224 951 S165 -2779 224 1001 S115 -3479 224
902 S214 -2093 93 952 S164 -2793 93 1002 S114 -3493 93
903 S213 -2107 224 953 S163 -2807 224 1003 S113 -3507 224
904 S212 -2121 93 954 S162 -2821 93 1004 S112 -3521 93
905 S211 -2135 224 955 S161 -2835 224 1005 S111 -3535 224
906 S210 -2149 93 956 S160 -2849 93 1006 S110 -3549 93
907 S209 -2163 224 957 S159 -2863 224 1007 S109 -3563 224
908 S208 -2177 93 958 S158 -2877 93 1008 S108 -3577 93
909 S207 -2191 224 959 S157 -2891 224 1009 S107 -3591 224
910 S206 -2205 93 960 S156 -2905 93 1010 S106 -3605 93
911 S205 -2219 224 961 S155 -2919 224 1011 S105 -3619 224
912 S204 -2233 93 962 S154 -2933 93 1012 S104 -3633 93
913 S203 -2247 224 963 S153 -2947 224 1013 S103 -3647 224
914 S202 -2261 93 964 S152 -2961 93 1014 S102 -3661 93
915 S201 -2275 224 965 S151 -2975 224 1015 S101 -3675 224
916 S200 -2289 93 966 S150 -2989 93 1016 S100 -3689 93
917 S199 -2303 224 967 S149 -3003 224 1017 S99 -3703 224
918 S198 -2317 93 968 S148 -3017 93 1018 S98 -3717 93
919 S197 -2331 224 969 S147 -3031 224 1019 S97 -3731 224
920 S196 -2345 93 970 S146 -3045 93 1020 S96 -3745 93
921 S195 -2359 224 971 S145 -3059 224 1021 S95 -3759 224
922 S194 -2373 93 972 S144 -3073 93 1022 S94 -3773 93
923 S193 -2387 224 973 S143 -3087 224 1023 S93 -3787 224
924 S192 -2401 93 974 S142 -3101 93 1024 S92 -3801 93
925 S191 -2415 224 975 S141 -3115 224 1025 S91 -3815 224
926 S190 -2429 93 976 S140 -3129 93 1026 S90 -3829 93
927 S189 -2443 224 977 S139 -3143 224 1027 S89 -3843 224
928 S188 -2457 93 978 S138 -3157 93 1028 S88 -3857 93
929 S187 -2471 224 979 S137 -3171 224 1029 S87 -3871 224
930 S186 -2485 93 980 S136 -3185 93 1030 S86 -3885 93
931 S185 -2499 224 981 S135 -3199 224 1031 S85 -3899 224
932 S184 -2513 93 982 S134 -3213 93 1032 S84 -3913 93
933 S183 -2527 224 983 S133 -3227 224 1033 S83 -3927 224
934 S182 -2541 93 984 S132 -3241 93 1034 S82 -3941 93
935 S181 -2555 224 985 S131 -3255 224 1035 S81 -3955 224
936 S180 -2569 93 986 S130 -3269 93 1036 S80 -3969 93
937 S179 -2583 224 987 S129 -3283 224 1037 S79 -3983 224
938 S178 -2597 93 988 S128 -3297 93 1038 S78 -3997 93
939 S177 -2611 224 989 S127 -3311 224 1039 S77 -4011 224
940 S176 -2625 93 990 S126 -3325 93 1040 S76 -4025 93
941 S175 -2639 224 991 S125 -3339 224 1041 S75 -4039 224
942 S174 -2653 93 992 S124 -3353 93 1042 S74 -4053 93
943 S173 -2667 224 993 S123 -3367 224 1043 S73 -4067 224
944 S172 -2681 93 994 S122 -3381 93 1044 S72 -4081 93
945 S171 -2695 224 995 S121 -3395 224 1045 S71 -4095 224
946 S170 -2709 93 996 S120 -3409 93 1046 S70 -4109 93
947 S169 -2723 224 997 S119 -3423 224 1047 S69 -4123 224
948 S168 -2737 93 998 S118 -3437 93 1048 S68 -4137 93
949 S167 -2751 224 999 S117 -3451 224 1049 S67 -4151 224
950 S166 -2765 93 1000 S116 -3465 93 1050 S66 -4165 93

New Vision Microelectronics Inc. Page 20

NO. Pad_name X Y NO. Pad_name X Y NO. Pad_name X Y

1051 S65 -4179 224 1101 S15 -4879 224 1151 G249 -5621 224
1052 S64 -4193 93 1102 S14 -4893 93 1152 G247 -5635 93
1053 S63 -4207 224 1103 S13 -4907 224 1153 G245 -5649 224
1054 S62 -4221 93 1104 S12 -4921 93 1154 G243 -5663 93
1055 S61 -4235 224 1105 S11 -4935 224 1155 G241 -5677 224
1056 S60 -4249 93 1106 S10 -4949 93 1156 G239 -5691 93
1057 S59 -4263 224 1107 S9 -4963 224 1157 G237 -5705 224
1058 S58 -4277 93 1108 S8 -4977 93 1158 G235 -5719 93
1059 S57 -4291 224 1109 S7 -4991 224 1159 G233 -5733 224
1060 S56 -4305 93 1110 S6 -5005 93 1160 G231 -5747 93
1061 S55 -4319 224 1111 S5 -5019 224 1161 G229 -5761 224
1062 S54 -4333 93 1112 S4 -5033 93 1162 G227 -5775 93
1063 S53 -4347 224 1113 S3 -5047 224 1163 G225 -5789 224
1064 S52 -4361 93 1114 S2 -5061 93 1164 G223 -5803 93
1065 S51 -4375 224 1115 S1 -5075 224 1165 G221 -5817 224
1066 S50 -4389 93 1116 G319 -5131 93 1166 G219 -5831 93
1067 S49 -4403 224 1117 G317 -5145 224 1167 G217 -5845 224
1068 S48 -4417 93 1118 G315 -5159 93 1168 G215 -5859 93
1069 S47 -4431 224 1119 G313 -5173 224 1169 G213 -5873 224
1070 S46 -4445 93 1120 G311 -5187 93 1170 G211 -5887 93
1071 S45 -4459 224 1121 G309 -5201 224 1171 G209 -5901 224
1072 S44 -4473 93 1122 G307 -5215 93 1172 G207 -5915 93
1073 S43 -4487 224 1123 G305 -5229 224 1173 G205 -5929 224
1074 S42 -4501 93 1124 G303 -5243 93 1174 G203 -5943 93
1075 S41 -4515 224 1125 G301 -5257 224 1175 G201 -5957 224
1076 S40 -4529 93 1126 G299 -5271 93 1176 G199 -5971 93
1077 S39 -4543 224 1127 G297 -5285 224 1177 G197 -5985 224
1078 S38 -4557 93 1128 G295 -5299 93 1178 G195 -5999 93
1079 S37 -4571 224 1129 G293 -5313 224 1179 G193 -6013 224
1080 S36 -4585 93 1130 G291 -5327 93 1180 G191 -6027 93
1081 S35 -4599 224 1131 G289 -5341 224 1181 G189 -6041 224
1082 S34 -4613 93 1132 G287 -5355 93 1182 G187 -6055 93
1083 S33 -4627 224 1133 G285 -5369 224 1183 G185 -6069 224
1084 S32 -4641 93 1134 G283 -5383 93 1184 G183 -6083 93
1085 S31 -4655 224 1135 G281 -5397 224 1185 G181 -6097 224
1086 S30 -4669 93 1136 G279 -5411 93 1186 G179 -6111 93
1087 S29 -4683 224 1137 G277 -5425 224 1187 G177 -6125 224
1088 S28 -4697 93 1138 G275 -5439 93 1188 G175 -6139 93
1089 S27 -4711 224 1139 G273 -5453 224 1189 G173 -6153 224
1090 S26 -4725 93 1140 G271 -5467 93 1190 G171 -6167 93
1091 S25 -4739 224 1141 G269 -5481 224 1191 G169 -6181 224
1092 S24 -4753 93 1142 G267 -5495 93 1192 G167 -6195 93
1093 S23 -4767 224 1143 G265 -5509 224 1193 G165 -6209 224
1094 S22 -4781 93 1144 G263 -5523 93 1194 G163 -6223 93
1095 S21 -4795 224 1145 G261 -5537 224 1195 G161 -6237 224
1096 S20 -4809 93 1146 G259 -5551 93 1196 G159 -6251 93
1097 S19 -4823 224 1147 G257 -5565 224 1197 G157 -6265 224
1098 S18 -4837 93 1148 G255 -5579 93 1198 G155 -6279 93
1099 S17 -4851 224 1149 G253 -5593 224 1199 G153 -6293 224
1100 S16 -4865 93 1150 G251 -5607 93 1200 G151 -6307 93

New Vision Microelectronics Inc. Page 21

NO Pad_name X Y NO Pad_name X Y
1201 G149 -6321 224 1251 G49 -7021 224
1202 G147 -6335 93 1252 G47 -7035 93
1203 G145 -6349 224 1253 G45 -7049 224
1204 G143 -6363 93 1254 G43 -7063 93
1205 G141 -6377 224 1255 G41 -7077 224
1206 G139 -6391 93 1256 G39 -7091 93
1207 G137 -6405 224 1257 G37 -7105 224
1208 G135 -6419 93 1258 G35 -7119 93
1209 G133 -6433 224 1259 G33 -7133 224
1210 G131 -6447 93 1260 G31 -7147 93
1211 G129 -6461 224 1261 G29 -7161 224
1212 G127 -6475 93 1262 G27 -7175 93
1213 G125 -6489 224 1263 G25 -7189 224
1214 G123 -6503 93 1264 G23 -7203 93
1215 G121 -6517 224 1265 G21 -7217 224
1216 G119 -6531 93 1266 G19 -7231 93
1217 G117 -6545 224 1267 G17 -7245 224
1218 G115 -6559 93 1268 G15 -7259 93
1219 G113 -6573 224 1269 G13 -7273 224
1220 G111 -6587 93 1270 G11 -7287 93
1221 G109 -6601 224 1271 G9 -7301 224
1222 G107 -6615 93 1272 G7 -7315 93
1223 G105 -6629 224 1273 G5 -7329 224
1224 G103 -6643 93 1274 G3 -7343 93
1225 G101 -6657 224 1275 G1 -7357 224
1226 G99 -6671 93 1276 DUMMY28 -7371 93
1227 G97 -6685 224 1277 DUMMY29 -7385 224
1228 G95 -6699 93 1278 DUMMY30 -7399 93
1229 G93 -6713 224
1230 G91 -6727 93
1231 G89 -6741 224
1232 G87 -6755 93 Left Mark -7480 225
1233 G85 -6769 224 Right Mark 7480 225
1234 G83 -6783 93
1235 G81 -6797 224
1236 G79 -6811 93
1237 G77 -6825 224
1238 G75 -6839 93
1239 G73 -6853 224
1240 G71 -6867 93
1241 G69 -6881 224
1242 G67 -6895 93
1243 G65 -6909 224
1244 G63 -6923 93
1245 G61 -6937 224
1246 G59 -6951 93
1247 G57 -6965 224
1248 G55 -6979 93
1249 G53 -6993 224
1250 G51 -7007 93

New Vision Microelectronics Inc. Page 22

7. Bump Size

New Vision Microelectronics Inc. Page 23

8. Command
8.1. Command list

Regulative commands
Command D W/ D17- Hex
D7 D6 D5 D4 D3 D2 D1 D0
function C R 8 default
No Operation 0 W XX 0 0 0 0 0 0 0 0 00h
Software 0 W XX 0 0 0 0 0 0 0 1 01h
0 W XX 0 0 0 0 0 1 0 0 04h
Read Display 1 R XX X X X X X X X X XX
Identification 1 R XX ID1[7] ID1[6] ID1[5] ID1[4] ID1[3] ID1[2] ID1[1] ID1[0] XX

information 1 R XX ID2[7] ID2[6] ID2[5] ID2[4] ID2[3] ID2[2] ID2[1] ID2[0] XX

1 R XX ID3[7] ID3[6] ID3[5] ID3[4] ID3[3] ID3[2] ID3[1] ID3[0] XX
0 W XX 0 0 0 0 1 0 0 1 09h
1 R XX X X X X X X X X XX
Read Display 1 R XX D[31] D[30] D[29] D[28] D[27] D[26] D[25] 0 00h
Status 1 R XX D[22] D[21] D[20] D[19] D[18] D[17] D[16] 61h
1 R XX D[15] D[13] D[10] D[9] D[8] 00h
1 R XX D[7] D[6] D[5] 00h
Read Display 0 W XX 0 0 0 0 1 0 1 0 0ah
Power Mode 1 R XX D[7] D[6] D[5] D[4] D[3] D[2] 08h
Read Display 0 W XX 0 0 0 0 1 0 1 1 0bh
MADCLT 1 R XX D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] 00h
Read Display 0 W XX 0 0 0 0 1 1 0 0 0ch
Pixel Format 1 R XX D[2] D[1] D[0] 06h
Read Display 0 W XX 0 0 0 0 1 1 0 1 0dh
Image Mode 1 R XX D[6] D[4] 00h
Read Display 0 W XX 0 0 0 0 1 1 1 0 0eh
Signal Mode 1 R XX D[7] D[6] 00h
Read Display 0 W XX 0 0 0 0 1 1 1 1 0fh
self-Diagnostic
1 R XX D[7] D[6] 00h
Result
Sleep In 0 W XX 0 0 0 1 0 0 0 0 10h
Sleep Out 0 W XX 0 0 0 1 0 0 0 1 11h
Partial
0 W XX 0 0 0 1 0 0 1 0 12h
Mode On
Normal
0 W XX 0 0 0 1 0 0 1 1 13h
Mode ON
Display
0 W XX 0 0 1 0 0 0 0 0 20h
Inversion Off
Display
0 W XX 0 0 1 0 0 0 0 1 21h
Inversion On
Display Off 0 W XX 0 0 1 0 1 0 0 0 28h
Display On 0 W XX 0 0 1 0 1 0 0 1 29h

New Vision Microelectronics Inc. Page 24

Command D W/ D17- Hex

D7 D6 D5 D4 D3 D2 D1 D0
function C R 8 default

0 W XX 0 0 1 0 1 0 1 0 2ah
1 W XX sc[15] sc[14] sc[13] sc[12] sc[11] sc[10] sc[9] sc[8] 00h
Column
1 W XX sc[7] sc[6] sc[5] sc[4] sc[3] sc[2] sc[1] sc[0] 00h
Address
1 W XX ec[15] ec[14] ec[13] ec[12] ec[11] ec[10] ec[9] ec[8] 00h
1 W XX ec[7] ec[6] ec[5] ec[4] ec[3] ec[2] ec[1] ec[0] efh
0 W XX 0 0 1 0 1 0 1 1 2bh
1 R XX sp[15] sp[14] sp[13] sp[12] sp[10] sp[10] sp[9] sp[8] 00h
Page
1 R XX sp[7] sp[6] sp[5] sp[4] sp[3] sp[2] sp[1] sp[0] 00h
Address
1 R XX ep[15] ep[14] ep[13] ep[12] ep[10] ep[10] ep[9] ep[8] 01h
1 R XX ep[7] ep[6] ep[5] ep[4] ep[3] ep[2] ep[1] ep[0] 3fh
0 W XX 0 0 1 0 1 1 0 0 2ch
Memory
D[17
Write 1 W D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] XX
:8]

Memory
0 W XX 0 0 1 0 1 1 1 0 2eh
Read
0 W XX 0 0 1 1 0 0 0 0 30h
Partial 1 W XX sr[15] sr[14] sr[13] sr[12] sr[11] sr[10] sr[9] sr[8] 00h
1 W XX sr[7] sr[6] sr[5] sr[4] sr[3] sr[2] sr[1] sr[0] 00h
Area
1 W XX er[15] er[14] er[13] er[12] er[11] er[10] er[9] er[8] 01h
1 W XX er[7] er[6] er[5] er[4] er[3] er[2] er[1] er[0] 3fh
0 W XX 0 0 1 1 0 0 1 1 33h
1 W XX tfa[15] tfa[14] tfa[13] tfa[12] tfa[11] tfa[10] tfa[9] tfa[8] 00h
Vertical 1 W XX tfa[7] tfa[6] tfa[5] tfa[4] tfa[3] tfa[2] tfa[1] tfa[0] 00h
1 W XX vsa[15] vsa[14] vsa[1 vsa[12] vsa[1 vsa[10] vsa[9] vsa[8] 01h
Scrolling
1 W XX vsa[7] vsa[6] vsa[5] vsa[4] vsa[3] vsa[2] vsa[1] vsa[0] 40h
1 W XX bfa[15] bfa[14] bfa[13 bfa[12] bfa[11 bfa[10] bfa[9] bfa[8] 00h
1 W XX bfa[7] bfa[6] bfa[5] bfa[4] bfa[3] bfa[2] bfa[1] bfa[0] 00h
Tear Effect
0 W XX 0 0 1 1 0 1 0 0 34h
Line Off
Tear Effect
0 W XX 0 0 1 1 0 1 0 1 35h
Line On
Memory 0 W XX 0 0 1 1 0 1 1 0 36h
Data
1 W XX my mx mv ml bgr mh 00h
Access
0 W XX 0 0 1 1 0 1 1 1 37h
Vertical
Vsp Vsp Vsp Vsp Vsp Vsp
Scroll Start 1 W XX vsp[9] vsp[8] 00h
[15] [14] [13] [12] [11] [10]
address
1 W XX vsp[7] vsp[6] vsp[5] vsp[4] vsp[3] vsp[2] vsp[1] vsp[0] 00h
Idle Mode Off 0 W XX 0 0 1 1 1 0 0 0 38h
Idle Mode On 0 W XX 0 0 1 1 1 0 0 1 39h
Pixel 0 0 1 1 1 0 1 0 3ah
0 W XX
Format Set dpi[2] dpi[1] dpi[0] dbi[2] dbi[1] dbi[0] 66h

New Vision Microelectronics Inc. Page 25

Command D W/ D17- Hex

D7 D6 D5 D4 D3 D2 D1 D0
function C R 8 default

Write 0 W XX 0 0 1 1 1 1 0 0 3ch
Memory D
1 W D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] XX
Continue [17-8]

Read 0 W XX 0 0 1 1 1 1 1 0 3eh
1 R XX X X X X X X X X XX
memory
D
Continue 1 R D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] XX
[17-8]
Set Tear 0 W XX 0 1 0 0 0 1 0 0 44h
1 W XX sts[8] 00h
Scanline
1 W XX sts[7] sts[6] sts[5] sts[4] sts[3] sts[2] sts[1] sts[0] 00h
0 W XX 0 1 0 0 0 1 0 1 45h
Get Tear 1 R XX X X X X X X X X XX
Scanline 1 R XX gts[8] 00h
1 R XX gts[7] gts[6] gts[5] gts[4] gts[3] gts[2] gts[1] gts[0] 00h
0 W XX 0 1 0 1 0 0 1 1 53h
Write display
Brightness 1 W XX bl 00h

0 W XX 1 1 0 1 0 0 1 1 d3h
1 R XX X X X X X X X X XX
Read ID4 1 R XX 0 0 0 0 0 0 0 0 00h
1 R XX 0 0 1 1 0 0 0 1 31h
1 R XX 0 0 1 0 1 0 0 1 29h
0 W XX 1 1 0 1 1 0 1 0 dah
Read ID1 1 R XX X X X X X X X X XX
1 R XX ID4[7] ID4[6] ID4[5] ID4[4] ID4[3] ID4[2] ID4[1] ID4[0] XX
0 W XX 1 1 0 1 1 0 1 1 dbh
Read ID2 1 R XX X X X X X X X X XX
1 R XX ID5[7] ID5[6] ID5[5] ID5[4] ID5[3] ID5[2] ID5[1] ID5[0] XX

0 W XX 1 1 0 1 1 1 0 0 dch
Read ID3
1 R XX X X X X X X X X XX
1 R XX ID6[7] ID6[6] ID6[5] ID6[4] ID6[3] ID6[2] ID6[1] ID6[0] XX

Extended commands
Note: Extended commands in the table below are only valid when send “06H” command followed by
“07H”. To exit extended commands, send “faH” command followed by “fbH”.
Command D W/ D Hex
D7 D6 D5 D4 D3 D2 D1 D0
function C R 17-8 default
RGB Interface 0 W XX 1 0 1 1 0 0 0 0 b0h
bypass
Control 1 W XX _mode
rcm[1] rcm[0] vspl hspl dpl epl 40h

0 W XX 1 0 1 1 0 0 0 1 b1h
Frame Divi Divi
1 W XX 00h
Rate1 [1] [0]
1 W XX rtni rtni rtni rtni rtni 12h
[4] [3] [2] [1] [0]

New Vision Microelectronics Inc. Page 26

0 W XX 1 0 1 1 0 0 1 0 b2h
Frame dive dive
1 W XX 00h
Rate2 [1] [0]
1 W XX
Display 0 W XX 1 0 1 1 0 1 0 0 b4h
Inversion 1 W XX nla nlb nlc 02h
0 W XX 1 0 1 1 0 1 0 1 b5h
1 W XX vfp[6] vfp[5] vfp[4] vfp[3] vfp[2] vfp[1] vfp[0] 02h
Blanking
1 W XX vbp[6] vbp[5] vbp[4] vbp[3] vbp[2] vbp[1] vpb[0] 02h
Porch
1 W XX hfp[4] hfp[3] hfp[2] hfp[1] hfp[0] 0ah
1 W XX hbp[4] hbp[3] hbp[2] hbp[1] hbp[0] 14h
0 W XX 1 0 1 1 0 1 1 0 b6h
1 W XX ptg[1] ptg[0] pts[1] pts[0] 0ah
Display
1 W XX rev gs ss sm isc[3] isc[2] isc[1] isc[0] 82h
Function
1 W XX nl[5] nl[4] nl[3] nl[2] nl[1] nl[0] 27h
1 W XX
0 W XX 1 0 1 1 0 1 1 1 b7h
Entry Mode Set
1 W XX gon dte 06h
0 W XX 1 0 1 1 1 1 1 0 Beh
Backlight 0 pwm_ pwm_ pwm_ pwm_ pwm_ pwm_ pwm_ pwm_
1 W XX 04h
div[7] div[6] div[5] div[4] div[3] div[2] div[1] div[0]
0 W XX 1 0 1 1 1 1 1 1 bfh
Backlight 1 ledonp ledpwm
1 W XX ledonr 00h
ol pol
Power 0 W XX 1 1 0 0 0 0 0 0 c0h
Control 0 1 W XX vrh[5] vrh[4] vrh[3] vrh[2] vrh[1] vrh[0] 10h
0 W XX 1 1 0 0 0 0 0 1 c1h
n3v_mo pump_ p5v_
1 W XX n3v_en p5v_en 00h
Power de 5vsel cmp_en
n20v n20v_ p20v_ p20v_
Control 1 1 W XX n20sel 00h
_md[1] md[0] md[1] md[0]
com_ com_ com_ en_ gamma_
1 W XX 00h
drv_en en2 en1 vreg1 en
0 W XX 1 1 0 0 0 1 0 0 c4h
Power
n20v_ p20v_ n3v_ p5v_
Control 4 1 W XX Oscsw1 00h
drain drain drain drain
0 W XX 1 1 0 0 0 1 0 1 c5h
Power
osc_ap osc_ap ga_ap ga_ap com_ com_ cmp_ cmp_
Control 5 1 W XX 00h
[1] [0] [1] [0] ap[1] ap[0] ap[1] ap[0]

0 W XX 1 1 0 0 0 1 1 0 c6h
Power
Control 6 rsel rsel vreg_ vreg_ ldo_ ldo_a
1 W XX rswenb 00h
[1] [0] ap[1] ap[0] ap[1] p[0]

0 W XX 1 1 0 0 0 1 1 1 c7h
Power
Control 7 ref_tr ref_tr ref_tr ref_tr osc_tr osc_tr osc_tr osc_tr
1 W XX 03h
m[3] m[2] m[1] m[0] m[3] m[2] m[1] m[0]

New Vision Microelectronics Inc. Page 27

Power 0 W XX 1 1 0 0 1 0 0 0 c8h
vram vram i_trm i_trm i_trm
Control 8 1 W XX 20h
[2] [0] [2] [1] [0]
Power 0 W XX 1 1 0 0 1 0 0 1 c9h
Control 9 1 W XX ldo_en osc_en bg_en 13h
Power 0 W XX 1 1 0 0 1 0 1 0 cah
Control a 1 W XX dc1[2] dc1[1] dc1[0] dc0[2] dc0[1] dc0[0] 23h
Power 0 W XX 1 1 0 0 1 0 1 1 cbh
Control b 1 W XX vc[1] vc[0] sap[1] sap[0] 20h

Vcom 0 W XX 1 1 0 0 1 1 0 0 cch
vcm0 vcm0 vcm0 vcm0 Vcm0 vcm0
Control 1 1 W XX 31h
[5] [4] [3] [2] [1] [0]

Vcom 0 W XX 1 1 0 0 1 1 0 1 cdh
vdv0 vdv0 vdv0 vdv0 vdv0
Control 2 1 W XX 18h
[4] [3] [2] [1] [0]
0 W XX 1 1 0 0 1 1 1 0 ceh
Vcom
vcm_ot vcm_ot vcm_ot vcm_ot vcm_ot vcm_ot
Control 3 1 R XX XX
p[5] p[4] p[3] p[2] p[1] p[0]
0 W XX 1 1 0 0 1 1 1 1 cfh
Vcom
vdv_ot vdv_ot vdv_ot vdv_ot vdv_ot
Control 4 1 R XX XX
p[4] p[3] p[2] p[1] p[0]
0 W XX 1 1 0 1 0 0 0 0 d0h
OTP
Pdin Pdin Pdin Pdin Pdin Pdin Pdin Pdin
Control 0 1 W XX
[7] [6] [5] [4] [3] [2] [1] [0]
0 W XX 1 1 0 1 0 0 0 1 d1h
OTP
power_
control 1 1 W XX por pprog pwe Ptm[1] Ptm[0] Pa[1] Pa[0]
sel

OTP 0 W XX 1 1 0 1 0 0 1 0 d2h
control 2 1 W XX OTP[7] OTP[6] OTP[5] OTP[4] OTP[3] OTP[2] OTP[1] OTP[0]

OTP 0 W XX 1 1 0 1 0 0 1 1 d3h
OTP OTP OTP OTP OTP OTP
control 3 1 W XX OTP[9] OTP[8]
[15] [14] [13] [12] [11] [10]
0 W XX 1 1 0 1 0 1 0 0 d4h
OTP
OTP OTP OTP OTP OTP OTP OTP OTP
control 4 1 W XX
[23] [22] [21] [20] [19] [18] [17] [16]
0 W XX 1 1 0 1 0 1 0 1 d5h
OTP
OTP OTP OTP OTP OTP OTP OTP OTP
control 5 1 W XX
[31] [30] [29] [28] [27] [26] [25] [24]
Gamma 0 W XX 1 1 1 0 0 0 0 0 e0h
Positive 1 1 W XX kp1[2] kp1[1] kp1[0] kp0[2] kp0[1] kp0[0] 17h
Gamma 0 W XX 1 1 1 0 0 0 0 1 e1h
Positive 2 1 W XX kp3[2] kp3[1] kp3[0] kp2[2] kp2[1] kp2[0] 01h
Gamma 0 W XX 1 1 1 0 0 0 1 0 e2h
Positive 3 1 W XX kp5[2] kp5[1] kp5[0] kp4[2] kp4[1] kp4[0] 77h
Gamma 0 W XX 1 1 1 0 0 0 1 1 e3h
Positive 4 1 W XX rp1[2] rp1[1] rp1[0] rp0[2] rp0[1] rp0[0] 54h

New Vision Microelectronics Inc. Page 28

Gamma 0 W XX 1 1 1 0 0 1 0 0 e4h
prc0 prc0 prc0 vrp0 vrp0 vrp0 vrp0 vrp0
Positive 5 1 W XX 80h
[2] [1] [0] [4] [3] [2] [1] [0]
Gamma 0 W XX 1 1 1 0 0 1 0 1 e5h

Positive 6 prc1 prc1 prc1 vrp1 vrp1 vrp1 vrp1 vrp1

1 W XX 88h
[2] [1] [0] [4] [3] [2] [1] [0]
Gamma 0 W XX 1 1 1 0 0 1 1 0 e6h
Negative 1 1 W XX kn1[2] kn1[1] kn1[0] kn0[2] kn0[1] kn0 00h
[0]
Gamma 0 W XX 1 1 1 0 0 1 1 1 e7h
Negative 2 1 W XX kp3[2] kp3[1] kp3[0] kp2[2] kp2[1] kp2[0] 67h
Gamma 0 W XX 1 1 1 0 1 0 0 0 e8h
Negative 3 1 W XX kn5[2] kn5[1] kn5[0] kn4[2] kn4[1] kn4[0] 06h
Gamma 0 W XX 1 1 1 0 1 0 0 1 e9h
Negative 4 1 W XX rn1[2] rn1[1] rn1[0] rn0[2] rn0[1] rn0[0] 46h

Gamma 0 W XX 1 1 1 0 0 1 0 0 eah
prc2 prc2 prc2 vrn0 vrn0 vrn0 vrn0 vrn0
Negative 5 1 W XX 88h
[2] [1] [0] [4] [3] [2] [1] [0]
Gamma 0 W XX 1 1 1 0 0 1 0 1 ebh
prc3 prc3 prc3 vrn1 vrn1 vrn1 vrn1 vrn1
Negative 6 1 W XX 88h
[2] [1] [0] [4] [3] [2] [1] [0]
0 W XX 1 1 1 0 1 1 0 0 ech
nowe Nowe Nowe Nowe Nowi Nowi Nowi
1 W XX 22h
[3] [2] [1] [0] [2] [1] [0]
nowi_e nowi_e nowi_e nowi_e nowi_e nowi_e nowi_e nowi_e
1 W XX 11h
[7] [6] [5] [4] [3] [2] [1] [0]
nowe_e nowe_e nowe_e nowe_e nowe_e nowe_e nowe_e nowe_e
1 W XX 11h
[7] [6] [5] [4] [3] [2] [1] [0]
Driver Timing Vcsiv Vcsiv Vcsiv Scsiv Scsiv scsiv[
1 W XX vcsie scsie a0h
[2] [1] [0] [2] [1] 0]
Vcsev Vcsev[ Vcsev[ scsev[ Scsev scsev[
1 W XX vcsee scsee a0h
[2] 1] 0] 2] [1] 0]
mcpe mcpe mcpe mcpe mcpi mcpi mcpi
1 W XX 11h
[3] [2] [1] [0] [2] [1] [0]
mspe mspe mspe mspe mspi mspi mspi
1 W XX 11h
[3] [2] [1] [0] [2] [1] [0]
0 W XX 1 1 1 1 0 1 0 0 f4h
Hsync Width hsync_wid hsync_wid hsync_wid hsync_wid hsync_wid hsync_wid
1 W XX
th[5] th[4] th[3] th[2] th[1] th[0] 00h

0 W XX 1 1 1 1 0 1 0 1 f5h
Vsync Width vsync_w Vsync_w vsync_w vsync_w vsync_w vsync_w
1 W XX idth[5] idth[4] idth[3] idth[2] idth[1] idth[0]
00h

0 W XX 1 1 1 1 0 1 1 0 f6h
Interface 1 W XX my_eor mx_eor mv_eor bgr_eo we_mod 18h
Control 1 W XX epf[1] epf[0] mdt[1] mdt[0] 00h
1 W XX endian dm[1] dm[0] rm rim 00h
PWM Duty 0 W XX 1 1 1 1 1 0 0 0 f8h
pwm_dr pwm_dr pwm_dr pwm_dr pwm_dr
Ratio 1 W XX 00h
[4] [3] [2] [1] [0]

New Vision Microelectronics Inc. Page 29

8.2. Command description

8.2.1. System interface command description
8.2.1.1. NOP(00h)

00h NOP （No Operation)

DC RD WR D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 1 ↑ XX 0 0 0 0 0 0 0 0 00
Parameter NO parameter
This command is empty command. It does not have any effect on the display module
However it can be used to terminate frame memory write as described in RAMWR(Memory
Description
Write) and RAMRD(Memory Read) Commands.
X=Don’t care
Restriction

Status Availability
Normal Mode On, idle Mode Off, Sleep Out Yes
Register Normal Mode On, idle Mode On, Sleep Out Yes
availability
Partial Mode On, idle Mode Off, Sleep Out Yes
Partial Mode On, idle Mode On, Sleep Out Yes
Sleep in or Booster Off Yes

Status Default Value

Power On Sequence N/A
Default
S/W Reset N/A
H/W Reset N/A

Flow chart

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8.2.1.2. Software Reset (01h)

01h SWRESET(Software Reset)

DC RD WR D15-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 1 ↑ XX 0 0 0 0 0 0 0 1 01
Parameter NO parameter
When the Software Reset command is written, it causes a software reset. It resets the
commands and parameters to their S/W Reset default values. (See default tables in each
Description command description.)
Note: The Frame Memory contents are unaffected by this command.
X = don’t care.
It will be necessary to wait 5 msec before sending new command following software reset.
The display module loads all display suppliers’ factory default values to the registers during
Restriction this 5 msec. If Software Reset is applied during Sleep Out mode, it will be necessary to wait
120 msec before sending Sleep Out command. Software Reset Command cannot be sent
during Sleep Out sequence.
Status Availability
Normal Mode On, Idle Mode Off, Sleep Out Yes
Register Normal Mode On, Idle Mode On, Sleep Out Yes
availability Partial Mode On, Idle Mode Off, Sleep Out Yes
Partial Mode On, Idle Mode On, Sleep Out Yes
Sleep in or Booster Off Yes
Status Default Value
Power On Sequence N/A
Default
S/W Reset N/A
H/W Reset N/A

Legend
SWRESET

Command
Display Whole Parameter
blank screen
Display
Flow chart
Action
Set Commands to
S/W Default Value
Mode

Sequential
Sleep In Mode transfer

New Vision Microelectronics Inc. Page 31

8.2.1.3. Read Display Identification Information (04h)

04h RDDIDIF (Read Display Identification Information)
D R W D17
D7 D6 D5 D4 D3 D2 D1 D0 HEX
C D R -8
Command 0 1 ↑ XX 0 0 0 0 0 1 0 0 04

1st parameter 1 ↑ 1 XX X X X X X X X X X

2nd parameter 1 ↑ 1 XX Id1[7] Id1[6] Id1[5] Id1[4] Id1[3] Id1[2] Id1[1] Id1[0] XX

3rdparameter 1 ↑ 1
XX
Id2[7] Id2[6] Id2[5] Id2[4] Id2[3] Id2[2] Id2[1] Id2[0] XX

4thparameter 1 ↑ 1 XX Id3[7] Id3[6] Id3[5] Id3[4] Id3[3] Id3[2] Id3[1] Id3[0] XX

This read byte returns 24-bits display identification information.

The 1st Parameter is dummy read.
Description The 2nd Parameter identifies the LCD module’s manufacture.
The 3rd Parameter identifies the LCD module/driver version ID.
The 4th Parameter identifies the LCD module/driver ID.
Restriction
Status Availability
Normal Mode On, Idle Mode Off, Sleep Out Yes
Register Normal Mode On, Idle Mode On, Sleep Out Yes
Availability Partial Mode On, Idle Mode Off, Sleep Out Yes
Partial Mode On, Idle Mode On, Sleep Out Yes
Sleep in or Booster Off Yes
Status Default Value
Power On Sequence N/A
Default
S/W Reset N/A
H/W Reset N/A

Flow Chart

New Vision Microelectronics Inc. Page 32

8.2.1.4. Read Display Status (09h)

09h RDDST (Read Display Status)

DC RD WR D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 1 ↑ XX 0 0 0 0 1 0 0 1 09
st
1 parameter 1 ↑ 1 XX X X X X X X X X X

2
nd
arameter 1 ↑ 1 XX D[31] D[30] D[29] D[28] D[27] D[26] D[25] 0 00

3rdparameter 1 ↑ 1 XX 0 D[22] D[21] D[20] D[19] D[18] D[17] D[16] 61

th
4 parameter 1 ↑ 1 XX D[15] 0 D[13] 0 0 D[10] D[9] D[8] 00
th
5 parameter 1 ↑ 1 XX D[7] D[6] D[5] 0 0 0 0 0 00

This command indicates the current status of the display as described in the table below:
Bit Description Comment
D[31] Booster Voltage Status
D[30] Page Address Order
D[29] Column Address Order
D[28] Page/Column Order
D[27] Vertical Order
D[26] RGB/BGR Order
LCD Horizontal refresh
D[25] Horizontal refresh order(MH)
direction control
D[24] - Set to ‘0’
D[23] - Set to ‘0’
D[22]
D[21] Interface Color Pixel Format Definition
D[20]
D[19] Idle Mode On/Off
D[18] Partial Mode On/Off
Description D[17] Sleep In/Out
D[16] Display Normal Mode On/Off
D[15] Vertical Scrolling Status
D[14] - Set to ‘0’
D[13] Inversion Status
D[12] - Set to ‘0’
D[11] - Set to ‘0’
D[10] Display On/Off
D[9] Tearing Effect Line On/Off
D[8] - Set to ‘0’
D[7] - Set to ‘0’
D[6] - Set to ‘0’
D[5] Tearing Effect Output Line Mode
D[4] For Future Use Set to ‘0’
D[3] For Future Use Set to ‘0’
D[2] For Future Use Set to ‘0’
D[1] For Future Use Set to ‘0’
D[0] For Future Use Set to ‘0’

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- Bit D[31]: Booster Voltage status.

”0”: Booster Off.
”1”: Booster On.
- Bit D[30]: Page Address Order.
“0”: Top to Bottom (When MADCTL B7 = ‘0’).
“1”: Bottom to Top (When MADCTL B7 = ‘1’).
- Bit D[29]: Column Address Order.
“0”: Left to Right (When MADCTL B6 = ‘0’).
“1”: Right to Left (When MADCTL B6 = ‘1’).
- Bit D[28]: Page/Column Order.
“0”: Normal Mode (When MADCTL B5 = ‘0’).
“1”: Reverse Mode (When MADCTL B5 = ‘1’).
Note: For Bits D30 to D28, also refer to Section 9.2.3
- Bit D[27]: Line Address Order
“0”: LCD Refresh Top to Bottom (When MADCTL B4 = ‘0’).
“1”: LCD Refresh Bottom to Top (When MADCTL B4 = ‘1’).
- Bit D[26]: RGB/BGR Order
“0”: RGB (When MADCTL B3 = ‘0’).
Description
“1”: BGR (When MADCTL B3 = ‘1’).
- Bit D[25]: set to “0”
Note: For Bits D[27], D[26] and D[25] also refer to 8.2.1.27.
- Bit D[24]: set to “0”
- Bit D[23]: set to “0”
- Bits D[22], D[21], D[20]: Interface Color Pixel Format Definition.
Interface Format D[22] D[21] D[20]
Not Defined 0 0 0
Not Defined 0 0 1
Not Defined 0 1 0
Not defined 0 1 1
Not Defined 1 0 0
16 Bit/Pixel 1 0 1
18 Bit/Pixel 1 1 0
18 Bit/Pixel 1 1 1
- Bit D[19]: Idle Mode On/Off
“0”: Idle Mode Off.
“1”: Idle Mode On.
- Bit D[18]: Partial Mode On/Off
“0”: Partial Mode Off.
“1”: Partial Mode On.

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- Bit D[17]: Sleep In/Out

“0”: Sleep In Mode.
“1”: Sleep Out Mode.
- Bit D[16]: Display Normal Mode
“0”: Display Normal Mode Off.
“1”: Display Normal Mode On.
- Bit D[15]: Vertical Scroll Status
“0”: Vertical Scrolling is Off.
“1”: Vertical Scrolling is On.
- Bit D[14]: set to “0”
- Bit D[13]: Inversion Status
“0”: Inversion is Off.
“1”: Inversion is On.
Description
- Bit D[12]: set to “0”
- Bit D[11]: set to “0”
- Bit D[10]: Display On/Off
“0”: Display is Off.
“1”: Display is On.
- Bit D[9]: Tearing Effect Line On/Off
“0”: Tearing Effect Line Off.
“1”: Tearing Effect Line On.
- Bit D[5]: Tearing Effect Line Output Mode
“0”: Mode 1, V-Blanking only.
“1”: Mode 2, both H-Blanking and V-Blanking.
- Bit D[4], Bit D[3], Bit D[2], Bit D[1] and Bit D[0] are for future use and are set to “0”
X = Don’t care
Restriction

Status Availability
Normal Mode On, Idle Mode Off, Sleep Out Yes

Register
Normal Mode On, Idle Mode On, Sleep Out Yes
Availability Partial Mode On, Idle Mode Off, Sleep Out Yes
Partial Mode On, Idle Mode On, Sleep Out Yes
Sleep in or Booster Off Yes

New Vision Microelectronics Inc. Page 35

Status Default Value

Power On Sequence N/A
Default
S/W Reset N/A
H/W Reset N/A

Flow Chart

8.2.1.5. Read Display Power Mode (0Ah)

0Ah RDDPM (Read Display Power Mode)
R W
DC D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX
D R
Command 0 1 ↑ XX 0 0 0 0 1 0 1 0 0A
st
1 parameter 1 ↑ 1 XX X X X X X X X X X

2nd parameter 1 ↑ 1 XX D[7] D[6] D[5] D[4] D[3] D[2] 0 0 08

This command indicates the current status of the display as described in the table below:
Bit Description Comment
D[7] Booster Voltage Status
D[6] Idle Mode On/Off
D[5] Partial Mode On/Off
Description
D[4] Sleep In/Out
D[3] Display Normal Mode On/Off
D[2] Display On/Off
D[1] - Set to ‘0’
D[0] - Set to ‘0’

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- Bit D[7] : Booster Voltage Status

“0”: Booster Off or has a fault.
“1”: Booster On and working OK
- Bit D[6 ]: Idle Mode On/Off
“0”: Idle Mode Off.
“1”: Idle Mode On.
- Bit D[5] : Partial Mode On/Off
“0”: Partial Mode Off.
“1”: Partial Mode On.
- Bit D[4] : Sleep In/Out
“0”: Sleep In Mode.
“1”: Sleep Out Mode.
- Bit D[3] : Display Normal Mode On/Off
“0”: Display Normal Mode Off.
“1”: Display Normal Mode On.
- Bit D[2] : Display On/Off
“0”: Display Off.
“1”: Display On.
- Bit D[1] : set to “0”
- Bit D[0] : set to “0”
X = Don’t care
Restriction
Status Availability
Normal Mode On, Idle Mode Off, Sleep Out Yes
Normal Mode On, Idle Mode On, Sleep Out Yes
Register
Availability Partial Mode On, Idle Mode Off, Sleep Out Yes
Partial Mode On, Idle Mode On, Sleep Out Yes
Sleep in or Booster Off Yes

Status Default Value

Power On Sequence 08h
Default
S/W Reset 08h
H/W Reset 08h

Flow Chart

New Vision Microelectronics Inc. Page 37

8.2.1.6. Read Display Madctl (0Bh)

0Bh RDDMADCTL (Read Display MADCTL)
R W D17-
DC D7 D6 D5 D4 D3 D2 D1 D0 HEX
D R 8
Command 0 1 ↑ XX 0 0 0 0 1 0 1 1 0B
st
1 parameter 1 ↑ 1 XX X X X X X X X X X

2nd parameter 1 ↑ 1 XX D[7] D[6] D[5] D[4] D[3] 0 0 0 XX

This command indicates the current status of the display as described in the table below:
Bit Description Comment
D[7] Page Address Order
D[6] Column Address Order
D[5] Page/Column Order
D[4] Line Address Order
D[3] RGB/BGR Order
D[2] - Set to ‘0’
D[1] - Set to ‘0’
D[0] - Set to ‘0’
- Bit D[7] : Page Address Order
“0”: Top to Bottom (When MADCTL B7=’0’).
“1”: Bottom to Top (When MADCTL B7=’1’).
- Bit D[6] : Column Address Order
“0”: Left to Right (When MADCTL B6=’0’).
Description “1”: Right to Left (when MADCTL B6=’1’
- Bit D[5] : Page/column Order
“0”: Normal Mode (When MADCTL B5=’0’).
“1”: Reverse Mode (When MADCTL B5=’1’)
Note: For Bits D7 to D5, also refer to Section 9.2.3 MCU to Memory write/read direction.
- Bit D[4 ]: Line Address Order
“0”: LCD Refresh Top to Bottom (When MADCTL B4=’0’).
“1”: LCD Refresh Bottom to Top (When MADCTL B4=’1’).
- Bit D[3] : RGB/BGR Order
“0”: RGB (When MADCTL B3=’0’).
“1”: BGR (When MADCTL B3=’1’).
- Bit D[2] : set to ‘0’
Note: For Bits D4 also refer to 8.2.1.27 Memory Access Control (36h).
- Bit D[1] : set to ‘0’
- Bit D[0] : set to ‘0’
X = Don’t care

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Restriction

Status Availability
Normal Mode On, Idle Mode Off, Sleep Out Yes
Register Normal Mode On, Idle Mode On, Sleep Out Yes
Availability
Partial Mode On, Idle Mode Off, Sleep Out Yes
Partial Mode On, Idle Mode On, Sleep Out Yes
Sleep in or Booster Off Yes
Status Default Value
Power On Sequence 00h
Default
S/W Reset No change
H/W Reset 00h

Legend

Command
Read RDDMADCTL Parameter
Host
Display
Flow Chart Display
Dummy Read Action

Mode

Send 2nd parameter Sequential

transfer

8.2.1.7 Read Display Pixel Format(0Ch)

0Ch RDDCOLMOD(Read Display COLMOD)

D17-
DC RD WR D7 D6 D5 D4 D3 D2 D1 D0 HEX
8
Command 0 1 ↑ XX 0 0 0 0 1 1 0 0 0C
1st parameter 1 ↑ 1 XX X X X X X X X X X

2nd parameter 1 ↑ 1 XX 0 0 0 0 0 D[2] D[1] D[0] 06

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This command indicates the current status of the display as described in the table

below:
Bit Description Comment
D[7] - Set to ‘0’
D[6] - Set to ‘0’
D[5] - Set to ‘0’
D[4] - Set to ‘0’
D[3] - Set to ‘0’
D[2]
D[1] Control interface Color Format
D[0]
Description - Bit D[7 ]: set to’0’.
- Bit D[6], D[5], D[4] : set to ‘0’s.
- Bit D[3] : set to ‘0’.
- Bit D[2], D[1], D[0] : Control Interface Color Pixel Format Definition. See section
8.2.1.31 Interface

Pixel Format (3Ah).

Control Interface Color Format D2 D1 D0
Not Defined 0 0 0
Not Defined 0 0 1
Not Defined 0 1 0
Not Defined 0 1 1
Not Defined 1 0 0
16bit/pixel 1 0 1
18bit/pixel 1 1 0
18bit/pixel 1 1 1
X=Don’t care
Restriction
Status Availability
Normal Mode On, Idle Mode Off, Sleep Out Yes

Register Normal Mode On, Idle Mode On, Sleep Out Yes
Availability Partial Mode On, Idle Mode Off, Sleep Out Yes
Partial Mode On, Idle Mode On, Sleep Out Yes
Sleep in or Booster Off Yes
Status Default Value
Power On Sequence 18bit/pixel
Default
S/W Reset No change
H/W Reset 18bit/pixel

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Flow Chart

8.2.1.8. Read Display Image Mode (0Dh)

0Dh RDDIM(Read Display Image Mode)

DC RD WR D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 1 ↑ XX 0 0 0 0 1 1 0 1 0D
st
1
1 ↑ 1 XX X X X X X X X X X
parameter
2nd
1 ↑ 1 XX 0 D[6] 0 D[4] 0 0 0 0 XX
parameter
This command indicates the current status of the display as described in the table below:
- Bit D[6] : Vertical Scrolling On/Off
“0”: Vertical Scrolling Off.
Descriptio
“1”: Vertical Scrolling On.
n - Bit D[4] : Inversion On/Off
“0”: Inversion Off.
“1”: Inversion On.
- Bit D[3 ]: set to ‘0’

Restriction

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Status Default Value

Power On Sequence 00HEX
Default
S/W Reset 00HEX
H/W Reset 00HEX

Legend

Command
Read RDDIM Parameter
Host
Display
Flow
Display
Chart Dummy Read Action

Mode

Send 2nd parameter Sequential

transfer

8.2.1.9. Read Display Signal Mode (0Eh)

0EH RDDSM(Read Display Signal Mode)

R W
DC D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX
D R
Command 0 1 ↑ XX 0 0 0 0 1 1 1 0 0E
st
1 parameter 1 ↑ 1 XX X X X X X X X X X

2nd parameter 1 ↑ 1 XX D[7] D[6] 0 0 0 0 0 0 00

This command indicates the current status of the display as described in the table below:

- Bit D[7] : Tearing Effect Line On/Off

“0”: Tearing Effect Line Off.

Description
“1”: Tearing Effect On.

- Bit D[6] : Tearing Effect Line Output Mode, see section 9.3 for mode definitions.

“0”: Mode 1.

“1”: Mode 2.

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- Bit D[6] : Tearing Effect Line Output Mode, see section 9.3 for mode definitions.

“0”: Mode 1.

“1”: Mode 2.

- Bit D[5] : set to ‘0’

- Bit D[4] : set to ‘0’

- Bit D[3] : set to ‘0’

- Bit D[2]: set to ‘0’

- Bit D[1], D[0] : set to ‘0’

Restriction
Status Availability
Normal Mode On, Idle Mode Off, Sleep Out Yes

Flow Chart

8.2.1.10. Read Display Self-Diagnostic Result (0Fh)

New Vision Microelectronics Inc. Page 43

0Fh RDDSDR(Read Display Self-Diagnostic Result)

D R W
D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX
C D R
Command 0 1 ↑ XX 0 0 0 0 1 1 1 1 0F
1st parameter 1 ↑ 1 XX X X X X X X X X X

2nd parameter 1 ↑ 1 XX D[7] D[6] 0 0 0 0 0 0 00

This command indicates the current status of the display as described in the table below:
- Bit D[7] : Register loading detection.
Inverting the D7 bit if registers values loading work properly.
- Bit D[6] : Functionality detection.
Description Inverting the D6 bit if the display is on function.
- Bit D[5] : set to ‘0’
- Bit D[4] : set to ‘0’
- Bit D[3 ]: set to ‘0’
- Bit D[2 ]: set to ‘0’
- Bit D[1], D[0] : set to ‘0’
Restriction
Status Availability
Normal Mode On, Idle Mode Off, Sleep Out Yes

Flow Chart

New Vision Microelectronics Inc. Page 44

8.2.1.11. Sleep In (10h)

10h SLPIN(Sleep In)

DC RD WR D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 1 ↑ XX 0 0 0 1 0 0 0 0 10
Parameter NO PARAMETER
This command causes the LCD module to enter the minimum power consumption mode.
In this mode the DC/DC converter is stopped, Internal oscillator is stopped, and panel
scanning is
stopped.

Description

MCU interfaces and memory are still working and the memory keeps its contents.
See also section 9.5.2.
X = Don’t care
This command has no effect when module is already in Sleep in mode. Sleep in mode can
only be left by the Sleep Out command(11h)
It will be necessary to wait 5msec before sending nest command, this is to allow time for the
Restriction
supply voltages and clock circuits to stabilize.
It will be necessary to wait 120msec after sending Sleep Out command (when in Sleep In
Mode) before Sleep In command can be sent.
Status Availability

Register Normal Mode On, Idle Mode Off, Sleep Out Yes
Availability Normal Mode On, Idle Mode On, Sleep Out Yes
Partial Mode On, Idle Mode Off, Sleep Out Yes

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Partial Mode On, Idle Mode On, Sleep Out Yes

SleepIn Yes

Status Default Value

Default Power On Sequence Sleep In Mode

S/W Reset Sleep In Mode
H/W Reset Sleep In Mode

It takes 120msec to get into Sleep In mode after SLPIN command issued

Flow Chart

New Vision Microelectronics Inc. Page 46

8.2.1.12. Sleep Out(11h)

11h SLPOUT(Sleep Out)

R W
DC D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX
D R
Command 0 1 ↑ XX 0 0 0 1 0 0 0 1 11
Parameter NO PARAMETER
This command turns off sleep mode.

In this mode the DC/DC converter is enabled, Internal oscillator is started, and panel

scanning is started.

Description

New Vision Microelectronics Inc. Page 47

Status Availability
Normal Mode On, Idle Mode Off, Sleep Out Yes

Register Normal Mode On, Idle Mode On, Sleep Out Yes
Availability Partial Mode On, Idle Mode Off, Sleep Out Yes
Partial Mode On, Idle Mode On, Sleep Out Yes
Sleep In Yes
Status Default Value
Power On Sequence Sleep In Mode
Default
S/W Reset Sleep In Mode
H/W Reset Sleep In Mode

It takes 120msec to get into Sleep Out mode after SLPOUT command issued

Flow Chart

New Vision Microelectronics Inc. Page 48

8.2.1.13. Partial Mode On (12h)

12h PTLON(Partial Mode On)

R W
DC D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX
D R
Command 0 1 ↑ XX 0 0 0 1 0 0 1 0 12
Parameter NO PARAMETER

This command turns on partial mode. The partial mode window is described by
the Partial Area Command (30H).
Description
To leave Partial mode, the Normal Display Mode command (13 H) should be written.
See also section 9.5.2.
X = Don’t care

Restriction This command has no effect when Partial mode is active.

Status Availability
Normal Mode On, Idle Mode Off, Sleep Out Yes
Register Normal Mode On, Idle Mode On, Sleep Out Yes
Availability Partial Mode On, Idle Mode Off, Sleep Out Yes
Partial Mode On, Idle Mode On, Sleep Out Yes
Sleep In Yes
Status Default Value
Power On Sequence Normal Display Mode On
Default S/W Reset Normal Display Mode On
H/W Reset Normal Display Mode On

Flow Chart See Partial Area(30h)

8.2.1.14. Normal Display Mode On(13h)

13h NORON (Normal Display Mode On)

DC RD WR D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 1 ↑ XX 0 0 0 1 0 0 1 1 13
Parameter NO PARAMETER
This command returns the display to normal mode.
Normal Display Mode On means Partial mode off.
Description
See also section 9.5.2.
X = Don’t care

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Restriction This command has no effect when Normal Display mode is active.

Status Availability
Normal Mode On, Idle Mode Off, Sleep Out Yes
Normal Mode On, Idle Mode On, Sleep Out Yes
Register Partial Mode On, Idle Mode Off, Sleep Out Yes
Availability
Partial Mode On, Idle Mode On, Sleep Out Yes
Sleep In or Booster Off Yes

Status Default Value

Power On Sequence Normal Display Mode On
Default S/W Reset Normal Display Mode On
H/W Reset Normal Display Mode On

Flow Chart See Partial Area(30h)

8.2.1.15. Display Inversion Off (20h)

20h DINVOFF (Display Inversion Off)

D
RD WR D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX
C
Command 0 1 ↑ XX 0 0 1 0 0 0 0 0 20
Parameter NO PARAMETER

This command is used to r ecove r from display in version mode. This command makes No Change of contents
of frame memory. This command does not change any other status.

Description

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Restriction This command has no effect when module is already in inversion off mode.

Status Availability
Normal Mode On, Idle Mode Off, Sleep Out Yes
Normal Mode On, Idle Mode On, Sleep Out Yes
Register
Availability Partial Mode On, Idle Mode Off, Sleep Out Yes
Partial Mode On, Idle Mode On, Sleep Out Yes
Sleep In Yes

Status Default Value

Power On Sequence Display Inversion Off
Default
S/W Reset Display Inversion Off
H/W Reset Display Inversion Off

Flow Chart

8.2.1.16. Display Inversion On(21h)

21h DINVON (Display Inversion On)

DC RD WR D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 1 ↑ XX 0 0 1 0 0 0 0 1 21
Parameter NO PARAMETER
This command is used to enter into display inversion mode. This command makes No
Change of contents of frame memory.

New Vision Microelectronics Inc. Page 51

Description

X=Don’t care

Restriction This command has no effect when module is already in inversion on mode.
Status Availability
Normal Mode On, Idle Mode Off, Sleep Out Yes

Register Normal Mode On, Idle Mode On, Sleep Out Yes
Availability Partial Mode On, Idle Mode Off, Sleep Out Yes
Partial Mode On, Idle Mode On, Sleep Out Yes
Sleep In Yes
Status Default Value
Power On Sequence Display Inversion Off
Default
S/W Reset Display Inversion Off
H/W Reset Display Inversion Off

Legend

Command
Display Inversion
Off Mode Parameter

Display
Flow Chart INVON
Action

Mode
Display Inversion
On Mode
Sequential
transfer

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8.2.1.17. Display Off (28h)

28h DISPOFF(Display Off)

DC RD WR D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 1 ↑ XX 0 0 1 0 1 0 0 0 28
Parameter NO PARAMETER
This command is used to enter into Display Off mode
In this mode, the output from Frame Memory is disabled and blank page is inserted.
This command is makes No Change any other status.
There will be no abnormal visible effect on the display
This command is makes No Change of contents of frame memory

Description

X=Don’t care
Restriction This command has no effect when module is already in display off mode.
Status Availability
Normal Mode On, Idle Mode Off, Sleep Out Yes

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Flow Chart

8.2.1.18. Display On(29h)

29h DISPON(Display On)

R W
DC D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX
D R
Command 0 1 ↑ XX 0 0 1 0 1 0 0 1 29
Parameter NO PARAMETER
This command is used to recover from Display Off Mode. Output from the Frame
Memory is enabled.
This command makes No Change of contents of frame memory
This command does not change any other status.

Description

X=Don’t care
Restriction This command has no effect when module is already in display on mode.

Register Status Availability

Availability Normal Mode On, Idle Mode Off, Sleep Out Yes

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Normal Mode On, Idle Mode On, Sleep Out Yes

Partial Mode On, Idle Mode Off, Sleep Out Yes
Partial Mode On, Idle Mode On, Sleep Out Yes
Sleep In Yes
Status Default Value
Power On Sequence Display Off
Default
S/W Reset Display Off
H/W Reset Display Off

Flow Chart

8.2.1.19. Column Address Set(2Ah)

2Ah CASET(Column Address Set)

D R W D
D7 D6 D5 D4 D3 D2 D1 D0 HEX
C D R 17-8
Command 0 1 ↑ XX 0 0 1 0 1 0 1 0 2A

1st SC SC SC SC SC
0 1 ↑ XX SC11 SC9 SC8
parameter 15 14 13 12 10
Note1
2nd
0 1 ↑ XX SC7 SC6 SC5 SC4 SC3 SC2 SC1 SC1
parameter

3rd EC EC EC EC EC
0 1 ↑ XX EC11 EC9 EC8
parameter 15 14 13 12 10
Note1
4th
0 1 ↑ XX EC7 EC6 EC5 EC4 EC3 EC2 EC1 EC0
parameter

New Vision Microelectronics Inc. Page 55

This command is used to define area of frame memory where MCU can access. This command
makes No Change on the other driver status.
The values of SC[15:0] and EC[15:0] are referred when RAMWR command comes. Each value
represents one column line in the Frame Memory.

Description

X=Don’t care

SC[15:0] always must be equal to or less than EC[15:0].

Restriction Note 1: When SC[15:0] or EC[15:0] is greater than 00EFh (When MADCTL’s B5 = 0) or
013Fh (When MADCTL’s B5 = 1), data of out of range will be ignored.

Status Default Value

Power On
SC[15:0]=0000HEX EC[15:0]=00EFHEX
Default Sequence
If MADCTL’S B5=0:EC[15:0]=00EFHEX
S/W Reset SC[15:0]=0000HEX
If MADCTL’S B5=1:EC[15:0]=013FHEX
H/W Reset SC[15:0]=0000HEX EC[15:0]=00EFHEX

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Flow
Chart

8.2.1.20. Page Address Set (2Bh)

2Bh PASET(Page Address Set)

W D
DC RD D7 D6 D5 D4 D3 D2 D1 D0 HEX
R 17-8
Command 0 1 ↑ XX 0 0 1 0 1 0 1 1 2B

1st SP SP SP SP SP SP
0 1 ↑ XX SP9 SP8
parameter 15 14 13 12 11 10 Note
nd 1
2
0 1 ↑ XX SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP1
parameter

3rd EP EP EP EP EP EP Note
0 1 ↑ XX EP9 EP8
parameter 15 14 13 12 11 10 1

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4
th
0 1 ↑ XX EP7 EP6 EP5 EP4 EP3 EP2 EP1 EP0
parameter
This command is used to define area of frame memory where MCU can access. This command
makes No Change on the other driver status.
Description
The values of SP[15:0] and EP[15:0] are referred when RAMWR command comes. Each value
represents one column line in the Frame Memory.

Description

X=Don’t care
SP[15:0] always must be equal to or less than EP[15:0].
Restriction Note 1: When SP[15:0] or EP[15:0] is greater than 00EFh (When MADCTL’s B5 = 0) or
013Fh (When MADCTL’s B5 = 1), data of out of range will be ignored.
Status Availability
Normal Mode On, Idle Mode Off, Sleep Out Yes

Register Normal Mode On, Idle Mode On, Sleep Out Yes
Availability Partial Mode On, Idle Mode Off, Sleep Out Yes
Partial Mode On, Idle Mode On, Sleep Out Yes
Sleep In Yes
Status Default Value
Power On
SP[15:0]=0000HEX EP[15:0]=00EFHEX
Sequence
Default
If MADCTL’S B5=0:EP[15:0]=00EFHEX
S/W Reset SP[15:0]=0000HEX
If MADCTL’S B5=1:EP[15:0]=013FHEX
H/W Reset SP[15:0]=0000HEX EP[15:0]=00EFHEX

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CASET

1st & 2nd parameter SC[15：0］

3rd & 4th parameter EC[15：0］

Legend
PASET
Command

1st & 2nd parameter SP[15：0］ Parameter

3rd & 4th parameter EP[15：0］
Display
Flow Chart

If needed
PAMWR Action

Mode

Image Data
D1 [15：0］， Sequential
D2[15：0］ transfer
...Dn[15：0］

Any Command

8.2.1.21. Memory Write(2Ch)

2CH RAMWR(Memory Write)

D R D D D D D D D D
WR D17-8 HEX
C D 7 6 5 4 3 2 1 0
Command 0 1 ↑ XX 0 0 1 0 1 1 0 0 2C
0000
D D D D D D
1st D D D D D D D D D D …
1 1 ↑ 1 1 1 1 1 1
parameter 9 8 7 6 5 4 3 2 1 0 FFF
5 4 3 2 1 0
F
D D D D D D 0000
. D D D D D D D D D D
X X X X X X …
. 1 1 ↑ X X X X X X X X X X
1 1 1 1 1 1 FFF
. 9 8 7 6 5 4 3 2 1 0
5 4 3 2 1 0 F

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D D D D D D 0000
D D D D D D D D D D
Nth n n n n n n …
1 1 ↑ n N N n n N N N n n
parameter 1 1 1 1 1 1 FFF
9 8 7 6 5 4 3 2 1 0
5 4 3 2 1 0 F
This command is used to transfer data from MCU to frame memory.
This command makes No Change to the other driver status. When this command is accepted,
the column register and the page register are reset to the Start Column/Start Page
position.The Start Column/Start Page positions are different in accordance with MADCTL
setting. (See Section 9.2.3 )

Description Then D[15:0] is stored in frame memory and the column register and the page register
incremented as in Table “MADCTL conditions”.
Sending nay other command can stop frame write.
See section 9.1.5 “Display Module Data Color Coding” for color coding, when there is used 8(IM0
is low– D[7:0] are used and D[17:8] are not used) or 16(IM0 is high – D[15:0] are used) data lines
for image data.
X=Don’t care
Restriction In all color modes, there is no restriction on length of parameters.
Status Availability
Normal Mode On, Idle Mode Off, Sleep Out Yes

Register Normal Mode On, Idle Mode On, Sleep Out Yes
Availability Partial Mode On, Idle Mode Off, Sleep Out Yes
Partial Mode On, Idle Mode On, Sleep Out Yes
Sleep In Yes
Status Default Value
Power On Sequence Contents of memory is set randomly
Default
S/W Reset Contents of memory is not cleared
H/W Reset Contents of memory is not cleared

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Flow Chart

8.2.1.22. Memory Read(2Eh)

2Eh RAMRD(Memory Read)

D R W D D D D D D D D
D17-8 HEX
C D R 7 6 5 4 3 2 1 0
Command 0 1 ↑ XX 0 0 1 0 1 1 1 0 2E

1st XX
1 1 ↑ XX X X X X X X X X
parameter XX

D D D D D D 0000
D D D D D D D D D D
2nd 1 1 1 1 1 1 …
1 1 ↑ 1 1 1 1 1 1 1 1 1 1
parameter 1 1 1 1 1 1 FFF
9 8 7 6 5 4 3 2 1 0
5 4 3 2 1 0 F
D D D D D D 0000
. D D D D D D D D D D
X X X X X X …
. 1 1 ↑ X X X X X X X X X X
1 1 1 1 1 1 FFF
. 9 8 7 6 5 4 3 2 1 0
5 4 3 2 1 0 F
D D D D D D 0000
D D D D D D D D D D
(N+1)th n n n n n n …
1 1 ↑ n n n n n n n n n n
parameter 1 1 1 1 1 1 FFF
9 8 7 6 5 4 3 2 1 0
5 4 3 2 1 0 F

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This command is used to transfer data from frame memory to MCU. See section 9.1.
This command makes No Change to the other driver status.
When this command is accepted, the column register and the page register are reset
to the Start Column/Start Page position.
The Start Column/Start positions are different in accordance with MADCTL setting(see

Description section 9.2.3).

Then D[15:0] is read back from the frame memory and the column register and the
page register incremented as in the Table “MADCTL conditions”.
Frame Read can be stopped by sending any other command.
See section 9.1.5 “Display Module Data Color Coding” for color coding (18 bit cases),
when there is used 8 or 6 data lines for image data.
X = Don’t care.
In all color modes, the Frame Read is always 18bit so there is no restriction on length of
Restriction
parameters. Note – Memory Read is only possible via the Parallel Interface.
Status Availability
Normal Mode On, Idle Mode Off, Sleep Out Yes

Register Normal Mode On, Idle Mode On, Sleep Out Yes
Availability Partial Mode On, Idle Mode Off, Sleep Out Yes
Partial Mode On, Idle Mode On, Sleep Out Yes
Sleep In Yes
Status Default Value
Power On Sequence Contents of memory is set randomly
Default
S/W Reset Contents of memory is not cleared
H/W Reset Contents of memory is not cleared

Flow Chart

New Vision Microelectronics Inc. Page 62

8.2.1.23. Partial Area(30h)

30h PLTAR(Partial Area)

D17-
DC RD WR D7 D6 D5 D4 D3 D2 D1 D0 HEX
8
Command 0 1 ↑ XX 0 0 1 1 0 0 0 0 30

1st
1 1 ↑ XX SR15 SR14 SR13 SR12 SR11 SR10 SR9 SR8 00
parameter

2nd
1 1 ↑ XX SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 00
parameter

3rd
1 1 ↑ XX ER15 ER14 ER13 ER12 ER11 ER10 ER9 ER8 01
parameter

4th
1 1 ↑ XX ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0 3F
parameter

This command defines the partial mode’s display area. There are 2 parameters associated
with this command, the first defines the Start Row (SR) and the second defines the End Row
(ER), as illustrated in the figures below. SR and ER refer to the Frame Memory Line Pointer.If
End Row Start Row When MADCTL B4=0:

Description

If End Row<Start Row when MADCTL B4=1:

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If End RowStart Row When Madctl B4=0:

If End Row=Start Row then the Partial Area will be one row deep.
X=Don’t care

Restriction SR[15..0] and ER[15..0] cannot be 0000h nor exceed 013Fh.

Status Availability
Normal Mode On, Idle Mode Off, Sleep Out Yes

Register Normal Mode On, Idle Mode On, Sleep Out Yes
Availability Partial Mode On, Idle Mode Off, Sleep Out Yes
Partial Mode On, Idle Mode On, Sleep Out Yes
Sleep In Yes

Status Default Value

Power On Sequence SR[15:0]=0000HEX ER[15:0]=013FHEX
Default
S/W Reset SR[15:0]=0000HEX ER[15:0]=013FHEX
H/W Reset SR[15:0]=0000HEX ER[15:0]=013FHEX

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1. To enter Partial Mode:

Legend

PLTAR
Command

SR[15...0］ Parameter

Display
ER[15...0］
Action

Mode
PTLON

Sequential
Partial Mode transfer

2. To exit Partial Mode:

Flow Chart
Partial Mode

DISPOFF
(Optional) To prevent Tearing
NORON Effect Image displayed

Partial Mode Off

RAMWR

DISPON

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8.2.1.24. Vertical Scrolling Definition(33h)

33h VSCRDEF(Vertical Scrolling Definition)

D R W D
D7 D6 D5 D4 D3 D2 D1 D0 HEX
C D R 17-8
Command 0 1 ↑ XX 0 0 1 1 0 0 1 1 33h

1st TFA TFA TFA TFA TFA TFA TFA

1 1 ↑ XX TFA9 00
parameter 15 14 13 12 11 10 8

2nd TFA TFA

1 1 ↑ XX TFA6 TFA5 TFA4 TFA3 TFA2 TFA1 00
parameter 7 0

3rd VSA VSA VSA VSA VSA VSA VSA VSA

1 1 ↑ XX 01
parameter 15 14 13 12 11 10 9 8

4th VSA VSA VSA VSA VSA VSA

1 1 ↑ XX VSA7 VSA6 40
parameter 5 4 3 2 1 0

5th BFA BFA BFA BFA BFA BFA

1 1 ↑ XX BFA9 BFA8 00
parameter 15 14 13 12 11 10

6th
1 1 ↑ XX BFA7 BFA6 BFA5 BFA4 BFA3 BFA2 BFA1 BFA0 00
parameter

This command defines the Vertical Scrolling Area of the display.

When MADCTL B4 = 0

The 1 & 2nd parameter TFA[15…0] describes the Top Fixed Area (in No. of lines from Top of
st

the Frame Memory and Display).

The 3 & 4th parameter VSA[15…0] describes the height of the Vertical Scrolling Area (in
rd

No. of lines of the Frame Memory [not the display] from the Vertical Scrolling Start Address).
The first line
read from Frame Memory appears immediately after the bottom most line of the Top Fixed

Area.The 5th and 6th parameter BFA[15…0] describes the Bottom Fixed Area (in No. of lines
from Bottom of the Frame Memory and Display).TFA, VSA and BFA refer to the Frame Memory
Line Pointer.

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When MADCTL B4 = 1

The 1st & 2nd parameter TFA[15…0] describes the Top Fixed Area (in No. of lines from
Bottom of the Frame Memory and Display).

The 3rd & 4th parameter VSA[15…0] describes the height of the Vertical Scrolling Area (in
No. of lines of the Frame Memory [not the display] from the Vertical Scrolling Start

Description Address). The first line read from Frame Memory appears immediately after the top most
line of the Top Fixed Area.

The 5th & 6th parameter BFA[15…0] describes the Bottom Fixed Area (in No. of lines from
Top of the Frame Memory and Display).

See also Section 9.2.2.2 for details of the Memory to Display mappings.
X=Don’t care

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The condition is TFA + VSA + BFA = 320, otherwise Scrolling mode is undefined.
Restriction In Vertical Scroll Mode, MADCTL B5 should be set to ‘0’, this only affects the Frame
Memory Write.

Status Default Value

Power On
Default TFA[15:0]=0000HEX VSA[15:0]=0140FHEX BFA[15:0]=0000FHEX
Sequence
S/W Reset TFA[15:0]=0000HEX VSA[15:0]=0140FHEX BFA[15:0]=0000FHEX
H/W Reset TFA[15:0]=0000HEX VSA[15:0]=0140FHEX BFA[15:0]=0000FHEX

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1.To enter Scroll Mode:

Flow
chart

Note 1
The Frame Memory Window size must be defined correctly otherwise undesirable image will
be displayed.

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2. Continuous Scroll:

Scroll Mode

Legend
CASET

1st & 2nd Parameter SC[15...0］ Command

Parameter
3rd & 4th Parameter EC[15...0］
Display

PASET Action

Mode
1st & 2nd Parameter SP[15...0］

Sequential
transfer
3rdt & 4th Parameter EP[15...0］

RAMWR

Scroll Image
Data

VSCRSADD

1st & 2nd Parameter VSA[15...0］

3. To leave Vertical Scroll Mode:

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Scroll Mode

(Optional) To prevent Tearing

DISPOFF Effect Image displayed

NORON/PTLON

Scroll Mode Off

RAMWR

DISPON
Note 2
Scroll Mode can be left by both the Normal Display Mode ON(13h) and Partial Mode on(12h)
commands.

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8.2.1.25. Tearing Effect Line Off(34h)

34h TEOFF(Tearing Effect Line Off)

DC RD WR D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX

Command 0 1 ↑ XX 0 0 1 1 0 1 0 0 34h

parameter NO PARAMETER

This command is used to turn OFF (Active Low) the Tearing Effect
Description output signal from the TE signal line.
X=Don’t care

Restriction This command has no effect when Tearing Effect output in already OFF.

Status Default Value

Default Power On Sequence Off

S/W Reset Off
H/W Reset Off

Flow Chart

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8.2.1.26. Tearing Effect Line ON(35h)

35h TEON(Tearing Effect Line ON)

DC RD WR D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 1 ↑ XX 0 0 1 1 0 1 0 1 35h
parameter 1 1 ↑ XX 0 0 0 0 0 0 0 M 00
This command is used to turn ON the Tearing Effect output signal from the TE signal line. This
output is not affected by changing MADTCTL bit B4. The Tearing Effect Line On has one parameter
that describes the mode of the Tearing Effect Output Line. (X = Don’t care).
When M=0:
The Tearing Effect Output line consists of V-blanking information only:

Description
When M=1:
The Tearing Effect Output line consists of V-blanking & H-blanking information:
tvdl tvdh

Vertical Time Scale

Note:

During Sleep In Mode with Tearing Effect Line On, Tearing Effect Output pin will be active Low.

X=Don’t care
Restriction This command has no effect when Tearing Effect output in already On.

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Status Default Value

Default Power On Sequence Off

S/W Reset Off
H/W Reset Off

Command
TE Line Output OFF
Parameter

TEON
Flow Chart

TE Line Output ON

8.2.1.27. Memory Data Access Control(36h)

36h MADCTL(Memory Data Access Control)

R W
DC D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX
D R
Command 0 1 ↑ XX 0 0 1 1 0 1 1 0 36h
parameter 1 1 ↑ XX my mx mv ml bgr mh 0 0 00
This command defines read/write scanning direction of frame memory.
This command makes No Change on the other driver status.

Bit Description Comment

my Page Address Order
Description mx Column Address Order
mv Page/Column Order
ml Line Address Order
bgr RGB/BGR Order
LCD Horizontal refresh
mh Horizontal refresh order(MH)
direction control
D[1] - Don’t care
D[0] - Don’t care

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- Bit D[7] – Page Address Order

‘0’ = Top to Bottom (When MADCTL B7 = ‘0’).
‘1’ = Bottom to Top (When MADCTL B7 = ‘1’).
- Bit D[6] – Column Address Order
‘0’ = Left to Right (When MADCTL B6 = ‘0’).
‘1’ = Right to Left (When MADCTL B6 = ‘1’).
- Bit D[5 ]– Page/Column Address Order
‘0’ = Normal Mode (When MADCTL B5 = ‘0’).
‘1’ = Reverse Mode (When MADCTL B5 = ‘1’).
Note: For Bits D[7] to D[5], also refer to Section 8.2.3 to memory write/read
directions.
- Bit D4 – Line Address Order
‘0’ = LCD Refresh Top to Bottom (When MADCTL B4 = ‘0’).
‘1’ = LCD Refresh Bottom to Top (When MADCTL B4 = ‘1’).
- Bit D3 – RGB / BGR Order
‘0’ = RGB (When MADCTL B3 = ‘0’).
‘1’ = BGR (When MADCTL B3= ‘1’).
- Bit D[2] – Set to ‘0’
- Bit D[1] – Set to ‘0’
- Bit D[0 ]– Set to ‘0’
X = Don’t care

Note: Top-Left(0,0)means a physical memory location.

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Restriction
Status Availability
Normal Mode On, Idle Mode Off, Sleep Out Yes

Flow Chart

8.2.1.28. Vertical Scrolling Start Address(37h)

37h VSCRSADD(Vertical Scrolling Start Address)

R W D1
DC D7 D6 D5 D4 D3 D2 D1 D0 HEX
D R 7-8
Command 0 1 ↑ XX 0 0 1 1 0 1 1 1 37h

1st parameter 1 1 ↑ XX VSP15 VSP14 VSP13 VSP12 VSP11 VSP10 VSP9 VSP8 00

2nd parameter 1 1 ↑ XX VSP7 VSP6 VSP5 VSP4 VSP3 VSP2 VSP1 VSP0 00

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This command is used together with Vertical Scrolling Definition (33h). These two commands
describe the scrolling area and the scrolling mode.
The Vertical Scrolling Start Address command has one parameter which describes
which line in the Frame Memory will be written as the first line after the last line of the
Top Fixed Area on the display as illustrated below.
When MADCTL B4 = 0
Example:
When Top Fixed Area = Bottom Fixed Area = 00, Vertical Scrolling Area = 320 and VSP= ‘3’.

Description
When MADCTL B4=1
Example:
When Top Fixed Area=Bottom Fixed Area=00,Vertical Scrolling Area=320and VSP=’3’.

Notes: When new Pointer position and Picture Data are sent, the result on the display will
happen at the next Panel Scan to avoid tearing effect.
VSP refers to the Vertical Scrolling Start Address..
X = Don’t care

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Since the value of the Vertical Scrolling Start Address is absolute (with reference to the Frame
Restriction Memory), it must not enter the fixed area (defined by Vertical Scrolling Definition 33h) –
otherwise undesirable image will be displayed on the Panel.
Status Availability
Normal Mode On, Idle Mode Off, Sleep Out Yes

Flow Chart See Vertical Scrolling Definition(33h) description.

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8.2.1.29. Idle Mode Off(38h)

38h IDMOFF(Idle Mode Off)

DC RD WR D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 1 ↑ XX 0 0 1 1 1 0 0 0 38h
parameter NO PARAMETER
This command is used to recover from idle mode on.
Description In the idle off mode, LCD can display maximum 262,144 colors. See also section 9.5.2.
X = Don’t care
Restriction This command has no effect when module is already in idle off mode.

Status Availability
Normal Mode On, Idle Mode Off, Sleep Out Yes

Flow Chart

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8.2.1.30. Idle Mode On(39h)

39h IDMON(Idle Mode On)

R W
DC D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX
D R
Command 0 1 ↑ XX 0 0 1 1 1 0 0 1 39h
parameter NO PARAMETER
This command is used to enter into idle mode on.
In the idle on mode, color expression is reduced. The primary and the secondary
colors using MSB of each R, G and B in the Frame Memory, 8 color depth data is
displayed.
Memory contents vs Display Color
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
Black 0XXXXX 0XXXXX 0XXXXX
Blue 0XXXXX 0XXXXX 1XXXXX
Description
Red 1XXXXX 0XXXXX 0XXXXX
Magenta 1XXXXX 0XXXXX 1XXXXX
Green 0XXXXX 1XXXXX 0XXXXX
Cyan 0XXXXX 1XXXXX 1XXXXX
Yellow 1XXXXX 1XXXXX 0XXXXX
White 1XXXXX 1XXXXX 1XXXXX
See also section 9.5.2.
X = Don’t care
Restriction This command has no effect when module is already in idle on mode.
Status Availability
Normal Mode On, Idle Mode Off, Sleep Out Yes

Register Normal Mode On, Idle Mode On, Sleep Out Yes
Availability Partial Mode On, Idle Mode Off, Sleep Out Yes
Partial Mode On, Idle Mode On, Sleep Out Yes
Sleep In Yes
Status Default Value
Power On Sequence Idle off Mode
Default
S/W Reset Idle off Mode
H/W Reset Idle off Mode

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Command
Display Inversion
On Mode Parameter

Display
Flow Chart IDMON
Action

Mode
Display Inversion
Off Mode
Sequential
transfer

8.2.1.31. Interface Pixel Format(3Ah)

3Ah PIXSET(Interface Pixel Format)

R W D17-
DC D7 D6 D5 D4 D3 D2 D1 D0 HEX
D R 8
Command 0 1 ↑ XX 0 0 1 1 1 0 1 0 3Ah

Parameter 1 1 ↑ XX X Dpi[2] Dpi[1] Dpi[0] X Dbi[2] Dbi[1] Dbi[0] 66

Dpi[2:0] is the pixel format select of RGB interface. Dbi[2:1] is the pixel format of MCU
interface.
If using RGB interface, serial interface must be selected.

Dpi[2:0] RGB interface Dbi[2:1] MCU interface

format format
0 0 0 reserved 0 0 0 reserved
Description
0 0 1 reserved 0 0 1 reserved
0 1 0 reserved 0 1 0 reserved
0 1 1 reserved 0 1 1 reserved
1 0 0 reserved 1 0 0 reserved
1 0 1 16 bits/pixel 1 0 1 16 bits/pixel
1 1 0 18 bits/pixel 1 1 0 18 bits/pixel
1 1 1 reserved 1 1 1 reserved
Restriction There is no visible effect until the Frame Memory is written to.

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Status Availability
Normal Mode On, Idle Mode Off, Sleep Out Yes

Register Normal Mode On, Idle Mode On, Sleep Out Yes
Availability Partial Mode On, Idle Mode Off, Sleep Out Yes
Partial Mode On, Idle Mode On, Sleep Out Yes
Sleep In Yes
Status Default Value
Power On Sequence 18Bit/Pixel
Default
S/W Reset No Change
H/W Reset 18Bit/Pixel
Example:

Flow Chart

8.2.1.32. Write_Memory_Continue（3Ch）
3Ch Write_Memory_Continue
D R W
D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX
C D R

Command 0 1 ↑ XX 0 0 1 1 1 1 0 0 3Ch

1st D1 D1 D1 D1 D1 D1 D1 D1 D1 000
1 1 ↑
Parameter [17..8] [7] [6] [5] [4] [3] [2] [1] [0] 3FF

Xth Dx Dx Dx Dx Dx Dx Dx Dx Dx 000
1 1 ↑
Parameter [17..8] [7] [6] [5] [4] [3] [2] [1] [0] 3FF

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N
th Dn Dn Dn Dn Dn Dn Dn Dn Dn 000
1 1 ↑
parameter [17..8] [7] [6] [5] [4] [3] [2] [1] [0] 3FF

This command transfers image data from the host processor to the display module’s frame
memory continuing from the pixel location following the previous write_memory_continue or
write_memory_start command.
If set_address_mode B5 = 0:
Data is written continuing from the pixel location after the write range of the previous
write_memory_start or write_memory_continue. The column register is then incremented and
pixels are written to the frame memory until the column register equals the End Column (EC)
value. The column register is then reset to SC and the page register is incremented. Pixels are
written to the frame memory until the page register equals the End Page (EP) value and the
column register equals the EC value, or the host processor sends another command. If the
number of pixels exceeds (EC – SC + 1) * (EP – SP + 1) the extra pixels are ignored.
If set_address_mode B5 = 1:
Data is written continuing from the pixel location after the write range of the previous
Description
write_memory_start or write_memory_continue. The page register is then incremented and
pixels are written to the frame memory until the page register equals the End Page (EP) value.
The page register is then reset to SP and the column register is incremented. Pixels are written
to the frame memory until the column register equals the End column (EC) value and the page
register equals the EP value, or the host processor sends another command. If the number of
pixels exceeds (EC – SC + 1) * (EP – SP + 1) the extra pixels are ignored.
Sending any other command can stop frame Write.
Frame Memory Access and Interface setting (B3h), WEMODE=0
When the transfer number of data exceeds (EC-SC+1)*(EP-SP+1), the exceeding data will be
ignored.
Frame Memory Access and Interface setting (B3h), WEMODE=1
When the transfer number of data exceeds (EC-SC+1)*(EP-SP+1), the column and page number will be
reset, and the exceeding data will be written into the following column and page.

A write_memory_start should follow a set_column_address, set_page_address or

Restriction set_address_mode to define the write address. Otherwise, data written with
write_memory_continue is written to undefined addresses.

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Status Default Value

Power On Sequence Random data
Default
S/W Reset No change
H/W Reset No change

Flow Chart

8.2.1.33. Read_Memory_Continue（3Eh）

3Eh Read_Memory_Continue
D R W D1
D7 D6 D5 D4 D3 D2 D1 D0 HEX
C D R 7-8
Command 0 1 ↑ XX 0 0 1 1 1 1 1 0 3Eh

D1
1st D1 D1 D1 D1 D1 D1 D1 D1 000
1 1 ↑ [17..
Parameter [7] [6] [5] [4] [3] [2] [1] [0] 3FF
8]
Dx
Xth Dx Dx Dx Dx Dx Dx Dx Dx 000
1 1 ↑ [17..
Parameter [7] [6] [5] [4] [3] [2] [1] [0] 3FF
8]

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Dn
Nth Dn Dn Dn Dn Dn Dn Dn Dn 000
1 1 ↑ [17..
[7] [6] [5] [4] [3] [2] [1] [0] 3FF
parameter 8]

This command transfers image data from the display module’s frame memory to the host
processor continuing from the location following the previous read_memory_continue (3Eh) or
read_memory_start (2Eh) command.
If set_address_mode B5 = 0:
Pixels are read continuing from the pixel location after the read range of the previous
read_memory_start or read_memory_continue. The column register is then incremented and
pixels are read from the frame memory until the column register equals the End Column (EC)
value. The column register is then reset to SC and the page register is incremented. Pixels
are read from the frame memory until the page register equals the End Page (EP) value and
Description
the column register equals the EC value, or the host processor sends another command.
If set_address_mode B5 = 1:
Pixels are read continuing from the pixel location after the read range of the previous
read_memory_start or read_memory_continue. The page register is then incremented and
pixels are read from the frame memory until the page register equals the End Page (EP)
value. The page register is then reset to SP and the column register is incremented. Pixels
are read from the frame memory until the column register equals the End Column (EC) value
and the page register equals the EP value, or the host processor sends another command.
This command makes no change to the other driver status.
A read_memory_start should follow a set_column_address, set_page_address or
Restriction set_address_mode to define the read location. Otherwise, data read with
read_memory_continue is undefined.

Status Default Value

Default Power On Sequence Random data

S/W Reset No change
H/W Reset No change

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Flow Chart

8.2.1.34. Set_Tear_Scanline（44h）
44h Set Tear Scanline
R W D17
DC D7 D6 D5 D4 D3 D2 D1 D0 HEX
D R -8
Command 0 1 ↑ XX 0 1 0 0 0 1 0 0 44h

1st STS
1 1 ↑ XX X X X X X X X 00
Parameter [8]

2nd STS STS STS STS STS STS STS STS

1 1 ↑ XX 00
Parameter [7] [6] [5] [4] [3] [2] [1] [0]

This command turns on the display Tearing Effect output signal on the TE signal line when
the display reaches line STS.
The TE signal is not affected by changing set_address_mode bit B4. The Tearing Effect Line
On has one parameter that describes the Tearing Effect Output Line mode.
Descriptio
n

Note that set_tear_scanline with STS=0 is equivalent to set_tear_on with M=0.

The Tearing Effect Output line shall be active low when the display module is in Sleep mode.
Restriction -

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Status Default Value

Default Power On Sequence STS [8:0]=0000h
S/W Reset STS [8:0]=0000h
H/W Reset STS [8:0]=0000h

Flow Chart

8.2.1.35. Get_Scanline（45h）
45h Get_Scanline
D R W D1
D7 D6 D5 D4 D3 D2 D1 D0 HEX
C D R 7-8
Command 0 1 ↑ XX 0 1 0 0 0 1 0 1 45h

1st
1 1 ↑ XX X X X X X X X X X
Parameter

2nd GTS GTS

1 1 ↑ XX 0 0 0 0 0 0 00
Parameter [9] [8]

3rd GTS GTS GTS GTS GTS GTS GTS GTS

00
Parameter [7] [6] [5] [4] [3] [2] [1] [0]

The display returns the current scan line, GTS, used to update the display device. The total
number of scan lines on a display device is defined as VSYNC + VBP + VACT + VFP. The
Description
first scan line is defined as the first line of V-Sync and is denoted as Line 0.
When in Sleep Mode, the value returned by get_scanline is undefined.
Restriction None

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Status Default Value

Default Power On Sequence GTS [9:0]=0000h

S/W Reset GTS [9:0]=0000h
H/W Reset GTS [9:0]=0000h

Flow Chart

8.2.1.36. Write CTRL Display (53h)

53h WRCTRLD (Write Control Display)

D R W D1
D7 D6 D5 D4 D3 D2 D1 D0 HEX
C D R 7-8
Command 0 1 ↑ XX 0 1 0 1 0 0 1 1 53h
Parameter 1 1 ↑ XX X 0 0 0 0 BL 0 0 00

This command is use to control backlight LED on or off, default is high. When bl=”1” and
Description
BC_CTRL output high.

Restriction None

Default Value
Status
BCTRL DD BL
Default
Power On Sequence 1’b0 1’b0 1’b0
S/W Reset 1’b0 1’b0 1’b0
H/W Reset 1’b0 1’b0 1’b0

Flow Chart

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8.2.1.37. Read ID4 (D3h)

D3h RDID4(Read ID4)

R W D1
DC D7 D6 D5 D4 D3 D2 D1 D0 HEX
D R 7-8
Command 0 1 ↑ XX 1 1 0 1 0 0 1 1 D3h
1st
1 1 ↑ XX X X X X X X X X X
Parameter
2nd
1 1 ↑ XX 0 0 0 0 0 0 0 0 00
Parameter
3rd
0 0 1 1 0 0 0 1 31
Parameter
4th
0 0 1 0 1 0 0 1 29
Parameter
Read IC device code.
Descriptio The 1st parameter is dummy read period.
n The 2nd parameter means the IC version.
The 3rd and 4th parameter mean the IC model name.
Restriction EXTC should be high to enable this command

Status Default Value

Default Power On Sequence 24’h009341h

S/W Reset 24’h009341h
H/W Reset 24’h009341h

8.2.1.38. Read ID1(DAh)

DAH RDID1(Read ID1)

D R W D1
D7 D6 D5 D4 D3 D2 D1 D0 HEX
C D R 7-8

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Command 0 1 ↑ XX 1 1 0 1 1 0 1 0 DAh

1st
1 1 ↑ XX X X X X X X X X X
Parameter

2nd
1 1 ↑ XX Id4[7] Id4[6] Id4[5] Id4[4] Id4[3] Id4[2] Id4[1] Id4[0] 00
Parameter
This read byte identifies the LCD module’s manufacturer ID and it is specified by User
The 1st parameter is dummy data.
Description
The 2nd parameter is LCD module’s manufacturer ID.
X = Don’t care
Restriction

Default Value Default Value

Status
(Before MTP program) （After MTP program）
Default
Power On Sequence 8’h00h MTP value
S/W Reset 8’h00h MTP value
H/W Reset 8’h00h MTP value

Flow Chart

8.2.1.39. Read ID2 (DBh)

DBh RDID2(Read ID2)

D R W D1
D7 D6 D5 D4 D3 D2 D1 D1 HEX
C D R 7-8
Command 0 1 ↑ XX 1 1 0 1 1 0 1 1 DBh

1st 1 1 XX X X X X X X X X XX
↑
Parameter

2
nd
1 1 ↑ XX Id5[7] Id5[6] Id5[5] Id5[4] Id5[3] Id5[2] Id5[1] Id5[0] 00
Parameter

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This read byte is used to track the LCD module/driver version. It is defined by display
supplier (with User’s agreement) and changes each time a revision is made to the display,
material or construction specifications.
The 1st parameter is dummy data.
Description
The 2nd parameter is LCD module/driver version ID and the ID parameter range is from 80h
to FFh.
The ID2 can be programmed by MTP function.
X = Don’t care
Restriction
Status Availability
Normal Mode On, Idle Mode Off, Sleep Out Yes

Register Normal Mode On, Idle Mode On, Sleep Out Yes
Availability Partial Mode On, Idle Mode Off, Sleep Out Yes
Partial Mode On, Idle Mode On, Sleep Out Yes
Sleep In Yes

Default Value Default Value

Status
(Before MTP program) （After MTP program）
Default
Power On Sequence 8’h80h MTP value
S/W Reset 8’h80h MTP value
H/W Reset 8’h80h MTP value

Command
RDID2(DBh)
Host Parameter

Driver Display
Flow Chart 1st parameter Dummy Read Action
2nd parameter: Send ID2[7:0]
Mode

Sequential
transfer

8.2.1.40. Read ID3(DCh)

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DCH RDID3(Read ID3)

D R W D1
D7 D6 D5 D4 D3 D2 D1 D1 HEX
C D R 7-8
Command 0 1 ↑ XX 1 1 0 1 1 1 0 0 DCh

1st 1 1 XX X X X X X X X X X
↑
Parameter

2
nd
1 1 ↑ XX Id6[7] Id6[6] Id6[5] Id6[4] Id6[3] Id6[2] Id6[1] Id6[0] 00
Parameter
read byte identifies the LCD module/driver and It is specified by User.
The 1st parameter is dummy data.
Description The 2nd parameter is LCD module/driver ID.
The ID3 can be programmed by MTP function.
X = Don’t care
Restriction

Default Value Default Value

Status
(Before MTP program) （After MTP program）
Default
Power On Sequence 8’h00h MTP value
S/W Reset 8’h00h MTP value
H/W Reset 8’h00h MTP value

Flow Chart

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8.2.2. Description of level2 command (extended command)

Note: Extended commands in the table below are only valid when send “06H” command followed by
“07H”. To exit extended commands, send “faH” command followed by “fbH”.

8.2.2.1. RGB interface control(B0h)

38h IFMODE(interface mode control)
R W D D
DC D7 D6 D5 D3 D2 D1 D0 HEX
D R 17-8 4
Command 0 1 ↑ XX 1 0 1 1 0 0 0 0 B0

parameter Bypas
Rcm[1 Rcm[0
1 1 ↑ XX s_mod 0 vspl hspl dpl epl 40
] ]
e

Set the operation status of display interface. The setting becomes effective as soon
as the commd is seted.
epl: DE polarity.
0: High enable for RGB interface;
1: Low enable for RGB interface.
dpl: Dotclock polarity.
0: data fetched at the rising time;
1: data fetched at the falling time.
hspl: HSYNC polarity.
Descriptio
0: Low level sync clock;
n
1: High level sync clock.
vspl: VSYNC polarity.
0: Low level sync clock;
1: High level sync clock.
rcm[1:0]: RGB interface selection. refer to the RGB interface setion.
bypass_mode: Select the display data path whether memory or direct to shift register
when RGB interface is used.
0: through memory;
1: direct to shift register.

Restriction This command has no effect when module is already in idle off mode.

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Register
Availability Status Availability
Normal Mode On, Idle Mode Off, Sleep Out Yes
Normal Mode On, Idle Mode On, Sleep Out Yes
Partial Mode On, Idle Mode Off, Sleep Out Yes
Partial Mode On, Idle Mode On, Sleep Out Yes
Sleep In Yes

Status Default Value

Default Power On Sequence 40h
S/W Reset 40h
H/W Reset 40h

8.2.2.2. Frame rate control (B1h)

38h FRMCTR1 (Frame rate control)

R W
DC D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX
D R
Command 0 1 ↑ XX 1 0 1 1 0 0 0 1 B1

1st divi divi

1 1 ↑ XX 0 0 0 0 0 0 00
parameter [1] [0]

2nd rtni rtni rtni rtni rtni

1 1 ↑ XX 0 0 0 [4] [3] [2] [1] [0] 12
parameter
RTNI[4:0]: Sets 1H (line) period when synchronizing NV3029C’s display operation with internal
clock signal.

RTNI[4:0] Clock per line RTNI[4:0] Clock per line

5’h10 16 clocks 5’h18 24 clocks
5’h11 17 clocks 5’h19 25 clocks
Description 5’h12 18 clocks 5’h1A 26 clocks
5’h13 19 clocks 5’h1B 27 clocks
5’h14 20 clocks 5’h1C 28 clocks
5’h15 21 clocks 5’h1D 29 clocks
5’h16 22 clocks 5’h1E 30 clocks
5’h17 23 clocks 5’h1F 31 clocks
clocks per line (internal clock operation: 1 clock = 1 OSC)

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DIVI[1:0]: set the division ratio of the internal oscillation clock, when NV3029C’s display
operation is synchronized with internal oscillation clock. NV3029C’s internal operation is
synchronized with the frequency divided internal oscillation clock. When changing the DIVI[1:0]
setting, the width of the reference clock for liquid crystal panel control signals is changed. The
frame frequency can be adjusted by setting RTNI[4:0] and DIVI[1:0].

DIVI[1:0] Division Ratio Internal Operation Clock Unit

2’h0 1/1 One OSC clock
2’h1 1/2 2 OSC clock
2’h2 1/4 4 OSC clock
2’h3 1/8 8 OSC clock
OSC: internal oscillation clock
Division ratio of the internal operation clock frequency

The frame frequency can be adjusted setting (RTNI and DIVI bits), When changing the number of lines to
drive the liquid crystal panel, adjust the frame frequency too. For details, see” Frame-Frequency
Adjustment Function”. The setting in DIVI[1:0] is disabled in RGB interface operation.
Frame Frequency Calculation

Internal Clock Frequency (fosc) is determined by register (C6h).

C6h Internal Clock frequency(KHz)

3 310
4 340
5 370
Only For Internal use, setting
Other setting
disabled
Note: For safe concern, Register C6h default value is 0003h. In this setting, The Frame Rate is about
64Hz; If C6h setting is 0005h, The Frame Rate is about 76Hz; If C6h setting is 0004h, The Frame Rate is
about 70Hz.

Restriction This command has no effect when module is already in idle off mode.

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Default Value
Status
Divi[1:0] Rtni[4:0]
Default Power On Sequence 00h 12h
S/W Reset 00h 12h
H/W Reset 00h 12h

8.2.2.3. Frame rate control 2(B2h)

38h FRMCTR2(Frame rate control 2)

R W D17-
DC D7 D6 D5 D4 D3 D2 D1 D0 HEX
D R 8
Command 0 1 ↑ XX 1 0 1 1 0 0 1 0 B2
1st div
dive
parameter 1 1 ↑ XX 0 0 0 0 0 0 e 00
[0]
[1]
2nd
1 1 ↑ XX 0 0 0 0 0 0 0 0 00
parameter
DIVE[1:0]: DIVE[1:0] sets the division ratio of DOTCLK, when the NV3029C
performs display operation via RGB interface. The NV3029C’s internal operation is
synchronized with the frequency divided DOTCLK in RGB interface operation.

8-bit,3
Descriptio DIVE Division 18-bit,1transfer DOTCLK= transfer DOTCLK=5
n [1:0] Ratio RGB interface 5MHZ RGB MHZ
interface
Setting Setting Setting
2’h0 - -
disabled disabled disabled
12DOTCLK
2’h1 1/4 4DOTCLKS 0.8us 0.8us
S

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24DOTCLK
2’h2 1/8 8DOTCLKS 1.6uS 1.6us
S
48DOTCLK
2’h3 1/161 16DOTCLKS 3.2uS 3.2us
S
Internal operation clock unit (DOTCLK)

Restriction This command has no effect when module is already in idle off mode.
Status Availability
Normal Mode On, Idle Mode Off, Sleep Out Yes

8.2.2.4. Display inversion(B4h)

38h INVTR(Display inversion control)

R D17- HE
DC WR D7 D6 D5 D4 D3 D2 D1 D0
D 8 X
Command 0 1 ↑ XX 1 0 1 1 0 1 0 0 B4
parameter 1 1 ↑ XX 0 0 0 0 0 nla nlb nlc 02
Display inversion mode set.
nla: inversion setting in normal mode;
Descriptio nlb: inversion setting in idle mode;
n nlc: inversion setting in partial mode.
0: line inversion;
1: frame inversion.
Restriction

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Status Availability
Normal Mode On, Idle Mode Off, Sleep Out Yes

Register Normal Mode On, Idle Mode On, Sleep Out Yes
Availability Partial Mode On, Idle Mode Off, Sleep Out Yes
Partial Mode On, Idle Mode On, Sleep Out Yes
Sleep In Yes
Default Value
Status
nla nlb nlc
Default Power On Sequence 1’b0 1’b1 1’b0
S/W Reset 1’b0 1’b1 1’b0

8.2.2.5. Blanking porch control(B5h)

38h PRCTR(Blanking porch)

R D17-
DC WR D7 D6 D5 D4 D3 D2 D1 D0 HEX
D 8
Command 0 1 ↑ XX 1 0 1 1 0 1 0 1 B5
1st vfp vfp vfp vfp vfp vfp vfp
1 1 ↑ XX 0 02
parameter [6] [5] [4] [3] [2] [1] [0]
2nd vbp vbp vbp vbp vbp vbp vbp
1 1 ↑ XX 0 02
parameter [6] [5] [4] [3] [2] [1] [0]
3rd hfp hfp hfp hfp hfp
1 1 ↑ XX 0 0 0 0a
parameter [4] [3] [2] [1] [0]
4th hbp hbp hbp hbp hbp
1 1 ↑ XX 0 0 0 14
parameter [4] [3] [2] [1] [0]
Descriptio Vfp[6:0]/vbp[6:0]: vfp[6:0] and vbp[6:0] set the line number vertical front and back porch period
n respectively.

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hfp[6:0]/hbp[6:0]: hfp[6:0] and hbp[6:0] set the line number horizontal front and back porch period
respectively.

Restriction

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Status Availability
Normal Mode On, Idle Mode Off, Sleep Out Yes

Register Normal Mode On, Idle Mode On, Sleep Out Yes
Availability Partial Mode On, Idle Mode Off, Sleep Out Yes
Partial Mode On, Idle Mode On, Sleep Out Yes
Sleep In Yes
Default Value
Status
Vfp[6:0] Vbp[6:0] Hfp[4:0] Hbp[4:0]
Default Power On Sequence 7’h02 7’h02 5’h0a 5’h14
S/W Reset 7’h02 7’h02 5’h0a 5’h14

8.2.2.6. Display function control(B6h)

38h DISCTRL(Display function control)

R D17- HE
DC WR D7 D6 D5 D4 D3 D2 D1 D0
D 8 X
Command 0 1 ↑ XX 1 0 1 1 0 1 1 0 B6
1st ptg ptg pts pts
1 1 ↑ XX 0 0 0 0 0A
parameter [1] [0] [1] [0]
2nd isc isc isc isc
1 1 ↑ XX rev gs ss sm 82
parameter [3] [2] [1] [0]
3rd nl nl nl nl nl nl
1 1 ↑ XX 0 0 27
parameter [5] [4] [3] [2] [1] [0]
4th
1 1 ↑ XX 0 0 0 0 0 0 0 0 00
parameter

Ptg[1:0]: set the scan mode in non-display area.

Descriptio
n

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Pts[1:0]: determine source and Vcom output in non-display area in the partial display mode.

Source output in non-display area Vcom output in non-display area

Pts[1:0] Negative
Positive polarity Negative polarity Positive polarity
polarity
0 0 V63 V0 Vcoml Vcomh
0 1 V0 V63 Vcoml Vcomh
1 0 Vssa Vssa Vsa Vssa
1 1 Hi-z Hi-z Vssa Vssa

ss: selects the shift direction of outputs of the source driver.

0: Source output S1- S720;
1: Source output S720 - S1.

GS: Sets the direction of scan by the gate driver in the range determined by SCN[5:0] and
NL[5:0].
When GS = 0, the scan direction is from G1 to G320.
When GS = 1, the scan direction is from G320 to G1

Rev: select the liquid crystal type is the white type or the normal black type.
0: normal black;
1: normal white.

ISC[3:0]: Specify the scan cycle of the gate driver when the PTG[1:0] are set to “10” in non-
display area. The scan cycle can be set in odd number of frames from 0 to 31. In this case,
polarity is inverted every scan cycle.

ISC Scan cycle (Fflm)=60HZ

0000 0 frame -
0001 3 frame 50ms
0010 5 frame 84ms
0011 7 frame 117ms
0100 9 frame 150ms
0101 11 frame 184ms
0110 13frame 217ms
0111 15frame 251ms

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1000 17frame 284ms

1001 19frame 317ms
1010 21frame 351ms
1011 23 frame 384ms
1100 25frame 418ms
1101 27frame 451ms
1110 29 frame 484ms
1111 31frame 518ms

Sm: scan mode selection.

When NL = 6’1d, SCN = 6’h02, the gate scan sequence shows below:
GS = 0 GS = 1
SM = 0 G17,18…255,256 G304,303…66,65
SM = 1 G18,17….256,255 G303,304…65,66
SM = 2 G33,35…317,319,2,4…190,192 G288,286…4,2,319,317…13
1,129
SM = 3 G35,33…319,317,4,2…192,190 G286,288…2,4,317,319…12
9,131
SM = 4 G17,18…255,256 G304,303…66,65
SM = 5 G18,17….256,255 G303,304…65,66
SM = 6 G33,35…269,271,34,36…270,2 G288,286…52,50,287,285…
72 51,49
SM = 7 G35,33…271,269,36,34…272,2 G286,288…50,52,285,287…
70 49,51

NL[5:0]: Set the number of lines to drive the LCD at an interval of 8 lines. The GRAM address
mapping is not affected by the number of lines set by this instruction. The number of lines
must be the same or more than the number of lines necessary for the size of the liquid crystal
panel.

NL[5:0] Number of lines NL[5:0] Number of lines NL[5:0] Number of lines

Setting Setting
6’h00 Setting inhibited 6’h0E 6’h1C
inhibited inhibited
Setting
6’h01 Setting inhibited 6’h0F 6’h1D 240(lines)
inhibited
6’h02 Setting inhibited 6’h10 Setting 6’h1E 248

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inhibited
Setting
6’h03 Setting inhibited 6’h11 6’h1F 256
inhibited
Setting
6’h04 Setting inhibited 6’h12 6’h20 264
inhibited
Setting
6’h05 Setting inhibited 6’h13 6’h21 272
inhibited
Setting
6’h06 Setting inhibited 6’h14 6’h22 280
inhibited
6’h07 Setting inhibited 6’h15 176lines 6’h23 288
Setting
6’h08 Setting inhibited 6’h16 6’h24 296
inhibited
Setting
6’h09 Setting inhibited 6’h17 6’h25 304
inhibited
Setting
6’h0A Setting inhibited 6’h18 6’h26 312
inhibited
Setting
6’h0B Setting inhibited 6’h19 6’h27 320
inhibited
Setting Setting
6’h0C Setting inhibited 6’h1A 6’h28-6’h3F
inhibited inhibited
Setting
6’h0D Setting inhibited 6’h1B
inhibited
liquid crystal drive lines
Restriction

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Status Default Value

ptg[1:0 pts[1:0 rev gs ss sm isc[3:0] nl[5:0]
] ]
Default
Power On 2’b10 2’b10 1’b1 1’b0 1’b0 1’b0 4’h0010 6’h27
Sequence
S/W Reset 2’b10 2’b10 1’b1 1’b0 1’b0 1’b0 4’h0010 6’h27
H/W Reset 2’b10 2’b10 1’b1 1’b0 1’b0 1’b0 4’h0010 6’h27

8.2.2.7. Entry mode set(B7h)

38h ETMOD(Entry mode set)

D R D17-
WR D7 D6 D5 D4 D3 D2 D1 D0 HEX
C D 8
Command 0 1 ↑ XX 1 0 1 1 0 1 1 1 B7
parameter 1 1 ↑ XX 0 0 0 0 0 gon dte 0 06
Gon/dte: set output level of gate driver.

gon dte G1-G320 gate output

Description 0 0 Vgh
0 1 Vgh
1 0 Vgl
1 1 Normal display
Restriction
Status Availability
Normal Mode On, Idle Mode Off, Sleep Out Yes

Register Normal Mode On, Idle Mode On, Sleep Out Yes
Availability Partial Mode On, Idle Mode Off, Sleep Out Yes
Partial Mode On, Idle Mode On, Sleep Out Yes
Sleep In Yes
Default Value
Status
gon Dte
Default Power On Sequence 1’b1 1’b1
S/W Reset 1’b1 1’b1

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8.2.2.8. Backlight control 1(BEh)

38h Backlight control1

D R D15- H
WR D7 D6 D5 D4 D3 D2 D1 D0
C D 8 EX
Command 0 1 ↑ XX 1 0 1 1 1 1 1 0 BE
pwm pwm pwm pwm pwm pwm pwm
Pwm_
parameter 1 1 ↑ XX _ _ _ _ _ _ _ 06
div[7]
div[7] div[7] div[7] div[7] div[7] div[7] div[7]
Pwm_div[7:0]: pwm_out frequency output control.

Pwm_div[7:0] Fpwm_out
8’h0 46.8KHz
8’h1 23.4KHz
8’h2 11.7KHz
Description 8’h3 5.85KHz
… …
8’hfb 186Hz
8’hfc 93.2Hz
8’hfd 46.6Hz
8’hfe 23.3Hz
8’hff 11.6Hz
Restriction
Status Availability
Normal Mode On, Idle Mode Off, Sleep Out Yes

Register Normal Mode On, Idle Mode On, Sleep Out Yes
Availability Partial Mode On, Idle Mode Off, Sleep Out Yes
Partial Mode On, Idle Mode On, Sleep Out Yes
Sleep In Yes

Status Default Value

Power On Sequence 8’h04

Default
S/W Reset No change
H/W Reset 8’h04

8.2.2.9. Backlight control 2(Bfh)

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38h Backlight control2

D R D17-
WR D7 D6 D5 D4 D3 D2 D1 D0 HEX
C D 8
Command 0 1 ↑ XX 1 0 1 1 1 1 1 1 BF
ledp
ledonp
parameter 1 1 ↑ XX ledonr wmp 00
ol
ol
Ledpwmpol: the bit is used to set the polarity of LEDPWM signal.
bl ledpwmpol Pwm_out
0 0 0
0 1 1
1 0 Original pwm_out
1 1 Inversed pwm_out
Ledonpol: the bit is used to control ledon.
bl ledpwmpol ledon
Description
0 0 0
0 1 1
1 0 ledonr
1 1 Inversed ledonr
Ledonr: the bit is used to control ledon
Ledonr Description
0 Low
1 high
Restriction
Status Availability
Normal Mode On, Idle Mode Off, Sleep Out Yes

Register Normal Mode On, Idle Mode On, Sleep Out Yes
Availability Partial Mode On, Idle Mode Off, Sleep Out Yes
Partial Mode On, Idle Mode On, Sleep Out Yes
Sleep In Yes

Status Default Value

Power On Sequence
Default
S/W Reset No change
H/W Reset

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8.2.2.10. Power control 1(C0h)

38h PWRCTRL1(power control 1)

D R D17- HE
WR D7 D6 D5 D4 D3 D2 D1 D0
C D 8 X
Command 0 1 ↑ XX 1 1 0 0 0 0 0 0 C0
parameter 1 1 ↑ XX 0 0 Vrh[5] Vrh[4] Vrh[3] Vrh[2] Vrh[1] Vrh[0] 10
Vrh[5:0]: set the vreg1out level, which is the reference voltage of Vcom and grayscale voltage.

Vrh[5:0] Vreg1out (V) Vrh[5:0] Vreg1out

Bandgap VCI
6’b000000 --- 6’b100000 ---
6’b000001 3 6’b100001 2.95
6’b000010 3.1 6’b100010 3.01
6’b000011 3.2 6’b100011 3.06
6’b000100 3.3 6’b100100 3.12
6’b000101 3.4 6’b100101 3.18
6’b000110 3.5 6’b100110 3.25
6’b000111 3.6 6’b100111 3.31
6’b001000 3.7 6’b101000 3.38
6’b001001 3.8 6’b101001 3.45
Description
6’b001010 3.9 6’b101010 3.53
6’b001011 4.0 6’b101011 3.61
6’b001100 4.1 6’b101100 3.69
6’b001101 4.2 6’b101101 3.77
6’b001110 4.3 6’b101110 3.86
6’b001111 4.4 6’b101111 3.96
6’b010000 4.5 6’b110000 4.06
6’b010001 4.6 6’b110001 4.16
6’b010010 4.7 6’b110010 4.27
6’b010011 4.8 6’b110011 4.39
6’b010100 4.9 6’b110100 4.51
6’b010101 5.0 6’b110101 4.64
6’b010110 5.1 6’b110110 4.77
6’b010111 5.2 6’b110111 4.92

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6’b011000 5.3 6’b111000 5.07

6’b011001 5.4 6’b111001 5.23
6’b011010 5.5 6’b111010 5.41
6’b011011 5.6 6’b111011 5.59
6’b011100 5.7 6’b111100 5.79
6’b011101 5.8 6’b111101 6.01
6’b011110 5.9 6’b111110 6.24
6’b011111 6 6’b111111 6.49
Note: Make sure that VRH setting restriction: VREG1OUT≤(DDVDH-0.3).

Restriction
Status Availability
Normal Mode On, Idle Mode Off, Sleep Out Yes

Register Normal Mode On, Idle Mode On, Sleep Out Yes
Availability Partial Mode On, Idle Mode Off, Sleep Out Yes
Partial Mode On, Idle Mode On, Sleep Out Yes
Sleep In Yes

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Status Default Value

Power On Sequence 10H

Default
S/W Reset No change
H/W Reset 10H

8.2.2.11. Power control 2(C1h)

38h PWRCTRL2(power control 2)

D R D17- H
WR D7 D6 D5 D4 D3 D2 D1 D0
C D 8 EX
Command 0 1 ↑ XX 1 1 0 0 0 0 0 1 C1
Parameter N3v_m N3v_e Pump P5v_cm P5v_e
1 1 ↑ XX 0 0 0 00
1st ode n 5v_sel p_en n

Parameter N20v_ N20v_ P20v_ P20v_

1 1 ↑ XX 0 N20sel 0 P20sel 00
2nd md[1] md[0] md[1] md[0]

Parameter Com_ Com_ Com_ En_vre Gamm

1 1 ↑ XX 0 0 0 00
3rd drv_en en2 en1 g1 a_en

P5v_en: enable DDVDH (2*VCI)when set p5v_en to “1”.

P5v_cmp_en: when p5v_cmp_en=0, comparator in 5v pump is off. when p5v_cmp_en=1, the
comparator is on.
Pump5v_sel: enable 3*VCI for DDVDH.
N3v_en: enable VCL when set n3v_en to “1”.
P20sel, n20sel: enable VGH and VGL when set them to “1”.
P20v_md[1:0], n20v_md[1:0]: specify VGH and VGL voltage level.
Description N3v_mode: VCL = -VDD when set n3v_mode to “0”; VCL = -VCI when set n3v_mode to “1”.
Gamma_en: enable grayscale amplifier when set gamma_en to “1”.
En_vreg1: enable vreg1out OP when set en_vreg1 to “1”, and disable vreg1out OP when set it
to “0”.
Com_en1: enable Vcoml when set com_en1 to “1”.
Com_en2: enable vcomh when set com_en2 to “1”.
Com_drv_en: enable Vcom output when set com_drv_en to “1”.

Restriction

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Status Default Value

Default Power On Sequence 00H
S/W Reset No change
H/W Reset 00H

8.2.2.12. 8.2.2.10 Power control 3(CAh)

38h PWRCTRL3(power control 3)

R W
DC D15-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX
D R
Command 0 1 ↑ XX 1 1 0 0 1 0 1 0 ca
Dc0[
Parameter 1 1 ↑ XX 0 Dc1[2] Dc1[1] Dc1[0] 0 Dc0[2] Dc0[1] 23
0]

DC0[2:0]: Sets the step-up factor of the step-up circuit 1. To improve the drivability of the step-up
circuit 1 and the display quality, use a higher step-up operation frequency, inevitably with the
increase of power consumption. make the trade-off between the quality of display and power
consumption.
DC0[2:0] Step-up circuit 1: step-up frequency (fDCDC1)
000 fosc
001 fosc/2
Description
010 fosc/4
011 fosc/8
100 fosc/16
101 Setting inhibited
110 Setting inhibited
111 Setting inhibited
step-up frequency (Step-up Circuit 1)

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Note: Make sure to set DC0 and DC1 so that fdcdc2 is maintained.

DC1[2:0]: Sets the step-up factor of the step-up circuit 2. To improve the drivability of the step-up
circuit 2 and the display quality, use a higher step-up operation frequency, inevitably with the
increase of the power consumption. make the trade-off between the quality of display and power
consumption.

DC1[2:0] Step-up circuit 2: step-up frequency (fDCDC1)

000 fosc/16
001 fosc/32
010 fosc/64
011 fosc/128
100 fosc/256
101 Setting inhibited
110 Setting inhibited
111 Setting inhibited
step-up frequency (Step-up Circuit 2)
Note: Make sure to set DC0 and DC1 so that fdcdc2 is maintained.

Restriction
Status Availability
Normal Mode On, Idle Mode Off, Sleep Out Yes

Register Normal Mode On, Idle Mode On, Sleep Out Yes
Availability Partial Mode On, Idle Mode Off, Sleep Out Yes
Partial Mode On, Idle Mode On, Sleep Out Yes
Sleep In Yes
Status Default Value

Power On Sequence 23H

Default
S/W Reset No change
H/W Reset 23H

8.2.2.13. Vcom control 1-4(CCh, CDh, CEh, CFh)

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8h Vcom control 1-4

R D17-
DC WR D7 D6 D5 D4 D3 D2 D1 D0 HEX
D 8
Command 0 1 ↑ XX 1 1 0 0 1 1 0 0 cc
Vcm Vcm0[ Vcm0[ Vcm0[ Vcm0[0
Parameter 1 1 ↑ XX 0 Vcm0[1] 31
0[5] 4] 3] 2] ]

Command 0 1 ↑ XX 1 1 0 0 1 1 0 1 cd
vdv0 vdv0 vdv0 vdv0 vdv0
Parameter 1 1 ↑ XX 0 0 0 18
[4] [3] [2] [1] [0]

Command 0 1 ↑ XX 1 1 0 0 1 1 1 0 Ce
Vcm_ Vcm_ Vcm_ Vcm_
Parameter 1 ↑ 1 XX 0 0 0 0 xx
otp[3] otp[2] otp[1] otp[0]

Command 0 1 ↑ XX 1 1 0 0 1 1 1 1 Cf
Vdv_ Vdv_ Vdv_ Vdv_
Parameter 1 ↑ 1 XX 0 0 0 0 xx
otp[3] otp[2] otp[1] otp[0]

Vdv_otp, vcm_otp are initially loaded from OTP and can be written by register later.
VCM0[5:0]+VCM_otp[3:0]=VCM[5:0]
VDV0[4:0]+VDV_otp[3:0]=VDV[4:0]
VCM[5:0]: Adjust the VcomH level (the higher level of Vcom AC voltage). The VCM5-0 bits can
set the VcomH level 0.4 ~ 0.98 times the VREG1OUT level. When VCM4-0 = “111111”, stop
the internal volume adjustment and adjust the VcomH with external resistance from VcomR.
VDV[4:0] Adjust the factor of VREG1OUT to set the amplitude of Vcom.
VCM5:0 VCOMH VCM5:0 VCOMH
000000 Vreg1out*0.685 100000 Vreg1out*0.845
000001 Vreg1out*0.690 100001 Vreg1out*0.850
Description
000010 Vreg1out*0.695 100010 Vreg1out*0.855
000011 Vreg1out*0.700 100011 Vreg1out*0.860
000100 Vreg1out*0.705 100100 Vreg1out*0.865
000101 Vreg1out*0.710 100101 Vreg1out*0.870
000110 Vreg1out*0.715 100110 Vreg1out*0.875
000111 Vreg1out*0.720 100111 Vreg1out*0.880
001000 Vreg1out*0.725 101000 Vreg1out*0.885
001001 Vreg1out*0.730 101001 Vreg1out*0.890
001010 Vreg1out*0.735 101010 Vreg1out*0.895
001011 Vreg1out*0.740 101011 Vreg1out*0.900
001100 Vreg1out*0.745 101100 Vreg1out*0.905
001101 Vreg1out*0.750 101101 Vreg1out*0.910
001110 Vreg1out*0.755 101110 Vreg1out*0.915

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VCM5:0 VCOMH VCM5:0 VCOMH

001111 Vreg1out*0.760 101111 Vreg1out*0.920
010000 Vreg1out*0.765 110000 Vreg1out*0.925
010001 Vreg1out*0.770 110001 Vreg1out*0.930
010010 Vreg1out*0.775 110010 Vreg1out*0.935
010011 Vreg1out*0.780 110011 Vreg1out*0.940
010100 Vreg1out*0.785 110100 Vreg1out*0.945
010101 Vreg1out*0.790 110101 Vreg1out*0.950
010110 Vreg1out*0.795 110110 Vreg1out*0.955
010111 Vreg1out*0.800 110111 Vreg1out*0.960
011000 Vreg1out*0.805 111000 Vreg1out*0.965
011001 Vreg1out*0.810 111001 Vreg1out*0.970
011010 Vreg1out*0.815 111010 Vreg1out*0.975
011011 Vreg1out*0.820 111011 Vreg1out*0.980
011100 Vreg1out*0.825 111100 Vreg1out*0.985
011101 Vreg1out*0.830 111101 Vreg1out*0.990
011110 Vreg1out*0.835 111110 Vreg1out*0.995
Description 011111 Vreg1out*0.840 111111 Vreg1out*1.000

VDV4:0 |COMH-VCOML| VDV4:0 |VCOMH-VCOML|

00000 Vreg1out*0.70 10000 Vreg1out*0.94
00001 Vreg1out*0.72 10001 Vreg1out*0.96
00010 Vreg1out*0.74 10010 Vreg1out*0.98
00011 Vreg1out*0.76 10011 Vreg1out*1.00
00100 Vreg1out*0.78 10100 Vreg1out*1.02
00101 Vreg1out*0.80 10101 Vreg1out*1.04
00110 Vreg1out*0.82 10110 Vreg1out*1.06
00111 Vreg1out*0.84 10111 Vreg1out*1.08
01000 Vreg1out*0.86 11000 Vreg1out*1.10
01001 Vreg1out*0.88 11001 Vreg1out*1.12
01010 Vreg1out*0.90 11010 Vreg1out*1.14
01011 Vreg1out*0.92 11011 Vreg1out*1.16
01100 Vreg1out*0.94 11100 Vreg1out*1.18
01101 Vreg1out*0.96 11101 Vreg1out*1.20
01110 Vreg1out*0.98 11110 Vreg1out*1.22

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01111 Vreg1out1.00 11111 Vreg1out1.24

Note 1) Adjust VREG1OUT and VCM0-5 so that the VcomH level is set within the range of
3.0V~ (DDVDH-0.3)V
Note 2) Adjust VREG1OUT and VDV0-4 so that the Vcom amplitude is set to 6.0V or less

Restriction

Status Availability
Normal Mode On, Idle Mode Off, Sleep Out Yes

Register Normal Mode On, Idle Mode On, Sleep Out Yes
Availability Partial Mode On, Idle Mode Off, Sleep Out Yes
Partial Mode On, Idle Mode On, Sleep Out Yes
Sleep In Yes

Default
Status Default Value
Power On Sequence
S/W Reset No change
H/W Reset

8.2.2.14. OTP control 1-6(D0h, D1h, D2h, D3h, D4h, D5h)

38h OTP control 1-6

DC R WR D17- D7 D6 D5 D4 D3 D2 D1 D0 HEX
D 8
Command 0 1 ↑ XX 1 1 0 1 0 0 0 0 D0
Parameter 1 1 ↑ XX Pdin[7] Pdin[6] Pdin[5] Pdin[4] Pdin[3] Pdin[2] Pdin[1] Pdin[0] 00
Command 0 1 ↑ XX 1 1 0 1 0 0 0 1 D1
1 1 ↑ XX por Power pprog pwe Ptm[1] Ptm[0] Pa[1] Pa[0] 00
Parameter
_sel

Command 0 1 ↑ XX 1 1 0 1 0 0 1 0 D2
Parameter 1st 1 ↑ 1 XX x x x x x x x x xx
Parameter 1 ↑ 1 XX Otp[7] Otp[6] Otp[5] Otp[4] Otp[3] Otp[2] Otp[1] Otp[0] xx
2nd
Command 0 1 ↑ XX 1 1 0 1 0 0 1 1 D3
Parameter 1st 1 ↑ 1 XX x x x x x x x X xx
Parameter 1 ↑ 1 XX Otp Otp Otp Otp Otp Otp[10 Otp[9] Otp[8] xx
[15] [14] [13] [12] [11] ]
2nd

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Command 0 1 ↑ XX 1 1 0 1 0 1 0 0 D4
Parameter 1st 1 ↑ 1 XX x x x x x x x X xx
Parameter 1 ↑ 1 XX Otp Otp Otp Otp Otp Otp Otp Otp xx
[23] [22] [21] [20] [19] [18] [17] [16]
2nd
Command 0 1 ↑ XX 1 1 0 1 0 1 0 0 D5
Parameter 1st 1 ↑ 1 XX x x x x x x x X Xx
Parameter 1 ↑ 1 XX Otp Otp Otp Otp Otp Otp Otp Otp Xx
[31] [30] [29] [28] [27] [26] [25] [24]
2nd
D01h and D01h are OTP programming control registers. see OTP operation section for reference.
OTP[31:0] are data which have been programmed into OTP.
OTP table
Otp[7] Otp[6] Otp[5] Otp[4] Otp[3] Otp[2] Otp[1] Otp[0]
Id0[7] Id0[6] Id0[5] Id0[4] Id0[3] Id0[2] Id0[1] Id0[0]
Description Otp[15] Otp[14] Otp[13] Otp[12] Otp[11] Otp[10] Otp[9] Otp[8]
Id1[7] Id1[6] Id1[5] Id1[4] Id1[3] Id1[2] Id1[1] Id1[0]
Otp[23] Otp[22] Otp[21] Otp[20] Otp[19] Otp[18] Otp[17] Otp[16]
Id2[7] Id2[6] Id2[5] Id2[4] Id2[3] Id2[2] Id2[1] Id2[0]
Otp[31] Otp[30] Otp[29] Otp[28] Otp[27] Otp[26] Otp[25] Otp[24]
Vdv3 Vdv2 Vdv1 Vdv0 Vcm3 Vcm2 Vcm1 Vcm0

Restriction

Status Default Value

Default Power On Sequence
S/W Reset No change
H/W Reset

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8.2.2.15. Gamma control 1-12(E0h, E1h, E2h, E3h, E4h, E5h, E6h, E7h, E8h, E9h, EAh, EBh,)

38h Gamma control 1-12

D R WR D17- D7 D6 D5 D4 D3 D2 D1 D0 H
C D 8 EX
Command 0 1 ↑ XX 1 1 1 0 0 0 0 0 E0

Parameter 1 1 ↑ XX kp1[2] kp1[1] kp1[0] kp0[2] kp0[1] kp0[0] 17

Command 0 1 ↑ XX 1 1 1 0 0 0 0 1 E1

Parameter 1 1 ↑ XX kp3[2] kp3[1] kp3[0] kp2[2] kp2[1] kp2[0] 01

Command 0 1 ↑ XX 1 1 1 0 0 0 1 0 E2

Parameter 1 1 ↑ XX kp5[2] kp5[1] kp5[0] kp4[2] kp4[1] kp4[0] 77

Command 0 1 ↑ XX 1 1 1 0 0 0 1 1 E3

Parameter 1 1 ↑ XX rp1[2] rp1[1] rp1[0] rp0[2] rp0[1] rp0[0] 54

Command 0 1 ↑ XX 1 1 1 0 0 1 0 0 E4

Parameter 1 1 ↑ XX prc0[2] prc0[1] prc0[0] vrp0[4] vrp0[3] vrp0[2] vrp0[1] vrp0[0] 80

Command 0 1 ↑ XX 1 1 1 0 0 1 0 1 E5

Parameter 1 1 ↑ XX prc1[2] prc1[1] prc1[0] vrp1[4] vrp1[3] vrp1[2] vrp1[1] vrp1[0] 88

Command 0 1 ↑ XX 1 1 1 0 0 1 1 0 E6

Parameter 1 1 ↑ XX kn1[2] kn1[1] kn1[0] kn0[2] kn0[1] kn0[0] 00

Command 0 1 ↑ XX 1 1 1 0 0 1 1 1 E7

Parameter 1 1 ↑ XX kp3[2] kp3[1] kp3[0] kp2[2] kp2[1] kp2[0] 67

Command 0 1 ↑ XX 1 1 1 0 1 0 0 0 E8

Parameter 1 1 ↑ XX kn5[2] kn5[1] kn5[0] kn4[2] kn4[1] kn4[0] 06

Command 0 1 ↑ XX 1 1 1 0 1 0 0 1 E9

Parameter 1 1 ↑ XX rn1[2] rn1[1] rn1[0] rn0[2] rn0[1] rn0[0] 46

Command 0 1 ↑ XX 1 1 1 0 1 0 1 0 EA

Parameter 1 1 ↑ XX prc2[2] prc2[1] prc2[0] vrn0[4] vrn0[3] vrn0[2] vrn0[1] vrn0[0] 88

Command 0 1 ↑ XX 1 1 1 0 1 0 1 1 EB

Parameter 1 1 ↑ XX prc3[2] prc3[1] prc3[0] vrn1[4] vrn1[3] vrn1[2] vrn1[1] vrn1[0] 88

Description E0h to EBh are gamma adjust registers. see gamma correction section for reference.

Restriction

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Status Default Value

Default Power On Sequence
S/W Reset No change
H/W Reset

8.2.2.16. Driver timing (ECh)

38h Driver timing

D D17- H
RD WR D7 D6 D5 D4 D3 D2 D1 D0
C 8 EX
E
Command 0 1 ↑ XX 1 1 1 0 1 1 0 0
C
Parameter Nowe Nowe Nowe Nowe Nowi Nowi Nowi
1 1 ↑ XX 22
1st [3] [2] [1] [0] [2] [1] [0]

Parameter Nowi_ Nowi_ Nowi_ Nowi_ Nowi_ Nowi_ Nowi_e Nowi_

1 1 ↑ XX 11
2nd e[7] e[6] e[5] e[4] e[3] e[2] [1] e[0]

Parameter Nowe_ Nowe_ Nowe_ Nowe_ Nowe_ Nowe_ Nowe_e Nowe_

1 1 ↑ XX 11
3rd e[7] e[6] e[5] e[4] e[3] e[2] [1] e[0]

Parameter Vcsiv Vcsiv Vcsiv Scsiv Scsiv Scsiv

1 1 ↑ XX Vcsie Scsie A0
4rd [2] [1] [0] [2] [1] [0]

Parameter Vcsev Vcsev Vcsev Scsev Scsev Scsev

1 1 ↑ XX Vcsee Scsee A0
5rd [2] [1] [0] [2] [1] [0]

Parameter Mcpe Mcpe Mcpe Mcpi Mcpi Mcpi

1 1 ↑ XX 11
6rd [2] [1] [0] [2] [1] [0]

Parameter Mspe Mspe Mspe Mspi Mspi Mspi

1 1 ↑ XX 11
7rd [2] [1] [0] [2] [1] [0]

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NOWI[2:0]: Set the gate output start point from a reference point when synchronizing with
internal clock signal.
Note: The clock in this table is a frequency-divided internal clock.
NOWI[2:0]
3’h0 0(clock period)
3’h1 1clock
3’h2 2clocks
3’h3 3clocks
3’h4 4clocks
3’h5 5clocks
3’h6 6clocks
3’h7 7clocks

NOWE[3:0]: Set the gate output start point in RGB operation.

NOWE[3:0 NOWE[3:0
] ]
0(internal clock period*see 8(internal clock period*see
4’h0 4’h8
note) note)
Description
4’h1 1 4’h9 9
4’h2 2 4’hA 10
4’h3 3 4’hB 11
4’h4 4 4’hC 12
4’h5 5 4’hD 13
4’h6 6 4’hE 14
4’h7 7 4’hF 15
Note: 1clock=(Number of data transfers/pixel) x DIVE (division ratio)[DOTCLK]

NOWI_E[7:0]: Set the gate output end point from a reference point when synchronizing with
internal clock signal.

NOWE_E[7:0]: Set the gate output end point in RGB operation.

SCSIV[2:0]: Sets Vcom charge sharing time when synchronizing with internal clock signal.
0 Setting disabled
1 1clock
2 2clocks

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3 3clocks
4 4clocks
5 5clocks
6 6clocks
7 7clocks
SCSIE: Set Vcom charge sharing off/on when synchronizing with internal clock signal.

VCSIV[2:0]: Sets Vcom charge sharing time when synchronizing with internal clock signal.
0 Setting disabled
1 1clock
2 2clocks
3 3clocks
4 4clocks
5 5clocks
6 6clocks
7 7clocks
VCSIE: Set Vcom charge sharing off/on when synchronizing with internal clock signal.

SCSEV[2:0]: Sets Vcom charge sharing time when synchronizing in RGB operation.
0 Setting disabled
1 1clock
2 2clocks
3 3clocks
4 4clocks
5 5clocks
6 6clocks
7 7clocks
SCSEE: Set Vcom charge sharing off/on when synchronizing in RGB operation.

VCSEV[2:0]: Sets Vcom charge sharing time when synchronizing in RGB operation.
0 Setting disabled
1 1clock
2 2clocks
3 3clocks
4 4clocks
5 5clocks

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6 6clocks
7 7clocks
VCSEE: Set Vcom charge sharing off/on when synchronizing in RGB operation.

MCPI[2:0]: Set the Vcom output timing when synchronizing with internal clock signal.

MCPI[2:0] Vcom output timing from a reference point

3’h0 Setting disabled
3’h1 1clock
3’h2 2clocks
3’h3 3clocks
3’h4 4clocks
3’h5 5clocks
3’h6 6clocks
3’h7 7clocks
Note: The clock in this table is a frequency-divided internal clock.

MSPI[2:0]: Set the source output timing when synchronizing with internal clock signal.
MSPI[2:0] Source output timing from a reference point
3’h0 Setting disabled
3’h1 1clock
3’h2 2clocks
3’h3 3clocks
3’h4 4clocks
3’h5 5clocks
3’h6 6clocks
3’h7 7clocks
Note: The clock in this table is a frequency-divided internal clock.

MCPE[2:0]: Specify theVcom output timing for liquid crystal AC drive in RGB operation.

MCPE[2;0] Vcom output position

3’h0 Setting disabled
3’h1 1clock
3’h2 2clocks
3’h3 3clocks

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3’h4 4clocks
3’h5 5clocks
3’h6 6clocks
3’h7 7clocks
Vcom output timing from a reference point
Note: 1clock=(Number of data transfers/pixel) x DIVE (division ratio)[DOTCLK]

MSPE[2:0]: Specify the source output timing and Vcom alternating timing for liquid crystal AC
drive in RGB operation.

MSPE[2;0] Source output position

3’h0 Setting disabled
3’h1 1clock
3’h2 2clocks
3’h3 3clocks
3’h4 4clocks
3’h5 5clocks
3’h6 6clocks
3’h7 7clocks
Source output timing from a reference point
Note: 1clock=(Number of data transfers/pixel) x DIVE (division ratio)[DOTCLK]
Restriction
Status Availability
Normal Mode On, Idle Mode Off, Sleep Out Yes

Register Normal Mode On, Idle Mode On, Sleep Out Yes
Availability Partial Mode On, Idle Mode Off, Sleep Out Yes
Partial Mode On, Idle Mode On, Sleep Out Yes
Sleep In Yes

Status Default Value

Power On Sequence
Default
S/W Reset No change
H/W Reset

8.2.2.17. Interface control (F6h)

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38h IFCTL(Interface control)

D R D17-
WR D7 D6 D5 D4 D3 D2 D1 D0 HEX
C D 8
Command 0 1 ↑ XX 1 1 1 1 0 1 1 0 F6
Parameter We_
My_ Mx_ Mv_eo Bgr_e
1 1 ↑ XX 0 0 0 mod 00
1st eor eor r or
e

Parameter Epf[ Mdt[ Mdt[

1 1 ↑ XX Epf[1] 0 0 00
2nd 0] 1] 0]

Parameter
1 1 ↑ XX endian 0 Dm[1] Dm[0] rm rim 00
3rd
my_eor/mx_eor/mv_eor/bgr_eor: the set of value MADCTL is used in the IC is derived as
exclusive OR between first parameter of IFCTL and MADCTL parameter.

Mdt[1:0]: select the method of display data transferring.

We_mode: memory write control.

We_mode=0: when the transfer number of data exceeds (EC-SC+1)*(EP-SP+1), the
exceeding data will be ignored.
We_mode=1: when the transfer number of data exceeds (EC-SC+1)*(EP-SP+1), the
column and page number will be reset, and the exceeding data will be
written into the following column and page.

Endian: select the little endian interface bit. At little endian mode, the host sends LSB
Description data first.
endian Data transfer mode
0 Normal (MSB first)
1 Little endian (LSB
first)
Note: the little endian is valid on only 65k 8bit and 9bit MCU interface mode.

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Dm[1:0]: select the display operation mode.

Dm[1] Dm[0] Display operation mode
0 0 Internal clock operation
0 1 RGB interface mode
1 0 Vsync interface mode
1 1 prohibit
The dm][1:0] setting allows switching between internal clock operation mode and
external display interface operation mode. However, switching between the RGB interface
operation and the Vsync interface is prohibited.

Rm: select the interface to access the GRAM.

rm Interface for RAM access
System interface/Vsync
0
interface
1 RGB interface
Rim: specify the RGB interface mode when RGB interface is used. These bits should be
set before display operation through RGB interface and should not be set during
operation.

Rim COLMOD[6:4] Display operation mode

110(262k 18 bit RGB interface (1 transfer/pixel)
0 color)
101(65k color) 16 bit RGB interface (1 transfer/pixel)
110(262k 6 bit RGB interface (3 transfer/pixel)
1
color)

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Description

Restriction
Status Availability
Normal Mode On, Idle Mode Off, Sleep Out Yes

Register Normal Mode On, Idle Mode On, Sleep Out Yes
Availability Partial Mode On, Idle Mode Off, Sleep Out Yes
Partial Mode On, Idle Mode On, Sleep Out Yes
Sleep In Yes

Status Default Value

Power On Sequence 8’h00

Default
S/W Reset No change
H/W Reset 8’h00

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8.2.2.18. PWM duty ratio (F8h)

38h PWM duty ratio

D R D17- H
WR D7 D6 D5 D4 D3 D2 D1 D0
C D 8 EX
Command 0 1 ↑ XX 1 1 1 1 1 0 0 0 F8
Pwm Pwm Pwm Pwm_ Pwm
Parameter 1 1 ↑ XX 0 0 0 00
_dr[4] _dr[3] _dr[2] dr[1] _dr[0]
Pwm_dr[4:0]: Specifies the duty raio of PWM_out. If setting “10h” to F7h, PWM_out should be
Description 50%-50% square pulse.
NOTE: pwm_dr[4:0] should be specified a value to generate PWM_out.
Restriction
Status Availability
Normal Mode On, Idle Mode Off, Sleep Out Yes

Register Normal Mode On, Idle Mode On, Sleep Out Yes
Availability Partial Mode On, Idle Mode Off, Sleep Out Yes
Partial Mode On, Idle Mode On, Sleep Out Yes
Sleep In Yes

Status Default Value

Power On Sequence 8’b00

Default
S/W Reset No change
H/W Reset 8’b00

9. Functional description

9.1 Module CPU interface

9.1.1 Parallel Interface

The Module uses a 11-wires 8-data parallel interface (IM0 = Low) or 19-wires 16-bit parallel
interface (IM0 = High). The chip-select CS (active low) enables and disables the parallel interface.
REST (active low) is an external reset signal. WR is the parallel data write, RD is the parallel data
read and D[7…0] or D[15…0] is parallel data.
The Graphics Controller Chip reads the data at the rising edge of WR signal. The RS is
data/command flag. When RS = “1”, D15 (or D7) to D0 bits are display RAM data or command
parameters. When DC = “0” D15 (or D7) to D0 bits are commands.

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9.1.1.1 Write Cycle/Sequence

The write cycle means that the host writes information (command or/and data) to the display via
the interface. Each write cycle (WR high-low-high sequence) consists of 3 control (DC, RD, WR)
and 8 (D[7..0]) or 16 (D[15…0]) data signals. RS bit is a control signal, which tells if the data
is a command or a data. The data signals are a command if the control signal is low (=’0’) and
vice versa it is data (=’1’).

The write cycle is described in the following figure.

Note: WR is an unsynchronized signal(it can be stopped).

Parallel I/F write Sequence-Example

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RESET

Interface DC

D[15...0] Command Address Command Data

Host D[15...0](MCU to LCD) Command Address Command Data

Hi-Z
Driver D[15...0](MCU to LCD)

Signal on D[15...0] RS and WR

lines during CS”H”are ignored.

9.1.1.2 Read Cycle/Sequence

The read cycle (RD high-low-high sequence) means that the host reads information from the
display via interface. The display sends data (D[7...0] or D[15…0]) to the host when there is a
falling edge of RD and the host reads data when there is a rising edge of RD.

The RD cycle is described the following figure.

Note: RD is an unsynchronized signal(it can be stopped).

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Parallel I/F Read Sequence-example

RESET

Interface DC

D[15...0] Command Address Dummy Data Read Data

Hi-Z
Command Address
Host D[15...0](MCU to LCD)

Hi-Z Dummy Data

Driver D[15...0](MCU to LCD) Read Data

Signal on D[15...0] DC and WR

lines during CS”H”are ignored.

Note:
1. Read Data is only valid when DC input is set High, if DC is set Low during read then Driver
Data line will be High Impedance.
2. This example is for commands: 0Ah, 0Bh, 0Ch, 0Dh, 0Eh, 0Fh, DAh, DBh and DCh.
Other read commands are:
Command 04h Dummy data (1 RD Cycle) 　 Data (3 RD Cycles)
Command 09h 　 Dummy data (1 RD Cycle) 　 Data (4 RD Cycles)
Command 2Eh 　 Dummy data (1 RD Cycle) 　 Data (Any Length RD Cycles More)

9.1.2 Display Module Data Transfer Break

If a 1 or more parameter command is being sent and a break occurs sending before the
last parameter of the command and if the host then sends a new command rather than re-
transmitting the parameter that was interrupted, then the parameters that were successfully sent
are stored and the parameters after the break occurred is rejected if there is a new command as
shown in the following example:

Without break

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With break

Break can be e.g. another command or noise pulse

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9.1.3 Display Module Data Transfer Pause

This applies to the following 4 conditions:

1. Command-Pause-Command
2. Command-Pause-Parameter
3. Parameter-Pause-Command
4. Parameter-Pause-Parameter

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9.1.4 Display Module Data Transfer Modes

The module has four color modes for transferring data to the display data RAM. These are 16-bit
color per pixel, 18-bit color per pixel. The data format is described for each interface. Data can be
downloaded to the Frame Memory by 2 methods.

9.1.4.1 Method 1

The Image data is sent to the Frame Memory in successive Frame writes, each time the Frame
Memory is filled, the Frame Memory pointer is reset to the start pint and the next Frame is written.

9.1.4.2 Method 2

The Image data is sent and at the end of each Frame Memory download, a command is sent to
stop Frame Memory Write. Then Start Memory Write command is sent, and a new Frame
downloaded.

Start Stop
Start Frame Start Frame
Image Data Any Image Data Any Any
Memory Memory
Frame 1 Command Frame 2 Command Command
Write Write
Note:
1. These apply to all Data Transfer Color modes on Parallel interfaces.
2. The Frame Memory can contain both odd and even number of pixels for both Methods.
Only complete pixel data will be stored to the Frame Memory.

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9.1.5 Display Module Data Color Coding

9.1.5.1 8 Data Line Parallel

16bit/Pixel(R 5-bit,G 6-bit,B 5-bit),65,536 colors

Note :The Data order is as follows, MSB = D7, LSB = D0 and Picture Data is MSB = Bit5, LSB =
Bit0 for Green data and MSB = Bit4, LSB = Bit0 for Red and Blue data.

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18 bit/pixel (R 6-bit, G 6-bit, B 6-bit), 262,144 colors

Note: The Data order is as follows, MSB = D7, LSB = D0 and Picture Data is MSB = Bit5, LSB = Bit0
for Red, Green and Blue data.

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9.1.5.2 16 Data Line Parallel

16 bit/pixel (R 5-bit, G 6-bit, B 5-bit), 65,536 colors

Note :The Data order is as follows, MSB = D15, LSB = D0 and Picture Data is MSB = Bit5, LSB =
Bit0 for Green data and MSB = Bit4, LSB = Bit0 for Red and Blue data.

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18 bit/pixel(R 6-bit,G 6-bit,B 6-bit),262,144colors

Note:The Data Order is as follows MSB=D15,LSB=D0 and Picture Data is MSB=Bit 5,LSB=Bit0 for
Red,Green and Blue data.

New Vision Microelectronics Inc. Page 135

9.2 Display Data RAM

9.2.1Configuration
The display data RAM stores display dots and consists of 1,382,400 bits (240 X18X320 bits).
There is no restriction on access to the RAM even when the display data on the same address is
loaded to DAC.
There will be no abnormal visible effect on the display when there is a simultaneous Panel Read
and Interface Read or Write to the same location of the Frame Memory.

9.2.2 Memory to Display Address Mapping

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9.2.2.1 Normal Display On or Partial Mode On, Vertical Scroll Off

In this mode, contents of the frame memory within an area where column pointer is 0000h to 00EFh
and page pointer is 0000h to 013Fh is displayed.
To display a dot on leftmost top corner, store the dot data at (column pointer, page pointer) = ( 0,0 ).

9.2.2.2 Vertical Scroll Mode

There is a vertical scrolling mode, which is determined by the commands “Vertical Scrolling
Definition” (33h) and “Vertical Scrolling Start Address” (37h).

Example 1
TFA = 2, VSA = 318, BFA = 0 when MADCTL Bit B4 = 0

New Vision Microelectronics Inc. Page 137

Example 2
TFA=2,VSA=316,BFA=2 when MADCTL bit B4=0

Example 3
TFA=2,VSA=316,BFA=2 when MADCTL bit B4=0

Note:when Vertical Scrolling Definition Parameters(TFA+VSA+BFA) ≠ 320, Scrolling Mode is

undefined.

9.2.2.3 Vertical Scroll example

Case 1: TFA + VSA + BFA 320

N/A. Do not set TFA + VSA + BFA 320, unless unexpected picture will be shown.

New Vision Microelectronics Inc. Page 138

Case 2: TFA + VSA + BFA = 320 (Rolling Scrolling)

Example 2-a. When TFA = 0, VSA = 320, BFA = 0 and VSCRSADD = 40.

MADCTL parameter B4=”0”

MADCTL parameter B4=”1”

New Vision Microelectronics Inc. Page 139

9.2.3 MCU to memory write/read direction

The data is written in the order illustrated above. The Counter which dictates where in the physical
memory the data is to be written is controlled by “Memory Data Access Control” command, Bits B5,
B6, B7 as described below.

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For each image orientation, the controls for the column and page counters apply as below. ;
B5 B6 B7 CASET PASET

0 0 0 Direct to Physical Column Pointer Direct to Physical Page Pointer

0 0 1 Direct to Physical Column Pointer Direct to (319-Physical Page Pointer)

0 1 0 Direct to (239-Physical Column Pointer) Direct to Physical Page Pointer

0 1 1 Direc to(239-Physical Column Pointer) Direct to (319-Physical Page Pointer)

1 0 0 Direct to Physical Page Pointer Direct to Physical Column Pointer

1 0 1 Direct to (319-Physical Page Pointer) Direct to Physical Column Pointer

1 1 0 Direct to Physical Page Pointer Direct to (239-Physical Column Pointer)

1 1 1 Direct to (319-Physical Page Pointer) Direct to (239-Physical Column Pointer)

For each image orientation, the controls for the column and page counters apply as below:

Condition Column Counter Page Counter

When MEMWR/MEMRD command is accepted Return to “Start Column” Return to “Start Page”

Complete Pixel Read/Write action Increment by 1 No change

The Column counter value is larger than “End Return to “Start Column” Increment by 1

Column”
The Column counter value is larger than “End Return to “Start Column” Return to “Start Page”
Column” and the Page counter value is larger
than “End Page”
Note:
Data is always written to the Frame Memory in the same order, regardless of the Memory
Write Direction set by MADCTL bits B7, B6 and B5. The write order for each pixel unit is

D D D D D D D D D
D8 D7 D6 D5 D4 D3 D2 D1 D0
17 16 15 14 13 12 11 10 9

R R R R R R G G G
G2 G1 G0 B5 B4 B3 B2 B1 B0
5 4 3 2 1 0 5 4 3
One pixel unit represents 1 column and 1 page counter value on the Frame Memory.

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This resultant image for each orientation setting is illustrated below:

Example for rotation with B7,B6 and B5

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This example is using following values: start page = 0, end page = 40, start column = 0 and end
column = 20
= Commands: page address set (0,40) and column address set (0,20).

The sent figure is as follows and its sending order is as follows.

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The sent figure is as follows and its sending order is as follows.

Written image and direction from the host to the frame memory

Writing direction Image from host

Start
Start page=0

End page=40

Start column=0 End column=20

End

Image position on the frame memory with B7=0/1,B6=0/1 and B5=1

Memory Memory
FRAME FRAME
Iocation Iocation
MEMORY MEMORY
(0,0) (0,0) 319

543210
Page counter(B7=1)
543210

543210
Page counter(B7=0)

Memory location
Memory location

012345

319
319

319

012345 239 012345 239

B7=0 Memory location B7=1 Memory location
B6=0 B6=0
012345 239 012345 239
B5=1 B5=1
Column counter(B6=0) Column counter(B6=0)

Memory Memory
FRAME FRAME
Iocation Iocation
MEMORY MEMORY
(0,0) (0,0)
543210

543210
Page counter(B7=0)

319

543210
Page counter(B7=1)
Memory location

Memory location
012345
319

319

012345 239 012345 239

B7=0 Memory location B7=1 Memory location
B6=1 B6=1
239 543210 239 543210
B5=1 B5=1
Column counter(B6=1) Column counter(B6=1)

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9.3 Tearing effect output line

The Tearing Effect output line supplies to the MCU a Panel synchronization signal. This signal
can be enabled or disabled by the Tearing Effect Line Off & On commands. The mode of the
Tearing Effect signal is defined by the parameter of the Tearing Effect Line On command.
The signal can be used by the MCU to synchronize Frame Memory Writing when displaying
video images.

9.3.1 Tearing Effect line Modes

Mode 1, the Tearing Effect Output signal consists of V-Sync Information only:

tvdl tvdh

Vertical Time Scale

tvdh = The LCD display is not updated from the Frame Memory
tvdl = The LCD display is updated from the Frame Memory(except Invisible Line – see below).

Mode 2, the Tearing Effect Output signal consists of V-Sync and H-Sync Information, there is one
V-sync and 320 H- sync pulses per field:

thdh
thdl thdl

V-Sync V-Sync

Invisible 1st Line

line 319th line 320th line

thdh = The LCD display is not updated from the Frame Memory
thdl = The LCD display is updated from the Frame Memory(except Invisible Line – see below).

Bottom Line

Top Line

2nd Line

TE(mode 2)

TE(mode 1)

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Note:During sleep in Mode,the tearing effect Output pin is active low.

9.3.2 Tearing Effect line Timings

The Tearing Effect signal is described below

Symbol Parameter Min. Max Unit Description

tvdl Vertical Timing Low Duration 13 17 ms
tvdh Vertical Timing High Duration 1000 1300 us
thdl Horizontal Timing Low Duration 20 - us
thdh Horizontal Timing High Duration 10 500 us
Notes:
1. the timings in this table apply when MADCTL B4=0 and B4=1
2. The signal’s rise and fall times (tr,tf) are stipulated to be equal to or less than 15ns.

tr tf

80% 80%

20% 20%

The tearing effect output line is fed back to the MCU and should be used as shown below to avoid
tearing effect:

New Vision Microelectronics Inc. Page 146

9.4 Power On/Off Sequence

9.4.1 Power ON/OFF Sequence

IOVCC and VDD can be applied in any order

VDD and IOVcc can be powered down in any order.
During power off, if LCD is in the Sleep Out Mode, VDD and IOVcc must be powered down
minimum 120msec after REST has been released.
During power off, if LCD is in the Sleep In mode, IOVcc or VDD can be powered down minimum
0msec after REST has been released.
CS can be applied at any timing or can be permanently grounded. REST has priority over CS.

Notes:
1. There will be no damage to the display module if the above power sequences are not met.
2. There will be no abnormal visible effects on the display panel during the Power On/Off
Sequences
3. There will be no abnormal visible effects on the display between end of Power On
Sequence and before receiving Sleep Out command. Also between receiving Sleep In
command and Power off sequence.
4. If REST line is not held stable by host during Power On Sequence as defined in Sections
“8.4.1.1 and 8.4.1.2, then it will be necessary to apply a Hardware Reset (REST) after
Host Power On Sequence is complete to
ensure correct operation. Otherwise function is not guaranteed.

The power on/off sequence is illustrated below:

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9.4.1.1 Case 1 – REST line is held high or Unstable by Host at Power On

If REST line is held High or unstable by the host during Power On, then a Hardware Reset must
be applied after both VDD and IOVcc have been applied – otherwise correct functionality is not
guaranteed. There is no timing restriction upon this hardware reset.

trPW=+/- no limit tfPW=+/- no limit

IOVcc
Time when the latter signal rises up to 90% of its Typical
VDD Value. E.g. when VDD comes later, This times is defined at
the cross point of 90% of 2.5/2.75V not 90% of 2.3V

Time when the former signal rises up to 90% of its Typical

Value. E.g. when VDD comes earlier, This times is defined
at the cross point of 90% of 2.5/2.75V not 90% of 2.3V

trPWCS=+/- no limit
trPWCS=+/- no limit

CS H or L

REST trPWREST=+no limit

(power down in
sleep out mode) 30%
trPWREST1= min,120ms

REST trPWREST=+no limit

(power down in
sleep in mode) 30%
trPWREST1= min,0ms
trPWREST1 is applied to REST falling in the Sleep Out Mode
trPWREST2 is applied to REST falling in the Sleep In Mode.

Note: Unless otherwise specified,timing herein show cross point at 50%of signal/power level.

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9.4.1.2 Case 2 – REST line is held low by Host at Power On

If REST line is held Low (and stable) by the host during Power On, then the REST must be held
low for minimum 10usec after both VDD and IOVcc have been applied.

trPW=+/- no limit tfPW=+/- no limit

IOVcc
Time when the latter signal rises up to 90% of its Typical
VDD Value. E.g. when VDD comes later, This times is defined at
the cross point of 90% of 2.5/2.75V not 90% of 2.3V

Time when the former signal rises up to 90% of its Typical

Value. E.g. when VDD comes earlier, This times is defined
at the cross point of 90% of 2.5/2.75V not 90% of 2.3V

trPWCS=+/- no limit
trPWCS=+/- no limit

CS H or L

REST trPWREST=min,10us
(power down in
sleep out mode)
trPWREST1= min,120ms

REST trPWREST=min,10us
(power down in
sleep in mode)
trPWREST1= min,0ms
trPWREST1 is applied to REST falling in the Sleep Out Mode
trPWREST2 is applied to REST falling in the Sleep In Mode.

Note: Unless otherwise specilied, timing herein show cross point at 50%of signal/power level.

9.4.2 Uncontrolled Power off

The uncontrolled power off means a situation when e.g. there is removed a battery without the
controlled power off sequence. The display module must meet following sequences:
1. There cannot be any damages for the display module or the display module cannot cause
any damages for the host or lines of the interface.
2. There cannot be any abnormal visible effects (= display must be blank) within in 1 second
on the display and remains blank until “Power On Sequence” powers it up.

New Vision Microelectronics Inc. Page 149

9.5 Power Level Definition

9.5.1 Power levels

6 level modes are defined they are in order of Maximum power consumption to Minimum power
consumption.
1. Normal Mode On (full display), Idle Mode Off, Sleep Out
In this mode, the display is able to show maximum 262,144 colors.
2. Partial Mode On, Idle Mode Off, Sleep Out
In this mode, part of the display is used with maximum 262,144 colors.
3. Normal Mode On (full display), Idle Mode On, Sleep Out
In this mode, the full display area is used but with 8 colors,
4. Partial Mode On, Idle Mode On, Sleep Out
In this mode, part of the display is used but with 8 colors
5. Sleep In Mode
In this mode, the DC:DC converter, Internal oscillator and panel driver circuit are stopped. Only
the MCU interface and memory works with IOVcc power supply. Contents of the memory are
safe.
6. Power Off Mode.
In this mode, both VDD and IOVcc are removed
Note: Transition between modes 1-5 is controllable by MCU commands. Mode 6 is entered only
when both Power supplies are removed.

New Vision Microelectronics Inc. Page 150

9.5.2 Power flow chart

Notes:
1. There is not any abnormal visual effect when there is changing from one power mode to
anther power mode.
2. There is not any limitation, which is not specified by Nokia, when there is changing from
one power mode to another power mode.

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9.6 8-color Display Mode

The NV3029C has a function to display in eight colors. In 8-color mode, the available grayscales are
only V0 and V63, and the power supplies for other grayscales (V1 to V62) are cut off to reduce
power consumption.

The γ- correction registers, PKP0-PKP5 and PKN0-PKN5, are disabled in 8-color display mode.
In 8-color display mode, the Gamma-micro-adjustment registers are invalid and only the upper bits
of RGB are used for display.

Graphics RAM(GRAM)
MSB LSB

Display R5 R4 R3R2 R1 R0 G5G4 G3 G2 G1G0 B5 B4 B3B2 B1B0

data

R5 G5 B5
V0 Two-level Two-level Two-level
Grayscale Amplifier

grayscale control grayscale control grayscale control

8 2 <R> <G> <B>

LCD driver LCD driver LCD driver

V63

9.7 OTP Operation

Operate mode

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Operating Mode PTM[1] PTM[0] PPROG PWE POR

Stand-by L L L L L
Read Access L L L L H
Entry L L H L L
Program(PGM)
Access L L H H L
Margin-1 Read Mode H L L L H
Margin-2 Read Mode L H L L H

Notes
H stands for logic High level. L stands for logic low level.
PTM[1]=L and PTM[0]=L is for user mode.
PTM[1]=H and PTM[0]=L is for Margin Read Mode. Margin Read Mode provides a critical read
condition to filter out “weak programmed” bits during CP1 sort in the testing flow. To cover all worse
corners, customer should implement Margin Read Mode during testing.

Write /Read Truth Table

In Programming state, the PA indicates which byte of OTP will be programmed.

PDIN Write PDOB Read

L H
H L
Notes
For “Initial”(un-programmed) state or “Erased” state(UV erase),the read out data is “L”

Bit cell mapping table

OTP cell Write Input Data Read Output Data
Cell[7:0] PA[1:0]=[0,0] and PDIN[7:0] PDOB[7:0]
Cell[15:8] PA[1:0]=[0,1]and PDIN[7:0] PDOB[15:8]
Cell[23:16] PA[1:0]=[1,0]nd PDIN[7:0] PDOB[23:16]
Cell[31:24] PA[1:0]=[1,1] and PDIN[7:0] PDOB[31:24]
Note: the 32 OTP cell written from 8 PDIN with PA[1:0] selection .

New Vision Microelectronics Inc. Page 153

Program OTP

Read OTP

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Timing Waveforms

¾ VDD/VPP/GND level is specified in each timing waveform.

¾ Power up sequence timint is based on power measuring point while VDD/VPP is stable as
waveform indicated.
¾ Signal to signal timing is measured from Ti to To of input/output signal at 50% VDD level based
on GND=0V.
¾ Signal rise time Tr (fall time Tf) is defined from 10% 90%(10% 90%)of VDD level based on
GND=0V.

New Vision Microelectronics Inc. Page 155

Timing parameters
Parameter Symbol Min Max Unit
Rising Time/Falling Timing Tt/Tf - 1 ns
Data Access Time Taa - 70 ns
POR Read Pulse Width Tpor 200 - ns
Address Setup/Hold Time Tas/Tah 4 - ns
Data Setup/Hold Time Tah/Tdh 9 - ns
Output Hold Time Toh 0 0 ns
External VPP Setup Time Tvps 0 - ns
External VPP Hold Time Tvph 0 - ns
Program Recovery Time Tvr 10 - us
Program Pulse Width Tpw 300 350 us
VDD Setup Time Tvds 0 - ns
VDD Recovery Time Tvdr 0 - ns
PPROG Setup Time Tpps 10 - ns
PPROG Recovery Time Tppr 10 - ns
Power on Read Time Trst 20 - ns
PTM Mode Setup/Hold Time Tms/ Tmh 10/10 - ns
Notes:
1. All electrical and timing parameters listed above are based on SPICEor( equivalent)
simulations and subject to change after silicon verification.
2. Capacitive loading should less than 1pf same as simulation conditions.
3. Tpw have maximum value limitation, which is reliability concern to avoid long HV tress time.

Input Capacitance
Pin Capacitance Symbol Min. Max. Unit Test Condition
Control Input CCON -- 0.7 pF Vin=0 at f=1 MHz
Address Input CADD -- 0.3 pF Vin=0 at f=1 MHz
Data Input CDIN -- 0.3 pF Vin=0 at f=1 MHz
VPP(from OTP block) CPP -- 3.0 pF Vin=0 at f=1 MHz

9.8 Gamma Correction

NV3029C has the gamma-correction function to display in 262,144 colors for liquid crystal panels.
The gamma-correction is performed with 3 groups of registers determining eight reference
grayscale levels, which are gradient adjustment, amplitude adjustment and fine-adjustment registers

New Vision Microelectronics Inc. Page 156

for positive and negative polarities. Each register group is set independently to other register groups,
making the NV3029C available with liquid crystal panels of various characteristics.

VRP14 VRP13 VRP12 VRP11 VRP10

Graphics RAM(GRAM) VRP04 VRP03 VRP02 VRP01 VRP00
PRP12 PRP11 PRP10
PRP02 PRP01 PRP00
Positive PKP02 PKP01 PKP00
polarity PKP 12 PKP11 PKP10
PKP22 PKP21 PKP20
R5 R4 R3R2 R1 R0 G5 G4 G3 G2 G1G0 B5 B4 B3 B2 B1 B0 Register PKP32 PKP31 PKP30
PKP42 PKP41 PKP40
PKP52 PKP51 PKP50
PKN52 PKN51 PKN50
PKN42 PKN41 PKN40
Negative PKN32 PKN31 PKN30
PKN22 PKN21 PKN20
polarity PKN12 PKN11 PKN10
Register PKN02 PKN01 PKN00
PRN02 PRN01 PRN00
PRN12 PRN11 PRN10
VRN04 VRN03 VRN02 VRN01 VRN00
VRN14 VRN13 VRN12 VRN11 VRN10

VRP114VRP113VRP112VRP111 VRP110
VRP104VRP103VRP102 VRP101 VPP100
6 6 6 PRP112 PRP111 PRP110
PRP102 PRP101 PRP100
V0 Positive PKP102 PKP101 PKP100
PKP
polarity PKP112 PKP111 PKP110
6bit Grayscale 6bit Grayscale 6bit Grayscale V1 122 PKP121 PKP120
Register PKP132 PKP131 PKP130
D/A Converter D/A Converter D/A Converter PKP142 PKP141 PKP140
Grayscale PKP152 PKP151 PKP150
Voltage VRN114VRN113VRN112VRN111 VRN110
Generator VRN104VRN103VRN102 VRN101 VPN100
PRN112 PRN111 PRN110
Negative PRN102 PRN101 PRN100
PKN102 PKN101 PKN100
polarity PKN112 PKN111 PKN110
Output Driver Output Driver Output Driver Register PKN122 PKN121 PKN120
63
PKN132 PKN131 PKN130
PKN142 PKN141 PKN140
PKN152 PKN151 PKN150

VRP214VRP213VRP212VRP211 VRP210
VRP204VRP203VRP202 VRP201 VPP200
PRP212 PRP211 PRP210
PRP202 PRP201 PRP200
PKP202 PKP201 PKP200
Positive PKP212 PKP211 PKP210
polarity PKP222 PKP221 PKP220
Register PKP232 PKP231 PKP230
PKP242 PKP241 PKP240
PKP252 PKP251 PKP250
VRN214VRN213VRN212VRN211 VRN210
VRN204VRN203VRN202 VRN201 VPN200
PRN212 PRN211 PRN210
PRN202 PRN201 PRN200
PKN202 PKN201 PKN200
Negative PKN212 PKN211 PKN210
polarity PKN222 PKN221 PKN220
LCD Register PKN232 PKN231 PKN230
PKN242 PKN241 PKN240
PKN252 PKN251 PKN250

Grayscale amplifier unit

In grayscale amplifier unit, 8-levels VINP(N)0~VINP(N)7 and 4-levels VINP(N)2_mid
VINP(N)3A_mid VINP(N)3B_mid VINP(N)4_mid are determined by gradient and fine adjustment
registers.
Then, the 8 levels are divided by the internal ladder resistors between grayscale amplifier and 64
grayscale levels(V0~V63) are generated.

New Vision Microelectronics Inc. Page 157

Micro adjust registers Micro adjust registers

PKP0/N0 PKP1/N1PKP2/N2 PKP3/N3 PKP4/N4 PKP5/N5 PRCP0 PRC1 PRC2 PRC3

VGAM1OUT
3 3 3 3 3 3 3 3 3 3

VINP0/VINN0
V0

8 to
VINP1/VINN1
1
selec V1
tor

8 to
1 VINP2/VINN2
selec V8
tor
VINP2_mid/
8 to
VINN2_mid
1
selec V14
tor
8 to
VINP3/VINN3
1
selec V20
5 3
tor
VINP3A_mid/
8 to
VINN3A_mid
1
selec V28
VRP0/VRN0 VRLP/VRLN
tor
Offset Center
Adjust Adjust
Register Register VINP3B_mid/
8 to
VINN3B_mid
1
VRP1/VRN1 VRHP/VRHN
selec V35
tor

5 3 8 to VINP4/VINN4
1
V43
selec
tor
VINP4_mid/
8 to VINN4_mid
1
selec
V49
tor
8 to
1 VINP5/VINN5
selec V55
tor

8 to
1 VINP6/VINN6
selec V62
tor

VINP7/VINN7
V63

VGS

Grayscale Voltage Generation

New Vision Microelectronics Inc. Page 158

VGAM1OUT

VRP0[4:0] VRN 0 VRN 0[4:0]

VRP 0
0~31R 0~ 31R
VINP 0 VINN0
KVP0 KVN0

PKP0[2:0] PKN0[2:0]
RP0 5R RN0
5R
KVP 1 KVN1
RP1 RN1 KVN 2
KVP 2
RP2 RN2 KVN 3
KVP 3 4R*7
4R*7 RP3 8 to 1 RN3 KVN 4 8 to 1
KVP 4 SEL VINN1
SEL VINP 1 RN4
RP4 KVP 5 KVN 5
RP5 RN5 KVN 6
KVP 6
RP6 RN6 KVN 7
KVP 7
RP7 RN7 KVN 8
KVP 8

VRHP PRP0 [2:0] VRHN PRN0[2:0] PKN1[2:0]

0~28R PKP1[2:0] 0~28R
KVN 9
KVP 9 RN8 KVN10
RP8 KVP 10 RN9 KVN11 PRC0[2:0]
RP9 KVP 11 PRC0[2:0] 1R*7
1R*7 RN10 KVN12 8 to 1
RP10 KVP 12 8 to 1 SEL VINN 2
VINP 2 RN11 KNV13
RP11 KVP 13 SEL RN12 7R
S21
7R KVN14
RP12 KVP 14 S21 RN13 KVN15 S22
RP13 KVP 15 S22 RN14 KVN16 S23
RP14 KVP 16 S23
S24 8 to 1
8 to 1 VINN2_mid
S24 VINP2_mid PKN2[2:0] 2R*7 SEL
PKP2[2:0] 2R*7 SEL RN15 S25
5R S25 5R
RP15 S26
S26 KVN17
KVP17 S27
S27 RN16 KVN18
RP16 KVP18 S28
S28 RN17 KVN19 7R
RP17 KVP19 7R PRC1[2:0]
PRC1[2:0] RN18 KVN20 8 to 1
RP18 KVP20 8 to 1 SEL VINN3
VINP3 1R*7 RN19 KVN21
RP19 SEL 7R
KVP21

2R*7
S31A
1R*7 7R RN20 S31A
KVN22
2R*7

S31A S31B
RP20 KVP22
S31A
S31B
RN21 KVN23
S32A
8 to 1 VINN3A_mid
RP21 KVP23
S32A
8 to 1 VINP3A_mid
S32B
SEL
S32B
SEL RN22 KVN24
S33A
RP22 KVP24
S33A
S33B S34A
S33B
PRC2[2:0]
S38A
S34A S38A PRC2[2:0] S34B
PKP3[2:0] S34B PKN3[2:0] S35A
16R RP23 S35A
S35B S31B 16R RN23 S35B S31B
S36A
S36A S36B
KVP25 S36B
KVN25 S37A 8 to 1
8 to 1 VINN3B_mid

2R*8
S37A S37B SEL
RP24 KVP26 VINP3B_mid RN24 KVN26
2R*8

S37B SEL S38A

S38A S38B
RP25 KVP27 S38B RN25 KVN27 7R
S38B
PRC3[2:0]
S38B
PRC3[2:0]
RP26 7R
KVP28 8 to 1 RN26 KVN28 8 to 1 VINN4
SEL VINP4 SEL
RP27 KVP29 1R*7 RN27 KVN29 7R
1R*7 S41
RP28 7R RN28
KVP30 S41 KVN30
RP29 RN29 S42
KVP31 S42 KVN31
RP30 RN30 S43
KVP32 S43 KVN32
S44 8 to 1
8 to 1 VINN4_mid
S44 VINP4_mid PKN4[2:0] 2R*7 SEL
PKP4[2:0] 2R*7 SEL RN31 S45
S45 5R
5R RP31 S46
S46 KVN 33
KPV 33 S47
S47 RN32 KVN 34
RP32 KPV 34 S48
S48 RN33 KVN 35 7R
RP33 KPV 35 7R RN34 KVN 36 8 to 1
RP34 KPV 36 8 to 1 SEL VINN5
VINP5 RN35 KVN 37
1R*7 RP35 SEL 1R*7
KPV 37 RN36
RP36 KVN 38
KPV 38 RN37
RP37 KVN 39
KPV 39 RN38
RP38 KVN 40
KPV 40

PKP5[2:0] VRLN PRN1 [2:0] PKN5[2:0]

VRLP PRP1 [2:0]
0~28R 0~28R
KVN 41
KPV 41 RN39
RP39 KVN 42
KVP 42 RN40
RP40 KVN 43
KPV 43 RN41
RP41 KVN 44 8 to 1
KVP 44 8 to 1 RN42 SEL VINN6
SEL VINP6 4R*7 KVN 45
4R*7 RP42 KVP 45 RN43 KVN 46
RP43 KVP 46 RN44 KVN 47
RP44 KVP 47 RN45 KVN 48
RP45 KVP 48

5R RN46 KVN49
5R RP46 KVP 49 VINN7
VINP7
VRN1 VRN 1[4:0]
VRP 1 VRP1[4:0]
0~31R 0 ~31R

8R RP47 8R RN47

VGS

EXVR

γ correction registers
The gamma correction registers of the NV3029C consists of gradient-adjustment, amplitude-
adjustment, fine-adjustment registers to correct grayscale voltage levels according to the gamma
characteristics of the liquid crystal panel. These register settings make adjustments to the
relationship between the grayscale number and its corresponding grayscale voltage level and the
setting can be made differently for positive and negative polarities (the reference level and the
register settings are the same for all RGB dots). The function of each register is as follows.

New Vision Microelectronics Inc. Page 159

1.Gradient adjustment registers

The gradient adjustment registers are used to adjust the gradients in the middle grayscale range
without changing the dynamic range. Adjustments are made by changing the resistance values of
the resistors (VRHP(N)/VRLP(N)) in the middle of the ladder resistor unit. The gradient adjustment
registers consist of positive and negative polarity registers to allow asymmetric drive.

2. Amplitude adjustment registers

The amplitude adjustment registers are used to adjust the amplitude of the grayscale voltage by
changing the resistance values of the resistors (VRP(N)1/0) at both ends of the ladder resistor unit.
Same with the gradient registers, the amplitude adjustment registers consist of positive and
negative polarity registers.

3. Fine adjustment registers

The fine adjustment registers are used for minute adjustment of grayscale voltage. The fine
adjustment register represent one voltage level to be selected in the 8-to-1 selector among 10 levels
generated from the ladder resistor unit. Same with other registers, the fine adjustment registers
consist of positive and negative polarity registers.
Register Positive Negative Function
PRP0[2:0] PRN0[2:0] Variable resistor VRHP(N)
Gradient
PRP1[2:0] PRN1[2:0] Variable resistor VRLP(N)
VRP0[4:0] VRN0[4:0] Variable resistor VRP(N)0
Amplitude
VRP1[4:1] VRN1[4:1] Variable resistor VRP(N)1
PKP0[2:0] PKN0[2:0] 8 to 1 selector(determine voltage level 1)
PKP1[2:0] PKN1[2:0] 8 to 1 selector(determine voltage level 8)
PKP2[2:0] PKN2[2:0] 8 to 1 selector(determine voltage level 20)
PKP3[2:0] PKN3[2:0] 8 to 1 selector(determine voltage level 43)
Fine PKP4[2:0] PKN4[2:0] 8 to 1 selector(determine voltage level 55)
adjustment PKP5[2:0] PKN5[2:0] 8 to 1 selector(determine voltage level 62)
PRCP0[2:0] PRCN0[2:0] 8 to 1 selector(determine voltage level 14)
PRCP1[2:0] PRCN1[2:0] 8 to 1 selector(determine voltage level 28)
PRCP2[2:0] PRCN2[2:0] 8 to 1 selector(determine voltage level 35)
PRCP3[2:0] PRCN3[2:0] 8 to 1 selector(determine voltage level 49)

New Vision Microelectronics Inc. Page 160

Reference voltage generating block (Ladder resistor units and 8-to-1 selectors)

Block configuration

The ladder resistor and 8-to-1 selector unit consists of two ladder resistor unit including variable
resistors and 8-to-1 selectors which selects a voltage generated by the ladder resistor unit and
output the reference voltage from which grayscale voltages are generated. The correction registers
represent the resistance values of these resistors in the ladder resistor unit and the reference levels
selected in the 8-to-1 selectors (see Table 68 γ correction register).

Variable resistors

The NV3029C uses variable resistors for the following three purposes: gradient adjustment
(VRHP(N)/VRLP(N)); amplitude adjustment (1) (VRP(N)0); and amplitude adjustment (2) (VRP(N)1).
The resistance values are determined by gradient adjustment and amplitude adjustment registers
as below.

Register Resistance
Register Resistance Resistance Register
VRP(N)1 VRHP(N)
VRP(N)0[4:0] VRP(N)0 VRP(N)1 PRP(N)0/1[2:0]
[4:0] VRLP(N)
00000 0R 00000 0R 000 0R
00001 1R 00001 1R 001 4R
00010 2R 00010 2R 010 8R
011 12R
… … … …
100 16R

11101 29R 11101 29R 101 20R

11110 30R 11110 30R 110 24R
11111 31R 11111 31R 111 28R
Amplitude Adjustment Amplitude Adjustment 2 Gradient Adjustment

8 to 1 selector

The 8-to-1 selector selects one voltage level according to the fine adjustment register setting among
the
voltages generated by ladder resistors, and outputs the selected level as one of the reference
voltages
(VINP(N)1~6). The following table shows the correspondence between the selected voltage levels
and the fine-adjustment register settings for respective reference voltage levels (VINP(N)1~6).

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Value in
Voltage level
Register
PKP(N)0-5 VINP VINP VINP VINP VINP VINP
[2:0] （N）1 （N）2 （N）3 （N）4 （N）5 （N）6
000 KVP(N)1 KVP(N)9 KVP(N)17 KVP(N)25 KVP(N)33 KVP(N)41
001 KVP(N)2 KVP(N)10 KVP(N)18 KVP(N)26 KVP(N)34 KVP(N)42
010 KVP(N)3 KVP(N)11 KVP(N)19 KVP(N)27 KVP(N)35 KVP(N)43
011 KVP(N)4 KVP(N)12 KVP(N)20 KVP(N)28 KVP(N)36 KVP(N)44
100 KVP(N)5 KVP(N)13 KVP(N)21 KVP(N)29 KVP(N)37 KVP(N)45
101 KVP(N)6 KVP(N)14 KVP(N)22 KVP(N)30 KVP(N)38 KVP(N)46
110 KVP(N)7 KVP(N)15 KVP(N)23 KVP(N)31 KVP(N)39 KVP(N)47
111 KVP(N)8 KVP(N)16 KVP(N)24 KVP(N)32 KVP(N)40 KVP(N)48

Value in
Voltage level
Register
PRCP(N)0-3
VIN2_mid VIN3A_mid VIN3B_mid VIN4_mid
[2:0]
000 S21 S31 SS31 S41
001 S22 S32 SS32 S42
010 S23 S33 SS33 S43
011 S24 S34 SS34 S44
100 S25 S35 SS35 S45
101 S26 S36 SS36 S46
110 S27 S37 SS37 S47
111 S28 S38 SS38 S48

The grayscale levels are determined by the following formulas.

Voltage Calculation Formula (Negative Polarity)
Reference Macro Adjustment
Formula Pin
Voltage Value
VINN0 - VGAM1OUT-VD*VRN0 /sumRN KVN0
VINN1 PKN0 2-0=000 VGAM1OUT-VD((VRN0+5R) /sumRN KVN1
PKN0 2-0=001 VGAM1OUT-VD((VRN0+9R) /sumRN KVN2
PKN0 2-0=010 VGAM1OUT-VD((VRN0+13R) /sumRN KVN3
PKN0 2-0=011 VGAM1OUT-VD((VRN0+17R) /sumRN KVN4
PKN0 2-0=100 VGAM1OUT-VD((VRN0+21R) /sumRN KVN5
PKN0 2-0=101 VGAM1OUT-VD((VRN0+25R) /sumRN KVN6

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PKN0 2-0=110 VGAM1OUT-VD((VRN0+29R) /sumRN KVN7

PKN0 2-0=111 VGAM1OUT-VD((VRN0+33R) /sumRN KVN8
PKN1 2-0=000 VGAM1OUT-VD((VRN0+33R+VRHN) /sumRN KVN9
PKN1 2-0=001 VGAM1OUT-VD((VRN0+34R+VRHN) /sumRN KVN10
PKN1 2-0=010 VGAM1OUT-VD((VRN0+35R+VRHN) /sumRN KVN11
PKN1 2-0=011 VGAM1OUT-VD((VRN0+36R+VRHN) /sumRN KVN12
VINN2
PKN1 2-0=100 VGAM1OUT-VD((VRN0+37R+VRHN) /sumRN KVN13
PKN1 2-0=101 VGAM1OUT-VD((VRN0+38R+VRHN) /sumRN KVN14
PKN1 2-0=110 VGAM1OUT-VD((VRN0+39R+VRHN) /sumRN KVN15
PKN1 2-0=111 VGAM1OUT-VD((VRN0+40R+VRHN) /sumRN KVN16
PKN2 2-0=000 VGAM1OUT-VD((VRN0+45R+VRHN) /sumRN KVN17
PKN2 2-0=001 VGAM1OUT-VD((VRN0+46R+VRHN) /sumRN KVN18
PKN2 2-0=010 VGAM1OUT-VD((VRN0+47R+VRHN) /sumRN KVN19
PKN2 2-0=011 VGAM1OUT-VD((VRN0+48R+VRHN) /sumRN KVN20
VINN3
PKN2 2-0=100 VGAM1OUT-VD((VRN0+49R+VRHN) /sumRN KVN21
PKN2 2-0=101 VGAM1OUT-VD((VRN0+50R+VRHN) /sumRN KVN22
PKN2 2-0=110 VGAM1OUT-VD((VRN0+51R+VRHN) /sumRN KVN23
PKN2 2-0=111 VGAM1OUT-VD((VRN0+52R+VRHN) /sumRN KVN24
PKN3 2-0=000 VGAM1OUT-VD((VRN0+68R+VRHN) /sumRN KVN25
PKN3 2-0=001 VGAM1OUT-VD((VRN0+69R+VRHN) /sumRN KVN26
PKN3 2-0=010 VGAM1OUT-VD((VRN0+70R+VRHN) /sumRN KVN27
PKN3 2-0=011 VGAM1OUT-VD((VRN0+71R+VRHN) /sumRN KVN28
VINN4
PKN3 2-0=100 VGAM1OUT-VD((VRN0+72R+VRHN) /sumRN KVN29
PKN3 2-0=101 VGAM1OUT-VD((VRN0+73R+VRHN) /sumRN KVN30
PKN3 2-0=110 VGAM1OUT-VD((VRN0+74R+VRHN) /sumRN KVN31
PKN3 2-0=111 VGAM1OUT-VD((VRN0+75R+VRHN) /sumRN KVN32
PKN4 2-0=000 VGAM1OUT-VD((VRN0+80R+VRHN) /sumRN KVN33
PKN4 2-0=001 VGAM1OUT-VD((VRN0+81R+VRHN) /sumRN KVN34
PKN4 2-0=010 VGAM1OUT-VD((VRN0+82R+VRHN) /sumRN KVN35
PKN4 2-0=011 VGAM1OUT-VD((VRN0+83R+VRHN) /sumRN KVN36
VINN5
PKN4 2-0=100 VGAM1OUT-VD((VRN0+84R+VRHN) /sumRN KVN37
PKN4 2-0=101 VGAM1OUT-VD((VRN0+85R+VRHN) /sumRN KVN38
PKN4 2-0=110 VGAM1OUT-VD((VRN0+86R+VRHN) /sumRN KVN39
PKN4 2-0=111 VGAM1OUT-VD((VRN0+87R+VRHN) /sumRN KVN40
PKN5 2-0=000 VGAM1OUT-VD((VRN0+87R+VRHN+VRLN) /sumRN KVN41
PKN5 2-0=001 VGAM1OUT-VD((VRN0+91R+VRHN+VRLN) /sumRN KVN42
PKN5 2-0=010 VGAM1OUT-VD((VRN0+95R+VRHN+VRLN) /sumRN KVN43
PKN5 2-0=011 VGAM1OUT-VD((VRN0+99R+VRHN+VRLN) /sumRN KVN44
VINN6
PKN5 2-0=100 VGAM1OUT-VD((VRN0+103R+VRHN+VRLN)/sumRN KVN45
PKN5 2-0=101 VGAM1OUT-VD((VRN0+107R+VRHN+VRLN)/sumRN KVN46
PKN5 2-0=110 VGAM1OUT-VD((VRN0+111R+VRHN+VRLN)/sumRN KVN47
PKN5 2-0=111 VGAM1OUT-VD((VRN0+115R+VRHN+VRLN)/sumRN KVN48
VINN7 - VGAM1OUT-VD((VRN0+120R+VRHN+VRLN)/sumRN KVN49
SumRN=128R+VRHN+VRLN+VRN0+VRN1

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VD=(VGAM1OUT-VGS)
sumRPx (sumRN/ (sumRP+sumRN))]/ [sumRPx sumRN/ (sumRP+sumRN) +EXVR]

PRCP0=000 VINN2-(VINN2-VINN3)*7R/28R
PRCP0=001 VINN2-(VINN2-VINN3)*9R/28R
PRCP0=010 VINN2-(VINN2-VINN3)*11R/28R
PRCP0=011 VINN2-(VINN2-VINN3)*13R/28R
VINN2_mid
PRCP0=100 VINN2-(VINN2-VINN3)*15R/28R
PRCP0=101 VINN2-(VINN2-VINN3)*17R/28R
PRCP0=110 VINN2-(VINN2-VINN3)*19R/28R
PRCP0=111 VINN2-(VINN2-VINN3)*21R/28R
PRCP1=000 VINN3-(VINN3-VINN4)*7R/44R
PRCP1=001 VINN3-(VINN3-VINN4)*9R/44R
PRCP1=010 VINN3-(VINN3-VINN4)*11R/44R
PRCP1=011 VINN3-(VINN3-VINN4)*13R/44R
VINN3A_mid
PRCP1=100 VINN3-(VINN3-VINN4)*15R/44R
PRCP1=101 VINN3-(VINN3-VINN4)*17R/44R
PRCP1=110 VINN3-(VINN3-VINN4)*19R/44R
PRCP1=111 VINN3-(VINN3-VINN4)*21R/44R
PRCP2=000 VINN3-(VINN3-VINN4)*23R/44R
PRCP2=001 VINN3-(VINN3-VINN4)*25R/44R
PRCP2=010 VINN3-(VINN3-VINN4)*27R/44R
PRCP2=011 VINN3-(VINN3-VINN4)*29R/44R
VINN3B_mid
PRCP2=100 VINN3-(VINN3-VINN4)*31R/44R
PRCP2=101 VINN3-(VINN3-VINN4)*33R/44R
PRCP2=110 VINN3-(VINN3-VINN4)*35R/44R
PRCP2=111 VINN3-(VINN3-VINN4)*37R/44R
PRCP3=000 VINN4-(VINN4-VINN5)*7R/28R
PRCP3=001 VINN4-(VINN4-VINN5)*9R/28R
PRCP3=010 VINN4-(VINN4-VINN5)*11R/28R
PRCP3=011 VINN4-(VINN4-VINN5)*13R/28R
VINN4_mid
PRCP3=100 VINN4-(VINN4-VINN5)*15R/28R
PRCP3=101 VINN4-(VINN4-VINN5)*17R/28R
PRCP3=110 VINN4-(VINN4-VINN5)*19R/28R
PRCP3=111 VINN4-(VINN4-VINN5)*21R/28R

New Vision Microelectronics Inc. Page 164

Voltage Calculation Formula of Grayscale Voltage (Negative Polarity)

N_Grayscale Formula
V63 VINN0
V62 VINN1
V61 VINN1-(VINN1-VINN2)*72/192
V60 VINN1-(VINN1-VINN2)*114/192
V59 VINN1-(VINN1-VINN2)*137/192
V58 VINN1-(VINN1-VINN2)*159/192
V57 VINN1-(VINN1-VINN2)*172/192
V56 VINN1-(VINN1-VINN2)*182/192
V55 VINN2
V54 VINN2-(VINN2-VINN2_mid)*6/48
V53 VINN2-(VINN2-VINN2_mid)*15/48
V52 VINN2-(VINN2-VINN2_mid)*30/48
V51 VINN2-(VINN2-VINN2_mid)*37/48
V50 VINN2-(VINN2-VINN2_mid)*44/48
V49 VINN2_mid
V48 VINN2_mid-(VINN2_mid-VINN3)*8/48
V47 VINN2_mid-(VINN2_mid-VINN3)*16/48
V46 VINN2_mid-(VINN2_mid-VINN3)*24/48
V45 VINN2_mid-(VINN2_mid-VINN3)*32/48
V44 VINN2_mid-(VINN2_mid-VINN3)*40/48
V43 VINN3
V42 VINN3-(VINN3-VINN3A_mid)*6/72
V41 VINN3-(VINN3-VINN3A_mid)*16/72
V40 VINN3-(VINN3-VINN3A_mid)*28/72
V39 VINN3-(VINN3-VINN3A_mid)*40/72
V38 VINN3-(VINN3-VINN3A_mid)*48/72
V37 VINN3-(VINN3-VINN3A_mid)*56/72
V36 VINN3-(VINN3-VINN3A_mid)*64/72
V35 VINN3A_mid
V34 VINN3A_mid-(VINN3A_mid-VINN3B_mid)*8/48
V33 VINN3A_mid-(VINN3A_mid-VINN3B_mid)*16/48
V32 VINN3A_mid-(VINN3A_mid-VINN3B_mid)*21/48
V31 VINN3A_mid-(VINN3A_mid-VINN3B_mid)*27/48
V30 VINN3A_mid-(VINN3A_mid-VINN3B_mid)*32/48
V29 VINN3A_mid-(VINN3A_mid-VINN3B_mid)*40/48
V28 VINN3B_mid
V27 VINN3B_mid-(VINN3B_mid-VINN4)*7/72
V26 VINN3B_mid-(VINN3B_mid-VINN4)*14/72
V25 VINN3B_mid-(VINN3B_mid-VINN4)*21/72
V24 VINN3B_mid-(VINN3B_mid-VINN4)*28/72
V23 VINN3B_mid-(VINN3B_mid-VINN4)*33/72

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V22 VINN3B_mid-(VINN3B_mid-VINN4)*42/72
V21 VINN3B_mid-(VINN3B_mid-VINN4)*62/72
V20 VINN4
V19 VINN4-(VINN4-VINN4_mid)*6/48
V18 VINN4-(VINN4-VINN4_mid)*12/48
V17 VINN4-(VINN4-VINN4_mid)*16/48
V16 VINN4-(VINN4-VINN4_mid)*24/48
V15 VINN4-(VINN4-VINN4_mid)*36/48
V14 VINN4_mid
V13 VINN4_mid-(VINN4_mid-VINN5)*11/48
V12 VINN4_mid-(VINN4_mid-VINN5)*16/48
V11 VINN4_mid-(VINN4_mid-VINN5)*18/48
V10 VINN4_mid-(VINN4_mid-VINN5)*24/48
V9 VINN4_mid-(VINN4_mid-VINN5)*38/48
V8 VINN5
V7 VINN5-(VINN5-VINN6)*15/192
V6 VINN5-(VINN5-VINN6)*30/192
V5 VINN5-(VINN5-VINN6)*40/192
V4 VINN5-(VINN5-VINN6)*60/192
V3 VINN5-(VINN5-VINN6)*80/192
V2 VINN5-(VINN5-VINN6)*120/192
V1 VINN6
V0 VINN7

Note: Make sure DDVDH-V00.5V DDVDH-V81.1V

Voltage Calculation Formula (Positive Polarity)

Reference Macro Adjustment
Formula Pin
Voltage Value
VINP0 - VGAM1OUT-VD*VRP0 /sumRP KVP0
PKP0 2-0=000 VGAM1OUT-VD((VRP0+5R) /sumRP KVP1
PKP0 2-0=001 VGAM1OUT-VD((VRP0+9R) /sumRP KVP2
PKP0 2-0=010 VGAM1OUT-VD((VRP0+13R) /sumRP KVP3
PKP0 2-0=011 VGAM1OUT-VD((VRP0+17R) /sumRP KVP4
VINP1
PKP0 2-0=100 VGAM1OUT-VD((VRP0+21R) /sumRP KVP5
PKP0 2-0=101 VGAM1OUT-VD((VRP0+25R) /sumRP KVP6
PKP0 2-0=110 VGAM1OUT-VD((VRP0+29R) /sumRP KVP7
PKP0 2-0=111 VGAM1OUT-VD((VRP0+33R) /sumRP KVP8
VINP2 PKP1 2-0=000 VGAM1OUT-VD((VRP0+33R+VRHP) /sumRP KVP9
PKP1 2-0=001 VGAM1OUT-VD((VRP0+34R+VRHP) /sumRP KVP10
PKP1 2-0=010 VGAM1OUT-VD((VRP0+35R+VRHP) /sumRP KVP11
PKP1 2-0=011 VGAM1OUT-VD((VRP0+36R+VRHP) /sumRP KVP12
PKP1 2-0=100 VGAM1OUT-VD((VRP0+37R+VRHP) /sumRP KVP13

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PKP1 2-0=101 VGAM1OUT-VD((VRP0+38R+VRHP) /sumRP KVP14

PKP1 2-0=110 VGAM1OUT-VD((VRP0+39R+VRHP) /sumRP KVP15
PKP1 2-0=111 VGAM1OUT-VD((VRP0+40R+VRHP) /sumRP KVP16
PKP2 2-0=000 VGAM1OUT-VD((VRP0+45R+VRHP) /sumRP KVP17
PKP2 2-0=001 VGAM1OUT-VD((VRP0+46R+VRHP) /sumRP KVP18
PKP2 2-0=010 VGAM1OUT-VD((VRP0+47R+VRHP) /sumRP KVP19
PKP2 2-0=011 VGAM1OUT-VD((VRP0+48R+VRHP) /sumRP KVP20
VINP3
PKP2 2-0=100 VGAM1OUT-VD((VRP0+49R+VRHP) /sumRP KVP21
PKP2 2-0=101 VGAM1OUT-VD((VRP0+50R+VRHP) /sumRP KVP22
PKP2 2-0=110 VGAM1OUT-VD((VRP0+51R+VRHP) /sumRP KVP23
PKP2 2-0=111 VGAM1OUT-VD((VRP0+52R+VRHP) /sumRP KVP24
PKP3 2-0=000 VGAM1OUT-VD((VRP0+68R+VRHP) /sumRP KVP25
PKP3 2-0=001 VGAM1OUT-VD((VRP0+69R+VRHP) /sumRP KVP26
PKP3 2-0=010 VGAM1OUT-VD((VRP0+70R+VRHP) /sumRP KVP27
PKP3 2-0=011 VGAM1OUT-VD((VRP0+71R+VRHP) /sumRP KVP28
VINP4
PKP3 2-0=100 VGAM1OUT-VD((VRP0+72R+VRHP) /sumRP KVP29
PKP3 2-0=101 VGAM1OUT-VD((VRP0+73R+VRHP) /sumRP KVP30
PKP3 2-0=110 VGAM1OUT-VD((VRP0+74R+VRHP) /sumRP KVP31
PKP3 2-0=111 VGAM1OUT-VD((VRP0+75R+VRHP) /sumRP KVP32
PKP4 2-0=000 VGAM1OUT-VD((VRP0+80R+VRHP) /sumRP KVP33
PKP4 2-0=001 VGAM1OUT-VD((VROP0+81R+VRHP) /sumRP KVP34
PKP4 2-0=010 VGAM1OUT-VD((VRP0+82R+VRHP) /sumRP KVP35
PKP4 2-0=011 VGAM1OUT-VD((VRP0+83R+VRHP) /sumRP KVP36
VINP5
PKP4 2-0=100 VGAM1OUT-VD((VRP0+84R+VRHP) /sumRP KVP37
PKP4 2-0=101 VGAM1OUT-VD((VRP0+85R+VRHP) /sumRP KVP38
PKP4 2-0=110 VGAM1OUT-VD((VRP0+86R+VRHP) /sumRP KVP39
PKP4 2-0=111 VGAM1OUT-VD((VRP0+87R+VRHP) /sumRP KVP40
PKP5 2-0=000 VGAM1OUT-VD((VRP0+87R+VRHP+VRLP) /sumRP KVP41
PKP5 2-0=001 VGAM1OUT-VD((VRP0+91R+VRHP+VRLP) /sumRP KVP42
PKP5 2-0=010 VGAM1OUT-VD((VRP0+95R+VRHP+VRLP) /sumRP KVP43
PKP5 2-0=011 VGAM1OUT-VD((VRP0+99R+VRHP+VRLP) /sumRP KVP44
VINP6
PKP5 2-0=100 VGAM1OUT-VD((VRP0+103R+VRHP+VRLP) /sumRP KVP45
PKP5 2-0=101 VGAM1OUT-VD((VRP0+107R+VRHP+VRLP) /sumRP KVP46
PKP5 2-0=110 VGAM1OUT-VD((VRP0+111R+VRHP+VRLP) /sumRP KVP47
PKP5 2-0=111 VGAM1OUT-VD((VRP0+115R+VRHP+VRLP) /sumRP KVP48
VINP7 - VGAM1OUT-VD((VRP0+120R+VRHP+VRLP) /sumRP KVP49

SumRP=128R+VRHP+ VRLP+ VRP0+VRP1,

VD=(VGAM1OUT-VGS)
sumRPx (sumRN/ (sumRP+sumRN))]/ [sumRPx sumRN/ (sumRP+sumRN) +EXVR])

New Vision Microelectronics Inc. Page 167

PRCP0=000 VINP2-(VINP2-VINP3)*7R/28R
PRCP0=001 VINP2-(VINP2-VINP3)*9R/28R
PRCP0=010 VINP2-(VINP2-VINP3)*11R/28R
PRCP0=011 VINP2-(VINP2-VINP3)*13R/28R
VINP2_mid
PRCP0=100 VINP2-(VINP2-VINP3)*15R/28R
PRCP0=101 VINP2-(VINP2-VINP3)*17R/28R
PRCP0=110 VINP2-(VINP2-VINP3)*19R/28R
PRCP0=111 VINP2-(VINP2-VINP3)*21R/28R
PRCP1=000 VINP3-(VINP3-VINP4)*7R/44R
PRCP1=001 VINP3-(VINP3-VINP4)*9R/44R
PRCP1=010 VINP3-(VINP3-VINP4)*11R/44R
PRCP1=011 VINP3-(VINP3-VINP4)*13R/44R
VINP3A_mid
PRCP1=100 VINP3-(VINP3-VINP4)*15R/44R
PRCP1=101 VINP3-(VINP3-VINP4)*17R/44R
PRCP1=110 VINP3-(VINP3-VINP4)*19R/44R
PRCP1=111 VINP3-(VINP3-VINP4)*21R/44R
PRCP2=000 VINP3-(VINP3-VINP4)*23R/44R
PRCP2=001 VINP3-(VINP3-VINP4)*25R/44R
PRCP2=010 VINP3-(VINP3-VINP4)*27R/44R
PRCP2=011 VINP3-(VINP3-VINP4)*29R/44R
VINP3B_mid
PRCP2=100 VINP3-(VINP3-VINP4)*31R/44R
PRCP2=101 VINP3-(VINP3-VINP4)*33R/44R
PRCP2=110 VINP3-(VINP3-VINP4)*35R/44R
PRCP2=111 VINP3-(VINP3-VINP4)*37R/44R
PRCP3=000 VINP4-(VINP4-VINP5)*7R/28R
PRCP3=001 VINP4-(VINP4-VINP5)*9R/28R
PRCP3=010 VINP4-(VINP4-VINP5)*11R/28R
PRCP3=011 VINP4-(VINP4-VINP5)*13R/28R
VINP4_mid
PRCP3=100 VINP4-(VINP4-VINP5)*15R/28R
PRCP3=101 VINP4-(VINP4-VINP5)*17R/28R
PRCP3=110 VINP4-(VINP4-VINP5)*19R/28R
PRCP3=111 VINP4-(VINP4-VINP5)*21R/28R

Voltage Calculation Formula of Grayscale Voltage (Positive Polarity)

P_Grayscale Formula
V0 VINP0
V1 VINP1
V2 VINP1-(VINP1-VINP2)*72/192
V3 VINP1-(VINP1-VINP2)*114/192
V4 VINP1-(VINP1-VINP2)*137/192
V5 VINP1-(VINP1-VINP2)*159/192
V6 VINP1-(VINP1-VINP2)*172/192

New Vision Microelectronics Inc. Page 168

V7 VINP1-(VINP1-VINP2)*182/192
V8 VINP2
V9 VINP2-(VINP2-VINP2_mid)*6/48
V10 VINP2-(VINP2-VINP2_mid)*15/48
V11 VINP2-(VINP2-VINP2_mid)*30/48
V12 VINP2-(VINP2-VINP2_mid)*37/48
V13 VINP2-(VINP2-VINP2_mid)*44/48
V14 VINP2_mid
V15 VINP2_mid-(VINP2_mid-VINP3)*8/48
V16 VINP2_mid-(VINP2_mid-VINP3)*16/48
V17 VINP2_mid-(VINP2_mid-VINP3)*24/48
V18 VINP2_mid-(VINP2_mid-VINP3)*32/48
V19 VINP2_mid-(VINP2_mid-VINP3)*40/48
V20 VINP3
V21 VINP3-(VINP3-VINP3A_mid)*6/72
V22 VINP3-(VINP3-VINP3A_mid)*16/72
V23 VINP3-(VINP3-VINP3A_mid)*28/72
V24 VINP3-(VINP3-VINP3A_mid)*40/72
V25 VINP3-(VINP3-VINP3A_mid)*48/72
V26 VINP3-(VINP3-VINP3A_mid)*56/72
V27 VINP3-(VINP3-VINP3A_mid)*64/72
V28 VINP3A_mid
V29 VINP3A_mid-(VINP3A_mid-VINP3B_mid)*8/48
V30 VINP3A_mid-(VINP3A_mid-VINP3B_mid)*16/48
V31 VINP3A_mid-(VINP3A_mid-VINP3B_mid)*21/48
V32 VINP3A_mid-(VINP3A_mid-VINP3B_mid)*27/48
V33 VINP3A_mid-(VINP3A_mid-VINP3B_mid)*32/48
V34 VINP3A_mid-(VINP3A_mid-VINP3B_mid)*40/48
V35 VINP3B_mid
V36 VINP3B_mid-(VINP3B_mid-VINP4)*7/72
V37 VINP3B_mid-(VINP3B_mid-VINP4)*14/72
V38 VINP3B_mid-(VINP3B_mid-VINP4)*21/72
V39 VINP3B_mid-(VINP3B_mid-VINP4)*28/72
V40 VINP3B_mid-(VINP3B_mid-VINP4)*33/72
V41 VINP3B_mid-(VINP3B_mid-VINP4)*42/72
V42 VINP3B_mid-(VINP3B_mid-VINP4)*62/72
V43 VINP4
V44 VINP4-(VINP4-VINP4_mid)*6/48
V45 VINP4-(VINP4-VINP4_mid)*12/48
V46 VINP4-(VINP4-VINP4_mid)*16/48
V47 VINP4-(VINP4-VINP4_mid)*24/48
V48 VINP4-(VINP4-VINP4_mid)*36/48
V49 VINP4_mid

New Vision Microelectronics Inc. Page 169

V50 VINP4_mid-(VINP4_mid-VINP5)*11/48
V51 VINP4_mid-(VINP4_mid-VINP5)*16/48
V52 VINP4_mid-(VINP4_mid-VINP5)*18/48
V53 VINP4_mid-(VINP4_mid-VINP5)*24/48
V54 VINP4_mid-(VINP4_mid-VINP5)*38/48
V55 VINP5
V56 VINP5-(VINP5-VINP6)*15/192
V57 VINP5-(VINP5-VINP6)*30/192
V58 VINP5-(VINP5-VINP6)*40/192
V59 VINP5-(VINP5-VINP6)*60/192
V60 VINP5-(VINP5-VINP6)*80/192
V61 VINP5-(VINP5-VINP6)*120/192
V62 VINP6
V63 VINP7

Make sure DDVDH-V00.5 and DDVDH-V81.1V

Relationship between RAM data and voltage output levels

RAM data and the output voltage relationship (REV = 1)

New Vision Microelectronics Inc. Page 170

Source output and Vcom relationship

9.9. Voltage Generation

The pattern diagram of voltage setting and an example of waveforms of NV3029C are as follows.

New Vision Microelectronics Inc. Page 171

Note: The DDVDH, VGH and VGL output voltages will become lower than their theoretical levels
(ideal voltages) due to current consumption at each output level. The voltage levels in the
following relationships (DDVDH – VREG1OUT) 0.5V and (VCOMDC – GND) 0.5V are
the actual voltage levels. When the alternating cycle of VCOM is set high (e.g., the
polarity inverts at every line cycle), current consumption will increase. In this case, check
the voltage before use.

VGH

VREG1OUT
VcomDC
Vcom
VRS
Sn (Source driver output)
Gn
(panel Interface output)
VGL

New Vision Microelectronics Inc. Page 172

9.10. Reset
9.10.1. Registers

The registers that are initialized are listed below.

After H/W
After Power On After S/W Reset
Reset
Frame Memory Random No Change No Change
Sleep In In In
Display mode Normal Normal Normal
Display Off Off Off
Idle Off Off Off
Column Start Address 0000h 0000h 0000h
If MADCTL’s B5=0:00EFh
Column End Address 00EFh 00EFh
If MADCTL’s B5=1:013Fh
Page Start Address 0000h 0000h 0000h
If MADCTL’s B5=0:013Fh
Page End Address 013Fh 013Fh
If MADCTL’s B5=1:00EFh
Partial Area Start 0000h 0000h 0000h
Partial Area End 013Fh 013Fh 013Fh
Memory Data Access Control 00h 00h No Change
RDDPM 08h 08h 08h
RDDMADCTL 00h 00h No Change
RDDCOLMOD 06h 06h No Change
RDDIM 00h 00h 00h
RDDSM 00h 00h 00h
RDDSDR 00h 00h 00h
FMARK Output Line Off Off Off
FMARK Line Mode Mode 1(3) Mode 1(3) Mode 1(3)
Note:
1. There will be no abnormal visible effects on the display when S/W or H/W Resets are applied.
2. After Powered-on Reset finishes within 10us after both VDD & IOVcc are applied.
3. Mode 1 means Tearing Effect Output Line consists of V-Sync Information only.

9.10.2 Module Input/Output Pins

9.10.2.1 Output Pins, I/O Pins

New Vision Microelectronics Inc. Page 173

After Hardware After Software

After Power On
Reset Reset
FMARK Line High High High
D[15…0](output driver) High-Z(inactive) High-Z(inactive) High-Z(inactive)
Note: There will be no output from D[15…0] during Power On/Off sequence, Hardware Reset and
Software Reset.

9.10.2.2. Input Pins

After After
During Power After During
Hardware Software
On Process Power On Power Off
Reset Reset
REST See 8.4 Input valid Input valid Input valid See 8.4
CS Input valid Input valid Input valid Input valid Input valid
DC Input valid Input valid Input valid Input valid Input valid
IM0 Input valid Input valid Input valid Input valid Input valid
WR Input valid Input valid Input valid Input valid Input valid
RD Input valid Input valid Input valid Input valid Input valid
D[15…0]
Input valid Input valid Input valid Input valid Input valid
(Input driver)
9.10.2.3. Reset Timing

Signal Symbol Parameter Min Max Unit

RESET tRW Reset pulse duration 10 us
5(note 5) ms
tRT Reset cancel
120(note 6,7) ms
Notes:

New Vision Microelectronics Inc. Page 174

1. The reset cancel includes also required time for loading ID bytes, VCOM setting and other
settings from EEPROM to registers. This loading is done every time when there is HW reset
cancel time(RT) within 5ms after a rising edge of RESET.
2. Spice due to and electrostatic discharge on RESET line does not cause irregular system reset
according to the table below:
RESET pulse Action
Shorter than 5us Reset Rejected
Longer than 10us Reset
Between 5us and 9us Reset starts
3. During the Resetting period, the display will be blanked (the display is entering blanking
sequence, which maximum time is 120ms, when Reset Starts in Sleep Out-mode. The display
remains the blank state in sleep in-mode.) and then return to Default condition for Hardware
Reset.
4. Spike Rejection also applies during a valid reset pulse as shown below:

5. When Reset applied during Sleep In Mode.

6. When Reset applied during Sleep Out Mode.
7. It is necessary to wait 5msec after releasing RESET before sending commands. Also Sleep
Out command cannot be sent for 120 msec.

New Vision Microelectronics Inc. Page 175

10. Application

New Vision Microelectronics Inc. Page 176

11. Electrical Characteristics

11.1. Absolute Maximum Ratings

Item Symbol Unit Ratings Notes

Power-supply voltage(1) Vci,IOVcc V -0.3 to +3.6 1,2
Power-supply voltage(2) Vci-GNDA V -0.3 to +3.6 1,3
Power-supply voltage(3) DDVDH-GNDA V -0.3 to +6.0 1,4
Power-supply voltage(4) VGH-VGL V -0.3 to +30.0 1,4
Power-supply voltage(5) GNDA-VGL V +3.0 to +13.0 1,7
Power-supply voltage(6) DDVDH-VGL V +4.0 to +19.0 1,5
Power-supply voltage(7) Vci-VGL V +3.0 to + 16.8 1,7
Power-supply voltage(7) VCOMH-VCOML V +3.0 to + 6.0 1,8
Input voltage Vt V -0.3 to 3.9 1
Operating temperature Topr ℃ -40 to +85 1,8
Storage temperature Tstg ℃ -55 to +110 1

11.2. DC Characteristic

Vci = 2.4 ~ 3.3V, IOVcc = 1.65~3.3V, Ta = -40 ~ 85 °C

Item Symbol Unit Test Condition Min. Typ. Max. Note

0.8* IOVc
Input high voltage VIH V IOVcc = 1.65V ~ 3.3 V - 2,3
IOVcc c
0.2*
Input low voltage VIL V IOVcc = 1.65V ~ 3.3 V – 0.3V - IOVc 2,3
c
Output high voltage 0.8 *
VOH V IOH = -0.1mA - - 2
(D0-17 pins, FMARK) IOVcc

0.2*
Output low voltage IOVcc = 1.65 ~ 2.4 V
VOL V - - IOVc 2
(D0-17 pins, FMARK) IOL = 0.1mA
c
I/O leak current ILi µA Vin = 0 ~ IOVcc -1 1 4

Current consumption Vci=IOVcc=Vci=2.8V,

during normal operation Ta=25C,
IOP(Vci) mA - 3 -
(Vci-GNDD)+(IOVcc- Fosc=6MHZ(320
GND) Line)GRAM data

New Vision Microelectronics Inc. Page 177

=0000h, Frame
rate=70HZ, REV=0,
Current consumption SAP=100,AP=100,DC0=
during standby operation 000,DC1=010,B/C=0,
IOP(Vci) µA - 45 5,6
(Vci-GNDD)+(IOVcc- VC=001,VRH=0011,
GND) VCM=10011,VDV=10000
,VCOMG=1,CL=0, NO
panel load
Notes: 1.If used beyond the absolute maximum ratings, the LSI may permanently be damaged. It is
strongly recommended to use the LSI within the electrical characteristics conditions in
normal operation. Exposure to a condition not within the electrical characteristics may
affect reliability of the device.
2. Make sure (RVci=Vci) (high) ≥ GND (low) and IOVcc (high) ≥ GND (low).
3. Make sure Vci (high) ≥ GNDA (low).
4. Make sure DDVDH (high) ≥ GNDA (low).
5. Make sure DDVDH (high) ≥ VGL (low).
6. Make sure VGH (high) ≥ GNDA (low).
7. Make sure GNDA (high) ≥ VGL (low).
8. Make sure VCOMH(high) ≥ VCOML (low).
9. The DC/AC characteristics of die and wafer products are guaranteed at 85 ºC.

11.3. AC Characteristics

80-system Bus Interface Timing Characteristics (16-bit Transfer Mode)

IOVcc = 1.65V to 3.30V, Vci = 2.4V ~ 3.3V

Item symbol Unit Min. Typ. Max.
Write tCYCW ns 125 - -
Bus cycle time
Read tCYCR ns 450 - -
Write (RS~CS, WR) 0
Setup time Read (RS~CS, tAS ns - -
10
RD*)

Write high-level pulse width ns 70 - -

PWHW

New Vision Microelectronics Inc. Page 178

Read high-level pulse width ns 250 - -

PWHR
Write/Read rise/fall time tWRr ,tWRf ns - - 25
Address hold time tAH ns 2 - -
Write data setup time tDSW ns 20 - -
Write data hold time tH ns 10 - -
Read data delay time tDD ns - - 150
Read data hold time tDHR ns 5 - -
Write low-level pulse width PWLW ns 45 - 500
Read low-level pulse width PWLR ns 170 - -

80-system Bus Interface Timing Characteristics (8-bit Transfer Mode)

IOVcc = 1.65V to 3.30V, Vci = 2.4V ~3.3V

Item symbol Unit Min. Typ. Max.
Write tCYCW ns 70 - -
Bus cycle time
Read tCYCR ns 450 - -
Write (RS~CS, WR) 0
Setup time tAS ns - -
Read (RS~CS, RD) 10

Write high-level pulse width ns 25 - -

PWHW
Read high-level pulse width ns 250 - -
PWHR
tWRr ,tWR
Write/Read rise/fall time ns - - 25
f

Address hold time tAH ns 2 - -

Write data setup time tDSW ns 20 - -
Write data hold time tH ns 10 - -
Read data delay time tDD ns - - 150
Read data hold time tDHR ns 5 - -
Write low-level pulse width PWLW ns 30 - -
Read low-level pulse width PWLR ns 170 - -

New Vision Microelectronics Inc. Page 179

Liquid crystal driver Output Characteristics

symbo Max
Item Unit Test Condition Min. Typ. Note
l .
Vci=3.00v,DDVDH=5.50V
VREG1OUT=5.00V,
RC oscillation fosc=6MHZ (drive
Tdd1 us - - 17 10
320 lines),Ta=25℃
REV=0,AP=010,SAP=010,
VRP14-00=0,VRN14-00=0,
Source- PKP52-00=0,PKN52-00=0,
drive output PRP12-00=0,PRN12-00=0,
delay time Load resistance R=10kΩ,
Load capacitance C=20Pf
Tdd2 us Time to reach the target voltage - - 17 11
level+/-35mv from VCOM Polarity
inversion timing
Transient from a same grayscale
at all source pins

11.4. Timing Characteristics Diagram

80-system Bus Interface Operation

New Vision Microelectronics Inc. Page 180

Information furnished is believed to be accurate and reliable. However, New Vision Microelectronics Inc.
assumes no responsibility for the consequences of use of such information nor for any infringement of patents
or other rights of third parties, which may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of New Vision Microelectronics Inc. Specifications mentioned in this
publication are subject to change without notice. This publication supersedes and replaces all information if
previously supplied.

New Vision Microelectronics Inc. Page 181

Revision history

Version No. Date Page Introduction

0.0 2012-09-10 All New build

0.1 2012-10-18 173 Update register definition

82, 84,
Update MCU WR setup time;
0.2 2012-12-7 86,87, add "3Ch", "3Eh", "44h", "45h", "53h", "D3h"
instruction description;
88,89

New Vision Microelectronics Inc. Page 182

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