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Lab Manual 10

The document describes a lab manual assignment to design a traffic light controller using Verilog HDL. It involves writing Verilog code to implement the control unit for the traffic light using asynchronous state machine design (ASMD) technique. The code uses parameters to define the states and always blocks to implement the state register, output logic and next state logic. The second task enhances the first by separating the design into datapath and control units modules to structure the code better.

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26 views8 pages

Lab Manual 10

The document describes a lab manual assignment to design a traffic light controller using Verilog HDL. It involves writing Verilog code to implement the control unit for the traffic light using asynchronous state machine design (ASMD) technique. The code uses parameters to define the states and always blocks to implement the state register, output logic and next state logic. The second task enhances the first by separating the design into datapath and control units modules to structure the code better.

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Thoughts
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© © All Rights Reserved
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University of Engineering
&
       Technology, Taxila
 

  

DSD  
Lab Manual# 10
 
GROUP NO 3
 
6TH SEMESTER
 
OMEGA SECTION
 
SUBMITTED TO: ENGR.ASGHAR ISMAIL
 
 
Dated;
18/07/2023
 
LAB MANUAL NO 10

Objectives:
The objective of this project is to design traffic light signal using behavioral modeling in Verilog..
The goal is to implement the Verilog code for the ripple carry adder and evaluate its functionality
and performance.

Apparatus List:
 Verilog HDL
 FPGA Development Board
 Xilinx Vivado or any other Verilog simulation and synthesis tool

Procedure:
 Design the Verilog code for the given task using behavioral modeling.
 Simulate the Verilog code to verify its correctness and functionality.
 Synthesize the Verilog code to obtain the gate-level implementation.
 Implement the synthesized design on an FPGA development board.
 Verify the functionality and performance of the adder on the FPGA.

Task No 1
Write Verilog Code for Control Unit of Traffic Light Controller using ASMD Technique

Code:

module traffic_light_controller(
input clk,
input reset,
output reg green,
output reg yellow,
output reg red
);

// Define the states


parameter S_IDLE = 2'b00;
parameter S_GREEN = 2'b01;
parameter S_YELLOW = 2'b10;
parameter S_RED = 2'b11;

// Define the state register and next state variable


reg [1:0] state_reg;
reg [1:0] state_next;

// State register update


always @(posedge clk or posedge reset) begin
if (reset)
state_reg <= S_IDLE;
else
state_reg <= state_next;
end

// Output logic
always @(state_reg) begin
case (state_reg)
S_IDLE: begin
green <= 1'b0;
yellow <= 1'b0;
red <= 1'b1;
end
S_GREEN: begin
green <= 1'b1;
yellow <= 1'b0;
red <= 1'b0;
end
S_YELLOW: begin
green <= 1'b0;
yellow <= 1'b1;
red <= 1'b0;
end
S_RED: begin
green <= 1'b0;
yellow <= 1'b0;
red <= 1'b1;
end
default: begin
green <= 1'b0;
yellow <= 1'b0;
red <= 1'b0;
end
endcase
end
// Next state logic
always @(state_reg) begin
case (state_reg)
S_IDLE: state_next <= S_GREEN;
S_GREEN: state_next <= S_YELLOW;
S_YELLOW: state_next <= S_RED;
S_RED: state_next <= S_GREEN;
default: state_next <= S_IDLE;
endcase
end

endmodule

Schematics:
RESULTS:

Task No 2
Write Verilog Code for Control Unit of Traffic Light Controller using ASMD Technique

Code:
module traffic_light_controller(
input clk,
input reset,
output reg green,
output reg yellow,
output reg red
);

// Define the states


parameter S_IDLE = 2'b00;
parameter S_GREEN = 2'b01;
parameter S_YELLOW = 2'b10;
parameter S_RED = 2'b11;

// Define the state register and next state variable


reg [1:0] state_reg;
reg [1:0] state_next;

// Define the datapath module


module datapath(
input clk,
input reset,
output reg signal
);
// Datapath logic goes here
// Example: signal <= ...;
endmodule

// Define the control unit module


module control_unit(
input clk,
input reset,
output reg [1:0] state_next
);
// Control unit logic goes here
// Example: state_next <= ...;
endmodule

// Instantiate the datapath and control unit modules


datapath dp(
.clk(clk),
.reset(reset),
.signal(signal)
);
control_unit cu(
.clk(clk),
.reset(reset),
.state_next(state_next)
);

// State register update


always @(posedge clk or posedge reset) begin
if (reset)
state_reg <= S_IDLE;
else
state_reg <= state_next;
end

// Output logic
always @(state_reg) begin
case (state_reg)
S_IDLE: begin
green <= 1'b0;
yellow <= 1'b0;
red <= 1'b1;
end
S_GREEN: begin
green <= 1'b1;
yellow <= 1'b0;
red <= 1'b0;
end
S_YELLOW: begin
green <= 1'b0;
yellow <= 1'b1;
red <= 1'b0;
end
S_RED: begin
green <= 1'b0;
yellow <= 1'b0;
red <= 1'b1;
end
default: begin
green <= 1'b0;
yellow <= 1'b0;
red <= 1'b0;
end
endcase
end

endmodule

Schematics:
RESULTS:

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