Lab Manual 10
Lab Manual 10
University of Engineering
&
Technology, Taxila
DSD
Lab Manual# 10
GROUP NO 3
6TH SEMESTER
OMEGA SECTION
SUBMITTED TO: ENGR.ASGHAR ISMAIL
Dated;
18/07/2023
LAB MANUAL NO 10
Objectives:
The objective of this project is to design traffic light signal using behavioral modeling in Verilog..
The goal is to implement the Verilog code for the ripple carry adder and evaluate its functionality
and performance.
Apparatus List:
Verilog HDL
FPGA Development Board
Xilinx Vivado or any other Verilog simulation and synthesis tool
Procedure:
Design the Verilog code for the given task using behavioral modeling.
Simulate the Verilog code to verify its correctness and functionality.
Synthesize the Verilog code to obtain the gate-level implementation.
Implement the synthesized design on an FPGA development board.
Verify the functionality and performance of the adder on the FPGA.
Task No 1
Write Verilog Code for Control Unit of Traffic Light Controller using ASMD Technique
Code:
module traffic_light_controller(
input clk,
input reset,
output reg green,
output reg yellow,
output reg red
);
// Output logic
always @(state_reg) begin
case (state_reg)
S_IDLE: begin
green <= 1'b0;
yellow <= 1'b0;
red <= 1'b1;
end
S_GREEN: begin
green <= 1'b1;
yellow <= 1'b0;
red <= 1'b0;
end
S_YELLOW: begin
green <= 1'b0;
yellow <= 1'b1;
red <= 1'b0;
end
S_RED: begin
green <= 1'b0;
yellow <= 1'b0;
red <= 1'b1;
end
default: begin
green <= 1'b0;
yellow <= 1'b0;
red <= 1'b0;
end
endcase
end
// Next state logic
always @(state_reg) begin
case (state_reg)
S_IDLE: state_next <= S_GREEN;
S_GREEN: state_next <= S_YELLOW;
S_YELLOW: state_next <= S_RED;
S_RED: state_next <= S_GREEN;
default: state_next <= S_IDLE;
endcase
end
endmodule
Schematics:
RESULTS:
Task No 2
Write Verilog Code for Control Unit of Traffic Light Controller using ASMD Technique
Code:
module traffic_light_controller(
input clk,
input reset,
output reg green,
output reg yellow,
output reg red
);
// Output logic
always @(state_reg) begin
case (state_reg)
S_IDLE: begin
green <= 1'b0;
yellow <= 1'b0;
red <= 1'b1;
end
S_GREEN: begin
green <= 1'b1;
yellow <= 1'b0;
red <= 1'b0;
end
S_YELLOW: begin
green <= 1'b0;
yellow <= 1'b1;
red <= 1'b0;
end
S_RED: begin
green <= 1'b0;
yellow <= 1'b0;
red <= 1'b1;
end
default: begin
green <= 1'b0;
yellow <= 1'b0;
red <= 1'b0;
end
endcase
end
endmodule
Schematics:
RESULTS: