University of Engineering
&
       Technology, Taxila
 

  

DSD  
Lab Manual# 12
 
GROUP NO 3
 
6 SEMESTER
TH

 
OMEGA SECTION
 
SUBMITTED TO: ENGR.ASGHAR ISMAIL
 
 
Dated;
18/07/2023
 LAB MANUAL NO 12

Objective:
Designing, Simulating and Implementing the Verilog Code for Stopwatch
Procedure:
Following is Procedure for Implementation on FPGA kit
 Writing the Source Code of module and simulating it
 Opening Elaborated Design
 Setting Constraints
 Running Synthesis
 After Successful Synthesis Running Implementation
 After Successful Implementation Generating Bit Stream
 Downloading Bit Stream to FPGA kit using Hardware Manager
Apparatus List:
 Verilog HDL
 FPGA Development Board
 Xilinx Vivado or any other Verilog simulation and synthesis tool

TASK
Verilog Code for Stopwatch.

Verilog Code:
 Source code Code for sec2

Code for sec1 module

Counter3bit(rst,inc,clk,flag,out); input
module rst,inc,clk; output reg [2:0] out; output
counter_sec1(rst,enb,clk,flag,out); input reg flag; reg [2:0]count;
rst,enb,clk; output reg [3:0] out; output always@(posedge clk)
reg flag; reg [3:0]count; begin if
always@(posedge clk) (rst==1'b1)
begin if begin
(rst==1'b1) count=3'd0;
begin out=count;
count=4'd0; end
out=count; else if(inc==1'b1) begin
end count <=count+1;
else out =count; end
if(enb==1'b0) else if
begin (count==3'd5) begin
count<=count; flag=1'b1; end else
out =count; end out =count; end
else if endmodule
(count==4'd9) begin
flag=1'b1; end
else
count=count
+1; out =count;
end
endmodule
Code for min1 Code for min2
module module
Counter4bit(rst,inc,clk,flag,out); input Counter3bit(rst,inc,clk,flag,out); input
rst,inc,clk; output reg [3:0] out; output rst,inc,clk; output reg [2:0] out; output
reg flag; reg [3:0]count; reg flag; reg [2:0]count;
always@(posedge clk) always@(posedge clk)
begin if begin if
(rst==1'b1) (rst==1'b1)
begin begin
count=4'd0; count=3'd0;
out=count; out=count;
end end
else if(inc==1'b1) else if(inc==1'b1) begin
begin count <=count+1;
count out =count; end
<=count+1; out else if
=count; end (count==3'd5) begin
else if flag=1'b1; end else
(count==4'd9) begin out =count; end
flag=1'b1; end endmodule
else out
=count; Code for Control Unit
end
endmodule module
ControlUnit(min2INC,min1INC,sec2INC,sec1ENB,min2R
Code for Datapath ST,min1RST,sec2RST,sec1RST,start,stop,rst,clk,min2CF,
min1CF,sec2CF,sec1CF);
module output reg
min2INC,min1INC,sec2INC,sec1ENB,min2RST,min1RST,
DataPath(min2,min1,sec2,sec1,min2CF,min1CF,sec2 sec2RST,sec1RST;
CF,sec1CF,min2INC,min1INC,sec2INC,sec1ENB,mi input start,stop,rst,clk,min2CF,min1CF,sec2CF,sec1CF;
n2RST,min1RST,sec2RST,sec1RST,clk); parameter reset_state = 3'b000; parameter start_state =
output [2:0] min2,sec2; 3'b001; parameter stop_state = 3'b001; parameter
output [3:0] min1,sec1; sec2CF_state = 3'b001; parameter min1CF_state =
output min2CF,min1CF,sec2CF,sec1CF; input 3'b001; parameter min2CF_state = 3'b001;
min2INC,min1INC,sec2INC,sec1ENB,min2RST,min reg [2:0] state; always@(posedge
1RST,sec2RST,sec1RST,clk; clk)
begin if(rst)
counter_sec1 s1(sec1RST,sec1ENB,clk,sec1CF,sec1); begin
state = reset_state;
Counter3bit s2(sec2RST,sec2INC,clk,sec2CF,sec2);
end else begin
Counter4bit
m1(min1RST,min1INC,clk,min1CF,min1);
Counter3bit
m2(min2RST,min2INC,clk,min2CF,min2);

Endmodule
 case(state) reset_state:
Code for Toplevel if(start)
begin
state = start_state;
module Top(min2,min1,sec2,sec1,start,stop,rst,clk); end
output [2:0] min2,sec2; output [3:0] min1,sec1; else
input start,stop,rst,clk; begin
wire state = reset_state;
min2CF,min1CF,sec2CF,sec1CF,min2INC,min1INC, end
sec2INC,sec1ENB,min2RST,min1RST,sec2RST,sec1 start_state: if(stop)
RST; begin
state = stop_state;
DataPath end
D1(min2,min1,sec2,sec1,min2CF,min1CF,sec2CF,sec else
begin
1CF,min2INC,min1INC,sec2INC,sec1ENB,min2RST,
state = start_state;
min1RST,sec2RST,sec1RST,clk); end
stop_state: if(stop)
ControlUnit begin
C1(min2INC,min1INC,sec2INC,sec1ENB,min2RST, state = stop_state;
min1RST,sec2RST,sec1RST,start,stop,rst,clk,min2CF end
,min1CF,sec2CF,sec1CF); else
begin
endmodule state = start_state;
end
sec2CF_state: if(sec1CF)
begin
state = sec2CF_state;
end else
begin
state = start_state;
end
min1CF_state: if(sec2CF)
begin
state = min1CF_state;
end begin
state = start_state;
end
min2CF_state: if(min1CF)
begin
state = min2CF_state;
end
else if(min2CF)
begin
state=reset_state;
end
else
begin
state = start_state;
end
endcase
end end
endmodule
RESULTS:

Schematics:

FPGA Implementation:

CONCLUSION:
We can conclude
The stopwatch will continue to increment the number till 59 in sec1 and sec2 respectively and as it hits 59, the
min 1 bit will be set to 1, and will turn min2 bit to 1 as the min 1 bit reaches 9, and will continue to increment
till min1 and min2 bits become 59 respectively. Reset and Stop will work accordingly.