dsPIC30F3014/4013 13.0 OUTPUT COMPARE MODULE. Tote: This dala sheal summarizes fealrea of he group of dsPIC2OF devices and isnot intended fo be a complete Feference_ source. Far mare information on the CPU, Peripherals, register descriptions and general device functional, refer to the dsPICSOF Famiy Reference ‘Manual (0370048), This section describes the output compare module and associated Operational modes. The features provided by this module are useful in applications requiring (Operational modes, such as: + Generation of Variable Width Output Pulses + Power Factor Correction Figure 13-1 depicts a block diagram of the output compare module. The key operational features of the output compare ‘module include: + Timer2 and Timer3 Selection mode + Simple Output Compare Match mode + Dual Output Compare Match mode + Simple PWM mode + Output Compare During Sieep and Idle modes + Interrupt on Output Compare/PWM Event ‘These Operating modes are determined by setting the appropriate bits in the 16-bit OCxCON SFR (where x= 1,2,3,...N). The dsPIC devices contain up to 8 compare channels (.e., the maximum value of Nis 8) ‘The dsPIC30F3014 device contains 2 compare chan- nels while the dsPIC30F4013 device contains 4 com: pare channels. ‘OCKRS and OCXR in Figure 13-1 represent the Dual ‘Compare registers. In the Dual Compare mode, the ‘OCKR register is used forthe first compare and OCxRS is used for the second compare. 13.1 Timer2 and Timer3 Selection Mode Each output compare channel can select between one: (of two 16-bit timers, Timer? o Timer’. ‘The selection of the timers is controlled by the OCTSEL bit (OCxCON«3>), Timer? is the default timer resource forthe output compare madule, FIGURE 13-1: OUTPUT COMPARE MODE BLOCK DIAGRAM ‘Set Flag bit ‘OcKIF ‘OCKRS + Oupat 5 a} z ————| OO togic He uw t Output OO% Enable 1<2:0> ‘Comparator Select OcTsEL, OcFA (orx=1,2,3 074) or OCFB From GP (forx= 5,6, 7 or 8) Timer Module TMR2<150 TMRG<15:0> 122. MATCH TaP3_MATCH Note: Where > is shown, reference is made to the registers associated withthe respective output compare channels 1 through W. '© 2004 Microchip Technology in. Advance Information 108701386-page 81dsPIC30F3014/4013 13.2 Simple Output Compare Match Mode ‘When control bits OCM<2:0> (OCxCON«2:0>) (010 of 014, the selected output compare channel is, configured for one of three simple Output Compare Match modes: + Compare forces iO pin low + Compare forces V0 pin high + Compare toggles /0 pin ‘The OCKR register is used in these modes. The OCxR register is loaded with a value and is compared to the selected incrementing timer count. When a compare ‘occurs, one of these Compare Match modes occurs. If the counter resets to zero before reaching the value in (OCR, the state of the OCx pin remains unchanged 13.3 Dual Output Compare Match Mode ‘When control bits OCM<2:0> (OCXCON«2:0>) = 100 or 102, the selected output compare channel is config- tured for one of two Dual Output Compare modes, which are: + Single Output Pulse mode * Continuous Output Pulse mode 13.3.1 SINGLE PULSE MODE For the user to configure the madule for the generation of a single output pulse, the following steps are required (assuming timer is off + Determine instruction eye time Tov. + Calculate desired pulse with value based on Tov. + Calculate time to start pulse from timer start value cof 0x0000, + Write pulse width start and stop times into OCxR and OCxRS Compare registers (x denotes: channel 1, 2, Nl) + Set Timer Period register to value equal to, or greater than value in OCxRS Compare register, + Set OCM<2:0> = 200. + Enable timer, TON (TxCON«15>) = 1 To initiate another single pulse, issue another write to set OCM«2:0> = 299, 13.3.2. CONTINUOUS PULSE MODE For the user to configure the module for the generation of a continuous stream of outout pulses, the following steps are required + Determine instruction eyele time Tev. + Calculate desired pulse value based on Tor. + Calculate timer start pulse width from timer start value of 0x0000. + Write pulse width star and stop times into OCxR ‘and OCxRS (x denotes channel 4,2, .a!N) Compare registers, respectively. + Set Timor Period register to value equal to, or = 102, + Enable timer, TON (TxCON«15> 13.4 Simple PWM Mode When control bits OCM«2:0> (OCxCONS2:0>) = 120, (or 112, the selected output compare channel is config- tured forthe PWM mode of operation. When configured forthe PWM mode of operation, OCxR isthe main latch (ead only) and OOXRS is the secondary latch. This enables gltchiess PWM transitions, ‘The user must perform the following steps in order to configure the output compare module for PWM ‘operation 41, Setthe PWM period by writing tothe appropriate period register 2. Setthe PWM duty cycle by writing to the OCxRS. register. 3. Configure the output compare module for PWM. ‘operation, 4. Set the TMRx prescale value and enable the Timer, TON (TxCONS15>) 13.4.1 INPUT PIN FAULT PROTECTION FOR PWM When control bits OCM<2:0> (OCxCON<2:0>) = 1 the selected output compare channel is again config red for the PWM mode of operation withthe adcltional feature of input FAULT protection. While in this mode, if logic'o'is detacted on the OCFAVB pin, the respeo- tive PWM output pin is placed in the high impedance Input state. The OCFLT bit (OCxCON<4>) indicates whether a FAULT condition has occurred. This state will 'be maintained until both of the following events have ‘occurred: + The extemal FAULT condition has been removed + The PWM mode has been re-enabled by writing to the appropriate control bits s70198C-page 82 Advance Information '© 2004 Microchip Technology ne.dsPIC30F3014/4013 13.4.2 PWMPERIOD ‘The PWM period is specified by writing to the PRX register. The PWM period can be calculated using Equation 13-1 EQUATION 13-1: PWM period = [(PRx)+1]+4+Tosc+ (TMRx prescale value) PWM frequency is defined as 1 / [PWM period] FIGURE 13-2: PWM OUTPUT TIMING When the selected TMRX is equal to its respective period register, PR, the folowing four events occur on the next increment cycle: + TMRx Is cleared. + The OCx pin is set = Exception 1: If PWM duty oye is 0x0000, the OCx pin wil remain low. = Exception 2: If duty cycle is greater than PRx, the pin will remain high, + The PWM duty cycle is latched from OCxRS into Oo, + The corresponding timer interrupt flag is set. ‘Soe Figure 13-2 for key PWM period comparisons. Timer3 is referred to in Figure 13-2 for clay Periog OcxR = OCHRS TMS = Duty Cycle (0cxR}) Duty Cycle : Tans = Ps “area See (roar lg) (raurupi ia) Sean OeaRS “TRS » Duty Cycle (oc) 13.5 Output Compare Operation During CPU Sleep Mode When the CPU enters Sleep mode, al internal clocks are stopped. Therefore, when the CPU enters the Sloop state, the output compare channel wil drive the pin to the active state that was observed prior to entering the CPU Sieep state, For example, ifthe pin was high when the CPU entered the Sleep state, the pin will remain high. Likewise, ifthe pin was low when the CPU entered the Sleep state, the pin will remain low. In either case, the output compare ‘module will resume operation when the device wakes up. 13.6 Output Compare Operation During CPU Idle Mode When the CPU enters the Idle mode, the output ‘compare module can operate with ful functionality The output compare channel will operate during the CPU ale mode ifthe OCSIDL bit (OCxCON<13>) is at logic ‘o'and the selected time base (Timer2 or Timer3) is enabled and the TSIOL bit ofthe selected timer is set to logic‘. 13.7 Output Compare Interrupts ‘The output compare channels have the abilly to gener- ‘ate an interrupt on a compare match, for whichever Match mode has been selected, For all modes except the PWM mode, when a compare: ‘event occurs, the respective interrupt flag (OCxIF) is asserted and an interrupt will be generated if enabled. The OCxIF bit is located in the corresponding IFS ‘Status register and must be cleared in software. The interrupt is enabled via the respective compare inter- nupt enable (OCxIE) bit located in the coresponding IEC Control register For the PWM mode, when an event occurs, he respec tive timer interrupt fag (TIF or T3IF) is asserted and an interrupt will be generated if enabled. The IF bit is located in the IFSO Status register and must be cleared in software. The interrupt is enabled via the respective timer interrupt enable bit (TZIE or T3IE) located in the IECO Control register. The output compare interrupt flag is never set during the PWM mode of operation. '© 2004 Microchip Technology in. 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