Memory Chips and Finite State Machines
Memory Chips and Finite State Machines
Whats next?
4.2
Memory
n Address
Memory Chip
Width = word size = m bits m
Dout [m 1..0]
Din [m 1..0]
Chip select
4.3
Error Detection
parity bit
4.4
data
Parity Generator
Error Detection
comparator
data
Parity Generator
4.5
Types of Memory
Write to it off-line, read from it any time.
ROM: Read-Only Memory PROM: Programmable ROM EPROM: Erasable (by UV) PROM EEPROM: Electrically Erasable PROM RAM: Random Access Memory SRAM: Static RAM DRAM: Dynamic RAM
Write to it any time, read from it any time. 4.6
SRAM
Store each bit inside a latch and its value remains as long as the chip is powered up. Access time is fixed (may be different for read or write operations). Setup and hold times must be observed for writes.
4.7
DRAM
The bits are stored in capacitors rather than in latches. Catch: capacitors leak charge => must refresh periodically. Refreshing takes only 1% to 2% of active cycles. Cost is lower than SRAM, but access time is higher.
4.8
Sequential Logic
Combinational Logic: No memory. What extra capabilities would a circuit with memory have?
Clock
10
Whats in a state?
Study the problem and determine what information needs to be remembered by the circuit as time evolves. The state indicates the current contents of memory and what the value of any output lines the circuit may have.
4.11
11
A/000
E/100
12
4.13
13
4.14
14
W=1
W=1
15
4.16
16
A Sprinkle of Formalism
Moore Machines Circuit Output Output Generation Clock Memory
Next State
4.17
17
A Sprinkle of Formalism
Mealy Machines Output Generation Memory Circuit Output
Clock
Next State
4.18
18