More Combinational Circuits, Memory Elements and Clocks
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Alexander TaylorMore Combinational Circuits, Memory Elements and Clocks
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Alexander TaylorLecture 4
More Combinational Circuits, Memory Elements and Clocks
4.1
XNOR from NANDs and NORs
A B = AB + A B
A B
A B
(i) From NANDs: start with SOP form and apply involution. (ii) From NORs: get the 0-rows, write the maxterms and take the product, then apply involution:
F = A B = ( A + B )( A + B )
F = F = ( A + B) + ( A + B )
4.2
Multiplexer
Think of it as a multi-way switch or a selector.
I0
I1
SELECT
Out
2-to-1 MUX
4.3
Multiplexer
Question: How many bits are needed to select which input will be shown at the output?
4-to-1 MUX
4.4
Generic Design for a Multiplexer
Question: For an N-to-1 MUX, what kind of decoder will we need?
4.5
Exercise: Design a Demultiplexer
O0 In
SELECT
O1
O2
On
1-to-N DEMUX
4.6
Programmable Logic Array (PLA)
Used to implement generic functions F : 2 n 2 n directly from the SOP canonical form. They are called programmable because they have a fixed structure and the designer only has to define connections in order to implement a function.
Inputs
AND gates
Product terms
OR gates
Outputs
4.7
Inside a PLA
Inputs A B C Outputs D OR plane E F AND plane
Each column in the AND plane corresponds to a minterm. Each row in the OR plane corresponds to a sum of minterms.
E = ( ABC ) + ( A BC ) + ( ABC )
There is an electronically programmable similar component called PAL (programmable array logic).
4.8
Memory Elements
Nothing weve seen so far has the ability to store data, not even a single bit. When you remove (or change) any input, after a propagation delay, the output correspondingly changes. As we well know, a computer needs to remember pieces of information
4.9
The S-R Latch
R=0 S =0 R =1
S R
Q+0=Q Q+0=Q
Q +1 = 0 = Q Q =1
Q
no change
S =0
R=0 S =1
Q +1 = 0 = Q Q =1
not allowed
Note: state changes happen when they happen. 4.10 You cant control when.
10
Clocks
Falling edge
Clock period
Rising edge
A clock signal is a square waveform (usually symmetrical) defined by a period or cycle time. It is a reference signal that allows one to measure the passage of time. The clock rate or clock frequency is the inverse of the cycle time and is measured in Hertz:
n Hertz = n times per second
4.11
11
Clock Edges
Falling edge Clock period Rising edge
Our circuits will all be edge-triggered, that is, things happen only when clock values change for 0-to-1 or 1-to-0. Note that the clock period must be chosen so that it is long enough for all signals in a combinational circuit to stabilize.
Definition: setup time is the minimum time that the inputs must be valid before the clock edge . Definition: hold time is the minimum time during which the inputs must stay valid after the clock edge .
4.12
12
The D Flip-Flop
D
C Q Q
When the clock line transitions from 0 to 1, the value presented at the D line is read into the component and becomes the state of the flip-flop.
4.13
13
Register: More than a Single Bit
Rn
D C Q D C Q
Rn 1
D C Q
Rn 2
D Q
R0
clock
Dn
Dn 1
Dn 2
D0
4.14
14
Register File: More than a Single Register
Read register number 1 Read register number 2 Write register Write data
Register file
Read data 1
Read data 2 Write
4.15
15
Inside a Register File: Read Ports
Read register number 1 Register 0 Register 1 Register n 1 Register n Read register number 2 M u x M u x Read data 1
Read data 2
4.16
16
Inside a Register File: Write Ports
Write 0 1 Register number n-to-1 decoder n1 n C Register n 1 D C Register data D Register n C D C D Register 1 Register 0
4.17
17
