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    Datapath For The MIPS Architecture (A Single-Cycle Implementation)

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    Alexander Taylor
    Luiz Felipe Perrone Sudikoff 209 Computer Architecture Computer Science 37 Dartmouth College

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    Datapath For The MIPS Architecture (A Single-Cycle Implementation)

    Uploaded by

    Alexander Taylor
    29 views22 pages
    Luiz Felipe Perrone Sudikoff 209 Computer Architecture Computer Science 37 Dartmouth College

    Original Title

    Computer Science 37 Lecture 16

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    Luiz Felipe Perrone Sudikoff 209 Computer Architecture Computer Science 37 Dartmouth College

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    29 views22 pages

    Datapath For The MIPS Architecture (A Single-Cycle Implementation)

    Uploaded by

    Alexander Taylor
    Luiz Felipe Perrone Sudikoff 209 Computer Architecture Computer Science 37 Dartmouth College

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 22

    Lecture 16

    Datapath for the MIPS Architecture (A single-cycle implementation)

    Figure 5.1: Abstract view of the MIPS datapath

    Data Register # PC Address Instruction memory Instruction Registers Register # Register # Data Data memory

    ALU

    Address

    Clock Methodology
    State element Combinational logic

    What can we do so that we can read the state and write back to it in the same clock cycle?

    CLOCK READ WRITE

    Incrementing the Program Counter

    Add
    4 Read address Instruction Instruction memory

    PC

    Instruction

    Read data 1 Read register 2 Registers Write register Read data 2 Write data RegWrite

    Read register 1

    ALU operation

    Zero ALU ALU result

    Figure 5.7: Datapath for R-type instructions

    Figure 5.9: Load/store datapath


    3 Read data 1 ALU operation MemWrite

    Read register 1 Instruction

    Read register 2 Registers Write register Write data RegWrite 16

    Read data 2

    Zero ALU ALU result

    Address

    Read data Data memory

    Write data Sign extend 32

    MemRead

    Figure 5.10: Branch datapath

    PC + 4 from instruction datapath


    Add Sum
    Shift left 2 Read register 1 3 ALU operation

    Branch target

    Instruction

    Read data 1 Read register 2 Registers Write register Read data 2 Write data RegWrite 16 Sign extend 32

    ALU Zero

    To branch control logic

    Figure 5.12: Datapath with instruction fetch.

    Add
    4

    PC

    Read address Instruction Instruction memory

    Registers Read register 1 Read Read register 2 data 1 Read Write data 2 register Write data RegWrite 16

    3 ALUSrc
    M u x

    ALU operation

    MemWrite MemtoReg

    Zero ALU ALU result

    Address

    Read data

    Data Write memory data MemRead

    M u x

    Sign 32 extend

    Figure 5.13: Single cycle datapath for basic MIPS instructions


    PCSrc Add 4 Shift left 2 Registers Read register 1 Read Read data 1 register 2 Write register Write data RegWrite 16 Read data 2 ALUSrc 3 ALU operation Zero ALU ALU result MemWrite MemtoReg Address Read data Add ALU result M u x

    PC

    Read address Instruction Instruction memory

    M u x

    Sign extend

    32

    Data Write memory data MemRead

    M u x

    opcode lw sw beq R-type R-type R-type R-type R-type

    ALU operation Op

    funct

    ALU action ALU


    control input

    00 00 01 10 10 10 10 10

    load word store word branch eq add subtract AND OR slt

    XXXXXX add XXXXXX add XXXXXX subtract 100000 100010 100100 100101 101010 add subtract and or set on less than

    010 010 110 010 110 000 001 111

    Figure 5.14: ALU control bits for R-type instructions

    10

    ALU ALU op1 op2

    Funct field X X X X X X X X X X X X X X X X X X 0 0 0 0 0 1 X X 0 0 1 1 1 0 X X 0 1 0 0 0 1 X X 0 0 0 1 1 0

    Operation 010 110 010 110 000 001 001 111

    0 X 1 1 1 1 1 1

    0 1 X X X X X X

    Figure 5.15: Truth table for the three ALU control bits


    11

     

    Review of Instruction Formats


    6 bits 5 bits 5 bits 5 bits 5 bits 6 bits

    R-format:

    OP
    6 bits

    rs
    5 bits

    rt
    5 bits

    rd

    shamt
    16 bits

    funct

    I-format:

    OP
    6 bits

    rs

    rt
    26 bits

    address/immediate

    J-format:

    OP

    target address

    Looking at the datapath, youll see many control lines that have been left dangling up to now. We need to figure out how to set these values; the information for this will come from instructions.

    12

    Designing the Control Unit


    PCSrc 1 M u x 0 Add 4 RegWrite Instruction [2521] PC Read address Instruction [310] Instruction memory Instruction [2016] 1 M u Instruction [1511] x 0 RegDst Instruction [150] Read register 1 Read register 2 Shift left 2 MemWrite ALUSrc 1 M u x 0 Zero ALU ALU result MemtoReg Address Read data 1 M u x 0 Add ALU result

    Read data 1

    Read Write data 2 register Write Registers data 16 Sign 32 extend

    Write Data data memory MemRead

    ALU control

    Instruction [50] ALUOp

    Figure 5.17: Control lines in the datapath

    13

    Figure 5.19: Adding the control unit to the datapath


    0 M u x

    Add ALU result Add


    4 Instruction [31 26] RegDst Branch MemRead Control MemtoReg ALUOp MemWrite ALUSrc RegWrite Read address Instruction Instruction memory Instruction [25 21] Instruction [20 16] 0 M u x 1 Read register 1 Shift left 2

    PCSrc

    PC

    Read data 1 Read register 2 Registers Read Write data 2 register Write data

    Instruction [15 11]

    0 M u x 1

    Zero ALU ALU result

    Address

    Read data Data memory

    Write data

    1 M u x 0

    Instruction [15 0]

    16

    Sign extend

    32 ALU control

    Instruction [5 0]

    14

    Figure 5.21: Executing an R-type instruction fetch from instruction memory and increment the PC.
    0 M u x

    Add ALU result Add


    4 RegDst Branch MemRead Shift left 2

    Instruction

            

             

    Instruction memory

              

    PC

    Read address

                                 

    MemtoReg Control ALUOp MemWrite ALUSrc RegWrite Read register 1

    0 M u x 1

    Read data 1 Read register 2 Registers Read Write data 2 register Write data

    0 M u x 1

    Zero ALU ALU result

    Address

    Read data Data memory

    Write data

    1 M u x 0

    16

    Sign extend

    32 ALU control

    15

    Figure 5.22: Read source registers from register file.

    0 M u x

    Add ALU result Add


    4 RegDst Branch MemRead Control MemtoReg ALUOp MemWrite ALUSrc RegWrite Read address Instruction Shift left 2

            

            

    Instruction memory

             

    PC

                               

    0 M u x 1

    Read data 1 Read register 2 Registers Read Write data 2 register Write data

    Read register 1

    0 M u x 1

    Zero ALU ALU result

    Address

    Read data Data memory

    Write data

    1 M u x 0

    16

    Sign extend

    32 ALU control

    16

    Figure 5.23: ALU performs operation on register contents.

    0 M u x

    Add ALU result Add


    4 Instruction [31 26] RegDst Branch MemRead MemtoReg Control ALUOp MemWrite ALUSrc RegWrite Read address Instruction Instruction memory Instruction [25 21] Instruction [20 16] 0 M u x 1 Read register 1 Shift left 2

    PC

    Read data 1 Read register 2 Registers Read Write data 2 register Write data

    Instruction [15 11]

    0 M u x 1

    Zero ALU ALU result

    Address

    Read data Data memory

    Write data

    1 M u x 0

    Instruction [15 0]

    16

    Sign extend

    32 ALU control

    Instruction [5 0]

    17

    Figure 5.24: Finally, write result to destination register and increment the PC.
    0 M u x

    Add ALU result Add


    4 Instruction [31 26] RegDst Branch MemRead MemtoReg Control ALUOp MemWrite ALUSrc RegWrite Read address Instruction Instruction memory Instruction [25 21] Instruction [20 16] 0 M u x 1 Read register 1 Shift left 2

    PC

    Read data 1 Read register 2 Registers Read Write data 2 register Write data

    Instruction [15 11]

    0 M u x 1

    Zero ALU ALU result

    Address

    Read data Data memory

    Write data

    1 M u x 0

    Instruction [15 0]

    16

    Sign extend

    32 ALU control

    Instruction [5 0]

    18

    Designing the Control Unit


    The setting of control lines is completely determined by the instruction opcode. Question: How are opcodes determined?
    Instruction

    Opcode in binary Op5 Op4 Op3 Op2 Op1 Op0

    lw sw beq

    0 1 0

    0 0 0

    0 0 0

    0 0 1

    0 1 0

    0 1 0

    Using an opcode as input, you can define a function that produces control signals as outputs (RegDst, ALUSrc, MemtoReg, etc). The control unit in this case is simply a combinational circuit.

    19

    Performance of Single-Cycle Machines The goal: have every instruction executed in a single clock cycle. The drawback: the clock period is chosen to allow for the execution of the longest instruction. Variable clocks: is this a solution?

    20

    A Multicycle Machine
    Goal: break up the execution of an instruction into steps, where each step takes one clock cycle to complete.

    Instruction register PC Address Instruction or data Memory data register

    Data A Register # Registers Register # B Register #

    Memory

    ALU

    ALUOut

    Data

    Main differences: one memory unit for data and code, a single ALU, extra registers to hold data thats passed from one clock cycle to the next.

    21

    Figure 5.33: Complete datapath for a multicycle machine


    PCWriteCond PCSource PCWrite ALUOp IorD Outputs ALUSrcB MemRead ALUSrcA MemWrite Control RegWrite MemtoReg

    PC

    Address
    Memory MemData Write data

    Instruction Instruction Instruction register Instruction

    Memory data register

    !   # "     

    0 M u x 1

    Instruction [31-26] Instruction Read register 1 Read Read register 2 data 1 Registers Write Read register data 2 Write data A

    0 M Instruction u x 1 0 M u x 1

       

    IRWrite

    Op

    RegDst 0

    26

    Shift left 2

    28

    Jump address [31-0]

    1 u
    x 2

    !  $  # "  $    
    0 M u x 1 0 4 1 M u 2 x 3 B
    16

    PC [31-28]

    Zero ALU ALU result

    ALUOut

    Sign extend

    32

    Shift left 2

    ALU control

    22

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