Unit-3 Basic VLSI Design

VLSI DESIGN FLOW

A design flow is a sequence of operations that transform the IC designers’ intention (usually
represented in RTL format) into layout GDSII data.
A well-tuned design flow can help designers go through the chip-creation process relatively
smoothly and with a decent chance of error-free implementation. And, a skilful IC
implementation engineer can use the design flow creatively to shorten the design cycle, resulting
in a higher likelihood that the product will catch the market window.

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Front-end design (Logical design):

1. Design entry – Enter the design in to an ASIC design system using a hardware description
language (HDL) or schematic entry
2. Logic synthesis – Generation of net list (logic cells and their connections) from HDL code.
Logic synthesis consists of following steps: (i) Technology independent Logic optimization (ii)
Translation: Converting Behavioral description to structural domain (iii) Technology mapping or
Library binding
3. System partitioning - Divide a large system into ASIC-sized pieces
4. Pre-layout simulation - Check to see if the design functions correctly. Gate level
functionality and timing details can be verified.
Back-end design (Physical design):
5. Floor planning - Arrange the blocks of the netlist on the chip
6. Placement - Decide the locations of cells in a block
7. Routing - Make the connections between cells and blocks
8. Circuit Extraction - Determine the resistance and capacitance of the interconnect
9. Post-layout simulation - Check to see the design still works with the added loads of the
interconnect
Partitioning

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MOS LAYERS

MOS design is aimed at turning a specification into masks for processing silicon to meet the
specification. We have seen that MOS circuits are formed on four basic layers
 N-diffusion
 P-diffusion
 Poly Si
 Metal
which are isolated from one another by thick or thin (thinox) silicon silicon dioxide insulating
layers. The thin oxide (thinox) mask region includes n-diffusion, p-diffusion, and transistor
channels. Polysilicon and thinox regions interact so that a transistor is formed where they cross
one another.
STICK DIAGRAMS

A stick diagram is a diagrammatic representation of a chip layout that helps to abstract a model
for design of full layout from traditional transistor schematic. Stick diagrams are used to convey
the layer information with the help of a color code.
“A stick diagram is a cartoon of a layout.”
The designer draws a freehand sketch of a layout, using colored lines to represent the various
process layers such as diffusion, metal and polysilicon. Where polysilicon crosses diffusion,
transistors are created and where metal wires join diffusion or polysilicon, contacts are formed.
For example, in the case of nMOS design,
 Green color is used for n-diffusion
 Red for polysilicon
 Blue for metal
 Yellow for implant, and black for contact areas.
Monochrome encoding is also used in stick diagrams to represent the layer information.

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Stick Diagrams –NMOS Encoding

NMOS ENCODING

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CMOS ENCODING

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Stick Diagrams – Some Rules

Rule 1:

When two or more ‘sticks’ of the same type cross or touch each other that represents
electrical contact.

Rule 2:
When two or more “sticks” of different type cross or touch each other there is no electrical
contact. (If electrical contact is needed we have to show the connection explicitly)

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Rule 3:

When a poly crosses diffusion it represents a transistor.

Note: If a contact is shown then it is not a transistor.

Rule 4:

In CMOS a demarcation line is drawn to avoid touching of p-diff with n-diff. All PMOS must lie
on one side of the line and all NMOS will have to be on the other side.

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nMOS Design Style :

To understand the design rules for nMOS design style , let us consider a single metal, single

polysilicon nMOS technology.

The layout of nMOS is based on the following important features.

 n-diffusion [n-diff.] and other thin oxide regions [thinox] (green) ;

 polysilicon 1 [poly.]-since there is only one polysilicon layer here (red);

 metal 1 [metal]-since we use only one metal layer here (blue);

 implant (yellow);

 contacts (black or brown [buried]).

A transistor is formed wherever poly. crosses n-diff. (red over green) and all diffusion wires

(interconnections) are n-type (green).When starting a layout, the first step normally taken is to

draw the metal (blue) VDD and GND rails in parallel allowing enough space between them for

the other circuit elements which will be required. Next, thinox (green) paths may be drawn

between the rails for inverters and inverter based logic as shown in Fig. below. Inverters and

inverter- based logic comprise a pull-up structure, usually a depletion mode transistor, connected

from the output point to VDD and a pull down structure of enhancement mode transistors

suitably interconnected between the output point and GND. This is illustrated in the Fig.(b).

remembering that poly. (red) crosses thinox (green)wherever transistors are required. One should

consider the implants (yellow) for depletion mode transistors and also consider the length to

width (L:W) ratio for each transistor. These ratios are important particularly in nMOS and

nMOS- like circuits.

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CMOS Design Style:

The CMOS design rules are almost similar and extensions of n-MOS design rules except the
Implant (yellow) and the buried contact (brown). In CMOS design Yellow is used to identify p
transistors and wires, as depletion mode devices are not utilized. The two types of transistors 'n'
and 'p', are separated by the demarcation line (representing the p-well boundary) above which all
p-type devices are placed (transistors and wires (yellow). The n-devices (green) are consequently
placed below the demarcation line and are thus located in the p-well as shown in the diagram
below.

Diffusion paths must not cross the demarcation line and n-diffusion and p-diffusion wires

must not join. The 'n' and 'p' features are normally joined by metal where a connection is needed.

Their geometry will appear when the stick diagram is translated to a mask layout. However, one

must not forget to place crosses on VDD and Vss rails to represent the substrate and p-well

connection respectively. The design style is explained by taking the example the design of a

single bit shift register. The design begins with the drawing of the VDD and Vss rails in parallel

and in metal and the creation of an (imaginary) demarcation line in-between, as shown in

Fig.below. The n-transistors are then placed below this line and thus close to Vss, while p-

transistors are placed above the line and below VDD In both cases, the transistors are

conveniently placed with their diffusion paths parallel to the rails (horizontal in the diagram) as

shown in Fig.(b). A similar approach can be taken with transistors in symbolic form.

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Fig. CMOS stick layout design style (a,b,c,d)

The n- along with the p-transistors are interconnected to the rails using the metal and
connect as Shown in Fig.(d). It must be remembered that only metal and poly-silicon can cross
the demarcation line but with that restriction, wires can run-in diffusion also. Finally, the
remaining interconnections are made as appropriate and the control signals and data inputs are
added as shown in the Fig.(d).

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Stick Diagrams:

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Examples of Stick Diagrams

CMOS Inverter

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Contd….

Fig. CMOS NAND gate

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Design Rules and Layout

In VLSI design, as processes become more and more complex, need for the designer to
understand the intricacies of the fabrication process and interpret the relations between the
different photo masks is really troublesome. Therefore, a set of layout rules, also called design
rules, has been defined. They act as an interface or communication link between the circuit
designer and the process engineer during the manufacturing phase. The objective associated with
layout rules is to obtain a circuit with optimum yield (functional circuits versus non-functional
circuits) in as small as area possible without compromising reliability of the circuit. In addition,
Design rules can be conservative or aggressive, depending on whether yield or performance is
desired. Generally, they are a compromise between the two. Manufacturing processes have their
inherent limitations in accuracy. So the need of design rules arises due to manufacturing
problems like –
• Photo resist shrinkage, tearing.
• Variations in material deposition, temperature and oxide thickness.
• Impurities.
• Variations across a wafer.
These lead to various problems like :
• Transistor problems:
Variations in threshold voltage: This may occur due to variations in oxide thickness, ion-
implantation and poly layer. Changes in source/drain diffusion overlap. Variations in
substrate.
• Wiring problems:
Diffusion: There is variation in doping which results in variations in resistance,
capacitance. Poly, metal: Variations in height, width resulting in variations in resistance,
capacitance. Shorts and opens.
• Oxide problems:
Variations in height.
Lack of planarity.

• Via problems:
Via may not be cut all the way through.

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Undersize via has too much resistance.

Via may be too large and create short.
To reduce these problems, the design rules specify to the designer certain geometric constraints
on the layout artwork so that the patterns on the processed wafers will preserve the topology and
geometry of the designs. This consists of minimum-width and minimum-spacing constraints and
requirements between objects on the same or different layers. Apart from following a definite set
of rules, design rules also come by experience.
Why we use design rules?
• Interface between designer and process engineer
• Historically, the process technology referred to the length of the silicon channel
between the source and drain terminals in field effect transistors.
• The sizes of other features are generally derived as a ratio of the channel length,
where some may be larger than the channel size and some smaller.
For example, in a 90 nm process, the length of the channel may be 90 nm, but the width of the
gate terminal may be only 50 nm.

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Design rules define ranges for features

Examples:
• min. wire widths to avoid breaks
• min. spacing to avoid shorts
• minimum overlaps to ensure complete overlaps
– Measured in microns
– Required for resolution/tolerances of masks
Fabrication processes defined by minimum channel width
– Also minimum width of poly traces
– Defines “how fast” a fabrication process is
Types of Design Rules
The design rules primary address two issues:
1. The geometrical reproduction of features that can be reproduced by the maskmaking and
lithographical process, and
2. The interaction between different layers.
There are primarily two approaches in describing the design rules.
1. Linear scaling is possible only over a limited range of dimensions.
2. Scalable design rules are conservative .This results in over dimensioned and less dense
design.
3. This rule is not used in real life.
1. Scalable Design Rules (e.g. SCMOS, λ-based design rules):
In this approach, all rules are defined in terms of a single parameter λ. The rules are so chosen
that a design can be easily ported over a cross section of industrial process ,making the layout
portable .Scaling can be easily done by simply changing the value of.
The key disadvantages of this approach are:
2. Absolute Design Rules (e.g. μ-based design rules ) :
In this approach, the design rules are expressed in absolute dimensions (e.g. 0.75μm) and
therefore can exploit the features of a given process to a maximum degree. Here, scaling and
porting is more demanding, and has to be performed either manually or using CAD tools .Also,
these rules tend to be more complex especially for deep submicron.

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The fundamental unity in the definition of a set of design rules is the minimum line width .It
stands for the minimum mask dimension that can be safely transferred to the semiconductor
material .Even for the same minimum dimension, design rules tend to differ from company to
company, and from process to process. Now, CAD tools allow designs to migrate between
compatible processes.

• Lambda-based (scalable CMOS) design rules define scalable rules based on λ

(which is half of the minimum channel length)
– classes of MOSIS SCMOS rules: SUBMICRON, DEEPSUBMICRON
• Stick diagram is a draft of real layout, it serves as an abstract view between the
schematic and layout.
• Circuit designer in general want tighter, smaller layouts for improved performance
and decreased silicon area.
• On the other hand, the process engineer wants design rules that result in a
controllable and reproducible process.
• Generally we find there has to be a compromise for a competitive circuit to be
produced at a reasonable cost.
• All widths, spacing, and distances are written in the form
• λ = 0.5 X minimum drawn transistor length
• Design rules based on single parameter, λ
• Simple for the designer
• Wide acceptance
• Provide feature size independent way of setting outmask
• If design rules are obeyed, masks will produce working circuits
• Minimum feature size is defined as 2 λ
• Used to preserve topological features on a chip
• Prevents shorting, opens, contacts from slipping out of area to be contacted

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DESIGN RULES FOR WIRES (nMOS and CMOS)

TRANSISTOR DESIGN RULES (nMOS, pMOS and CMOS)

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CONTACT CUTS

When making contacts between poly-silicon and diffusion in nMOS circuits it should be
remembered that there are three possible approaches--poly. to metal then metal to diff., or
aburied contact poly. to diff. , or a butting contact (poly. to diff. using metal). Among the three
the latter two, the buried contact is the most widely used, because of advantage in space and a
reliable contact. At one time butting contacts were widely used , but now a days they are
superseded by buried contacts.
In CMOS designs, poly. to diff. contacts are always made via metal. A simple process is
followed for making connections between metal and either of the other two layers (as in Fig.a),
The 2λ. x 2λ. contact cut indicates an area in which the oxide is to be removed down to the
underlying polysilicon or diffusion surface. When deposition of the metal layer takes place the
metal is deposited through the contact cut areas onto the underlying area so that contact is made
between the layers.
The process is more complex for connecting diffusion to poly-silicon using the butting
contact approach (Fig.b), In effect, a 2λ. x 2λ contact cut is made down to each of the layers to
be joined. The layers are butted together in such a way that these two contact cuts become
contiguous. Since the poly-silicon and diffusion outlines overlap and thin oxide under poly
silicon acts as a mask in the diffusion process, the poly-silicon and diffusion layers are also
butted together. The contact between the two butting layers is then made by a metal overlay as
shown in the Fig.

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Fig.(a) . n-MOS & C-MOS Contacts

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Fig.(b). Contacts poly-silicon to diffusion

In buried contact basically, layers are joined over a 2λ. x 2λ. area with the buried contact cut
extending by 1λ, in all directions around the contact area except that the contact cut extension is
increased to 2λ. in diffusion paths leaving the contact area. This helps to avoid the formation of
unwanted transistors. So this buried contact approach is simpler when compared to others. The,
poly-silicon is deposited directly on the underlying crystalline wafer. When diffusion takes place,
impurities will diffuse into the poly-silicon as well as into the diffusion region within the contact
area. Thus a satisfactory connection between poly-silicon and diffusion is ensured. Buried
contacts can be smaller in area than their butting contact counterparts and, since they use no
metal layer, they are subject to fewer design rule restrictions in a layout.

Other design rules

 Double Metal MOS process Rules

 CMOS fabrication is much more complex than nMOS fabrication

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  2 um Double metal, Double poly. CMOS/BiCMOS Rules
Unit-2 1.2um Double Metal single poly.CMOS rules VLSI Circuit Design Processes

CMOS Lambda-based Design Rules:

The CMOS fabrication process is more complex than nMOS fabrication. In a CMOS
process, there are nearly 100 actual set of industrial design rules. The additional rules are
concerned with those features unique to p-well CMOS, such as the p-well and p+ mask and the
special 'substrate contacts. The p-well rules are shown in the diagram below

In the diagram above each of the arrangements can be merged into single split contacts.

From the above diagram it is also clear that split contacts may also be made with separate cuts.

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The CMOS rules are designed based on the extensions of the Mead and Conway
concepts and also by excluding the butting and buried contacts the new rules for CMOS design
are formed. These rules for CMOS design are implemented in the above diagrams.

µM CMOS Design rules

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Layout Diagrams for NMOS and CMOS Inverters and Gates

Basic Gate Design

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Layout & Stick Diagram of CMOS Inverter

2 input NAND gate

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2 input NOR gate

Scaling of MOS circuits

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Unit-2 VLSI Circuit Desig n Processes

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CURRENT DENSITY J:

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Limitations of Scaling:

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STICK DIAGRAMS WORKED EXAMPLES
 STICK DIAGRAMS WORKED EXAMPLES

ALTERNATE FORM FOR CMOS NAND GATE

STICK DIAGRAMS WORKED EXAMPLES
STICK DIAGRAMS WORKED EXAMPLES
STICK DIAGRAMS WORKED EXAMPLES
STICK DIAGRAMS WORKED EXAMPLES
STICK DIAGRAMS WORKED EXAMPLES
STICK DIAGRAMS WORKED EXAMPLES
STICK DIAGRAMS WORKED EXAMPLES
 STICK DIAGRAMS WORKED EXAMPLES

Assignment
Draw the stick diagrams for the following expressions using CMOS, NMOS,
PMOS logics.
I) (A+B+C)

II) (A+B).C

III) F= AB’ +B C’ + A’ C