DIGITAL SYSTEMS DESIGN II

Dr. Sébastien Le Beux

COEN 313 – Summer I 2023
 General Information
• Schedule
– Lectures:
• Mo/We, 8:45-11:30
• Active class participation by students is strongly encouraged
– Office hours:
• Th: 10:00- 12:00 or by appointment
– Tutorials :
• AE: Mo 14:45-16:25 - Mohsen Asghari
• AF: Th 14:45-16:25 Milad Eslaminia
– Course management
• Moodle will be used in this course for all course communication

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Grading Scheme
• 14% Individual project

• 26% Lab Works

– Refer to Laboratory Guidelines

• 20% Midterm Exam

– Wednesday May 31, from 8:45 to 9:45

• 40% Final Exam (Date and venue will be announced later)

In order to pass the class, your cumulative score must

be above 50%. COEN313 - 3
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Outline

1. Why Digital?
2. Device Technologies
3. Abstraction

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 Advantages
• Advantage of digital devices
– Reproducibility of information
– Flexibility and functionality: easier to store,
transmit and manipulate information
– Economy: cheaper device and easier to design
• Moore’s law
– Transistor geometry
– Chips double its density (number of transistors) in
every 18 months
– Devices become smaller, faster and cheaper
– Now a chip consists of billions of gates

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What is a Digital Circuit

• any digital circuit are usually made from large

assemblies of logic gates,
• A logic gate is a simple electronic representation of
Boolean logic functions

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 How to implement a digital system
• No two applications are identical and every one needs certain amount
of customization
• Basic methods for customization
• “General-purpose hardware” with custom software
- General purpose processor: e.g., performance-oriented processor
(e.g., Pentium),
- cost-oriented processor (e.g., PIC micro-controller)
• Special purpose processor: with architecture to perform a specific
set of functions: e.g., DSP processor (to do multiplication-addition),
network processor (to do buffering and routing), “graphic engine” (to
do 3D rendering)
• Custom hardware
• Custom software on a custom processor (known as hardware-software
co-design)
• Trade-off between Programmability, Coverage,Cost, Performance,
and Power consumption
• A complex application contains many different tasks and use more
than one customization methods
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Smartphone teardown – physical view

Functional part:
motherboard

https://eandt.theiet.org/content/articles/2016/12/teardown-google-pixel-xl-smartphone/

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Motherboard – physical view

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Smartphone schematic view

Block diagram of Mobile Zen- 10

COEN313
http://farhek.com/jd/h1183u1/of-mobile-zen/ss2138
Store information

Volatile memory
Non-volatile memory

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Communicate information
Antenna
Transceiver
Baseband processing

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Process information

Processors
Interfaces

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Internet of things
• From cyberphysical systems to the cloud
• Ultra-low energy embedded systems (pJ/bit) to
measure and interact autonomously with the
physical environment in real time

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2. DEVICE TECHNOLOGIES

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Fabrication of an IC
• Transistors and connection are made from many
layers (typical 10 to 15 in CMOS) built on top of
one another

• Each layer has a special pattern defined by a mask

• One important aspect of an IC is the length of a

smallest transistor that can be fabricated
– The process continues to improve, as witnessed
by Moore’s law
– The state-of-art process approaches 5nm
(known as deep sub-micron)

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Classification of device
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technologies
• Where customization is done:
– In a fab (fabrication facility): ASIC (Application
Specific IC)
– In the “field”: non-ASIC
• Classification:
– Full-custom ASIC
– Standard cell ASIC
– Gate array ASIC
– Complex field programmable logic device
– Simple field programmable logic device
– Off-the-shelf SSI (Small Scaled IC)/MSI (Medium
Scaled IC) components

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Full-custom ASIC
• All aspects (e.g., size of a transistor) of a circuit are
tailored for a particular application.
• Circuit fully optimized
• Design extremely complex and involved
• Only feasible for small components
• Masks needed for all layers
• è Analog Design

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Standard-Cell ASIC
• Circuit made of a set of pre-defined logic, known as
standard cells
• E.g., basic logic gates, 1-bit adder, D FF etc
• Layout of a cell is pre-determined, but layout of the
complete circuit is customized
• Masks needed for all layers
• è Digital Design

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Gate array ASIC

• Circuit is built from an array of a single type of cell
(known as base cell)
• Base cells are pre-arranged and placed in fixed positions,
aligned as one- or two-dimensional array
• More sophisticated components (macro cells) can be
constructed from base cells
• Masks needed only for metal layers (connection wires)

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Complex Field Programmable Device

• Device consists of an array of generic logic cells

and general interconnect structure
• Logic cells and interconnect can be “programmed”
by utilizing “semiconductor fuses or “switches”
• Customization is done “in the field”
• Two categories:
– CPLD (Complex Programmable Logic Device)
– FPGA (Field Programmable Gate Array)
• No custom mask needed
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Three viable technologies

• Standard Cell ASIC
• Gate Array ASIC
• FPGA/CPLD

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3 Comparison of technology

• Area (Size): silicon “real-estate”

– Standard cell is the smallest since the cells and
interconnect are customized
– FPGA is the largest
• Overhead for “programmability”
• Capacity cannot be completely utilized

• Speed (Performance)
– Time required to perform a task
• Power
• Cost
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Cost

• Types of cost:
– NRE (Non-Recurrent Engineering) cost: one-time,
per-design cost
– Part cost: per-unit cost
– Time-to-market “cost” loss of revenue
• Standard cell: high NRE, small part cost and large
lead time
• FPGA: low NRE, large part cost and small lead time

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5 Graph of per-unit cost

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Summary of technology

• Trade-off between optimal use of hardware

resource and design effort/cost
• No single best technology
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3. ABSTRACTION

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Abstraction
• How to manage complexity for a chip with
100 million transistors?
• Abstraction:
– simplified model
of a system
• è show the
selected features
• è Ignore
associated detail

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Level of Abstractions

• Transistor level
• Gate level
• Register transfer (RT) level
• Processor level

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 Summary

Typical Signal rep. Time Behav Phys. Desc.

blocks rep. desc.

Transistor transistor, Voltage Continu- Differential Transistor

resistor, ous equations layout
capacitors,…
Functions

And,or,xor,fl Logic 0 or 1 Propagat- Boolean Cell layout

Gate ip-flop ion delay equations

Adder,mux, Integer, Clock tick Finate State RT level floor

RT register system state Machines plan

Processor, Abstract Event,seq Algorithm IP level floor

Processor memory data type uence plan

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Why COEN313?
• To become familiar with the industry standard
in hardware design

– VHDL
– Simulation
– Logic Synthesis
– FPGA

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What will be covered?

Overview of Hardware Description Languages

Introduction to Digital Design
Basic Language constructs of VHDL
Concurrent Signal Assignment Statements of VHDL
Sequential Statement
Digital Design with VHDL
Combinational Circuit Design
Sequential Circuit Design
Finite State Machine
Algorithmic State Machine

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