Compal Confidential: Cartier DIS LA-4901P

1 2 3 4 5
A A
Compal Confidential
Schematics Document
B
Intel CLARKSFIELD/ARRANDALE B
with IBEX PEAK-M core logic
Cartier DIS
C
LA-4901P C
2009-12-01
REV:1.0
D D
S ecurity Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/09/15 Deciphered Date 2009/12/31 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Sheet
Size D o c u m ent Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
C u s t om L A -4 9 0 1 P 1 .0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D a te: T u e s day, December 15, 2009 Sheet 1 of 54
1 2 3 4 5
1 2 3 4 5
Accelerometer
Compal Confidential
File Name : LA-4901P
The rmal Sensor Fan C ontrol DP to Docking

Cartier DIS L IS302DLTR
Page 4 Page 36 Page 34

E M C 2113
Page 4
A Mobile A
XDP C onn.
LCD co nn PEG X 16 A uburndale / Clarksfield DDR3 1066/1333M Hz 1.5V DDR3-SO-DI MM X 2 Page 4
Page 19 N 1 0 M-GLM BANK 0, 1, 2, 3 Page 9,10
Socke t-rPGA989 Dual Channel

C RT Page 20,21,22,23 CK505
Page 18 37.5mm*37.5mm
Page 4,5,6,7,8 Clo ck Generator

CRT to Docking ICS9LPRS397
Page 36 V RAM
D D R3-512MB DMI X4 E-SAT A and USB Page 11
DP co nn
Page 18
Page 24,25 SATA4 comb o conn x 1(For
I/O) Page 32
USB x2 (Docking)Page 34
B E xpress Card 54 WW AN Card USB2.0
B
PCIE X1 + USB X1 PCIE X1 USB2.0 Finger Printer VFM451 daughte r board

Audio Board Page 28
Intel Ibex Peak M U SBx1 Modular Page 33
Azalia
USB conn x 3(For I/O)
1071pins BT Co nn USB x 1Page 32
25mm*27mm SATA0
PCI -E BUS
USB x1(Camara)
10/100/10 00 LAN WL AN Card Richo R5 C835 SATA1
Page 19
WLAN + PCIE X1 PCI BUS
Page 12,13,14,15,16,17
I ntel Hansville GbE Page 28
Controller MDC V1 .5 R J11
PHY Page 31 Cable
Page 26 Page 30
Audi o CKT TPA6047A

IDT 92HD75 AMP & Audio Jack
Audio Board
RJ45 CONN Audio Board
Page 27
1394 port Smar tModular
Card SD/MMC S lot
Audio Board
C SAT A ODD Connector C
Page 12
2.5" SATA HDD Connector

LPC B US Page 12 Page 34
Docking CONN.
(2) PS/ 2 Interfaces
RT C CKT. LED (2) USB 2.channels
Page 12 Audio Board (2) SATA Channels
(2) Display Port Channels
(1) Se rial Port
TPM1.2 SMSC Super I/O (1) Pa rallel Port
P ower OK CKT. SMSC KBC 1098 (1) Line In
Page 37 SLB9635TT LPC47N217 Page 36 (1) Line Out
Page 33 page 35 (1) RJ45 (10/100/1000)
(1 ) VGA
COM1 LPT (1) 2 LAN indicator LED's
Po wer On/Off CKT. Touch P ad CONN. In t.KBD ( Docking ) ( Docking ) (1) Power Button
Page 31 Page 31 Page 31 Page 34 Page 34
(1) I2C interface
D D
Track Point CONN.

Page 31
DC/DC Interface CKT.
Page 38
SPI R OM S ecurity Classification Compal Secret Data Compal Electronics, Inc.
8MB Page 33 Issued Date 2008/09/15 Deciphered Date 2009/12/31 Title
Block Diagram
C u s t om L A -4 9 0 1 P 1 .0
1 2 3 4 5
1
( O MEANS ON X MEANS OFF )

Voltage Rails Symbol Note :
+RTCVCC +B +5VALW +3VM +1.5V +5VS
+3VL +3VALW +1.05VM +0.75V +3VS
+1.5VS : means Digital Ground
power
plane +VGA_CORE
+VCCP
+CPU_CORE : means Analog Ground
+1.05VS
+1.8VS
State
S0
O O O O O O Install below 45 level BOM structure
S1 45@ : means just put it in the BOM of 45 level.
O O O O O O
S3
O O O O O X
S5 S4/AC
O O O O X X
S5 S4/ Battery only
O O X X X X Install below 43 level BOM structure
S5 S4/AC & Battery @ : means just reserve , no build
don't exist
O X X X X X
CONN@ : means ME part.
VRAM@ : means VRAM strip pin part.
A A
SMBUS Control Table
THERMAL
SOURCE BATT XDP SODIMM CLK CHIP MINI CARD DOCK NIC SENSOR G-SENSOR
SMB_EC_CK1
SMB_EC_DA1
SMSC1098 V X X X X X X X X
SMBCLK
SMBDATA
Calpella X V V V V V X X V
SML0CLK
SML0DATA
Calpella X X X X X X V X X
SML1CLK
SML1DATA
Calpella X X X X X X X V X

Notes List
C u s t om L A -4 9 0 1 P 1 .0
1
1 2 3 4 5
Layout rule ： 10mil width tr ace +VCCP +VCCP +VCCP
length < 0.5", spacing 20mil PM_EXTTS#0 R1 1 2 10K_0402_5%

JCPU1B C O NN@ 2009/02/06 HP DB-2
20_0402_1% 1 2 R2 C O M P3 AT23 PM_EXTTS#1 R3 1 2 10K_0402_5% P M _ P W R B TN#_R R 9091 @ 2 1K_0402_5%
COMP3 C L K _ BCLK
A16 C L K _ C P U_BCLK 15
BCLK
MISC
20_0402_1% 1 2 R5 C O M P2 AT24 B16 C L K _BCLK# 2008/10/09 HP
COMP2 BCLK# C L K _ C P U_BCLK# 15 + 1.5V
CLOCKS
49.9_0402_1% 1 2 R7 C O M P1 G16 AR30 C L K _ C PU_XDP X D P_TDO R 1 01 2 51_0402_5%
COMP1 BCLK_ITP C L K _ C PU_XDP#
AT30
49.9_0402_1% 1 BCLK_ITP#
2 R9 C O M P0 AT26 This shall place near XDP
1
COMP0 C L K_EXP
E16 C LK_EXP 13
PEG_CLK C LK_EXP# R 1218
D16 C LK_EXP# 13
T P _ S KTOCC# PEG_CLK# 1K_0402_5%
T2 AH24
SKTOCC# R11
A18 1 2 0_0402_5% 2009/04/13 Compal DB-3
DPLL_REF_SSCLK R13
A17 1 2 0_0402_5%
2
H _ C A T E RR# DPLL_REF_SSCLK#
A AK14 A
CATERR#
THERMAL
S S M3K7002F_SC59-3
Q 87
D
F6 3 1 D R A M R ST# 9,10
SM_DRAMRST#
15 H _ P E CI 1 R16 2 H _ P E C I_ISO AT15
0_0402_5% PECI S M _ R COMP0
AL1
SM_RCOMP[0] S M _ R COMP1
G
AM1
2
to power; PU to VCCP at power side also SM_RCOMP[1] S M _ R COMP2
AN1 P C H _ D D R _ RST 5 ,15
SM_RCOMP[2]
46 H _ P R O C HOT# 1 R17 2 H _ P R O C H OT#_D AN26
0_0402_5% PROCHOT# PM_EXTTS#0 from DDR
AN15 T3
PM_EXT_TS#[0]
DDR3
MISC
AP15 PM_EXTTS#1 R 18 1 2 0_0402_5% 2009/07/02 HP SI-1b
PM_EXT_TS#[1] PM_EXTTS#1_R 9,10
1
1
15,20 H _ T H E R MTRIP# 1 R19 2 H _ T H E R M TRIP#_R AK15
0_0402_5% THERMTRIP# R 1219 @ C 997
100K_0402_5% 470P_0402_50V8J
AT28 X D P _ P R DY# 2 2009/07/21 HP SI-2
2
PRDY# X D P _PREQ#
AP27
PREQ#
AN28 X D P_TCK
TCK
H _ C P U R ST# 1 R20 2 H _ C P U R S T#_R AP26 AP28 X DP_TMS
RESET_OBS# TMS
PWR MANAGEMENT
0_0402_5% AT27 X D P_TRST#
TRST#
JTAG & BPM

14 H _ P M _ S Y NC 1 R21 2 H _ P M _ S Y N C_R AL15 AT29 X D P_TDI
0_0402_5% PM_SYNC TDI AR27 X D P_TDO
TDO X D P_TDI_M
AR29
H_CPUPWRGD 1 R22 2 V C C P W R G O OD_1 AN14
0_0402_5% VCCPWRGOOD_1
TDI_M
TDO_M
AP29 X D P_TDO_M CPU XDP Connector
AN25 X D P _ D BRESET# JP1
DBR#
15 H _ C P U P W R G D 1 R24 2 V C C P W R G O OD_0 AN27 1 2
0_0402_5% VCCPWRGOOD_0 X D P _PREQ# GND0 GND1
3 4 C FG 8 5
X DP_BPM#0 X DP_BPM#0 R 1016 0_0402_5% X D P _ P R DY# OBSFN_A0 OBSFN_C0
AJ22 1 2 5 6 C FG 9 5
BPM#[0] OBSFN_A1 OBSFN_C1
14 P M _ D R A M _ P WRGD 1 R26 2 V D D P W R G O O D _R AK13 AK22 X DP_BPM#1
5 C F G 12
R 1017 1 @ 2 0_0402_5% 7 8
0_0402_5% SM_DRAMPWROK BPM#[1] X DP_BPM#2 X DP_BPM#1 R 1018 0_0402_5% X D P_BPM#0_R GND2 GND3
AK24 1 2 9 10 C FG 0 5
from power BPM#[2] X DP_BPM#3 R 1019 @ 0_0402_5% X D P_BPM#1_R OBSDATA_A0 OBSDATA_C0
AJ24 5 C F G 13 1 2 11 12 C FG 1 5
BPM#[3] X DP_BPM#4 X DP_BPM#2 R 1020 0_0402_5% OBSDATA_A1 OBSDATA_C1
37 V T T P W R GOOD AM15 AJ25 1 2 13 14
B VTTPWRGOOD BPM#[4] AH22 X DP_BPM#5 R 1021 1 @ 2 0_0402_5% X D P_BPM#2_R 15 GND4 GND5 16
B
BPM#[5] 5 C F G 14 OBSDATA_A2 OBSDATA_C2 C FG 2 5
AK23 X DP_BPM#6 X DP_BPM#3 R 1022 1 2 0_0402_5% X D P_BPM#3_R 17 18
BPM#[6] OBSDATA_A3 OBSDATA_C3 C FG 3 5
H _ P W R G D _XDP 1 R 3 0 2 H _ P W R G D _XDP_R AM26 AH23 X DP_BPM#7 R 1023 1 @ 2 0_0402_5% 19 20
TAPPWRGOOD BPM#[7] 5 C F G 15 GND6 GND7 + 3VS
0_0402_5% 21 22
5 C F G 17 OBSFN_B0 OBSFN_D0 C F G 10 5 2009/02/25 HP DB-2
5 C F G 16 23 24 C F G 11 5
OBSFN_B1 OBSFN_D1
15 B U F _ P LT_RST# 1 R31 2 P L T_RST#_R AL14 25 26
1.5K_0402_1% RSTIN# X DP_BPM#4 GND8 GND9
27 28 C FG 4 5
1
X DP_BPM#5 OBSDATA_B0 OBSDATA_D0
29 30 C FG 5 5
1
31 OBSDATA_B1 OBSDATA_D1 32 2008/12/12 HP DB-1 R23

2009/02/24 HP DB-2 I C , A U B _ C F D_rPGA,R1P0 +VCCP X DP_BPM#6 GND10 GND11 1K_0402_5%
33 34 C FG 6 5
R 33 R25 X DP_BPM#7 35 OBSDATA_B2 OBSDATA_D2 36
+ 1.5V OBSDATA_B3 OBSDATA_D3 C FG 7 5
750_0402_1% 1K_0402_5% 37 38
2
H_CPUPWRGD 1 2 H _ C P U P W R G D _R 39 GND12 GND13 40 C L K _ C PU_XDP + V C CP
1
2
P M _ P W R B TN#_R PWRGOOD/HOOK0 ITPCLK/HOOK4 C L K _ C PU_XDP#

12,14 P M _ P W R B TN#_R 41 42
HOOK1 ITPCLK#/HOOK5
1
C1 @ 43 44 1K_0402_5%
R 1226 @ 0 .1U_0402_16V4Z H _ P W R G D _XDP 1 VCC_OBS_AB VCC_OBS_CD X D P _RST#_R R28 H _ C P U R ST#
2 45 46 1 2
0_0402_5% 2 R27 0_0402_5% HOOK2 RESET#/HOOK6 X D P _ D BRESET#_R X D P _ D BRESET#
47 48 1 2 X D P _ D BRESET# 12,14
HOOK3 DBR#/HOOK7 R29 0_0402_5%
49 50
GND14 GND15 X D P_TDO
T110 51 52
2
V D D P W R G O O D _R R 14 1 SDA TD0
2 1.5K_0402_1% V C C P _ 1 . 5 V SPWRGD 37
2008/12/12 HP
T111 53 54 X D P_TRST#
55 SCL TRST# 56 X D P_TDI
R 15 1 TCK1 TDI
2 750_0402_1% 2009/07/02 HP SI-1b X D P_TCK 57 58 X DP_TMS
2009/04/10 HP DB-3 59 TCK0 TMS 60
GND16 GND17
SAMTE_BSH-030-01-L-D-A C ONN@
X D P _RST#_R 1 @ 2 P LT_RST# 12,15,20,26,28,31,33
JTAG MAPPING R32 0_0402_5%
Processor Pullups Thermal Sensor EMC2113-2 with CPU PWM FAN

C C
+VCCP
2009/02/06 HP DB-2 F A N _ P W M-R R 794 1 2 0_0402_5%
+ 3VS F A N _ P W M 35
H _ C A T E RR# R 3 91 2 49.9_0402_1%
21 V G A _ T H E RMDC 1
H _ P R O C H OT#_D R 4 21 2 68_0402_5% 10/16 HP Add
C 830 @
1
H _ C P U R S T#_R R 4 51 @ 2 68_0402_5% 21 V G A _ T H ERMDA U 5 4 EMC2113-2-AX_QFN16_4X4 0 .1U_0402_16V4Z
2
R 35 V G A _ T H E RMDC 1 16 R E M OTE2+ + 5 VS
68_0402_5% DN DP2/DN3
1 2 V G A _ T H ERMDA 2 15 R E MOTE2-
2
C2 2200P_0402_50V7K DP DN2/DP3 2009/07/23 Compal thermal team
1
+ 3 V S_THER 3 0.4mA 14 R38 1 2 4.53K_0402_1% 2009/02/06 HP DB-2
VDD TRIP_SET 2009/02/06 HP DB-2 R 1060
DDR3 Compensation Signals 1 2009/01/21 HP F A N _ P W M-R 4 13 R41 1 2 10K_0402_5% + 3VS 10K_0402_5%
2009/02/06 HP DB-2 PWM_IN SHDN_SEL
C3 1 2 10K_0402_5% A D D R _ SEL 5 12 1 @ 2 JP2 C ONN@
2
S M _ R COMP0 R 52 ADDR_SEL GND
1 2 100_0402_1% 0 .1U_0402_16V4Z R 1141 2008/11/17 HP R44 10K_0402_5% 1
2 F A N _ P W M _OUT R 1061 10.3A
15 T H E R M _SCI# 6 11 1 2 0_0402_5% 2
R 53 ALERT# PWM 2
S M _ R COMP1 1 2 24.9_0402_1% Close to XDP 1 2 + 3VS 3
R48 1 @ 2 10K_0402_5% 7 10 T ACH R47 10K_0402_5% 4 3
+ 3VS SYS_SHDN# TACH 4
S M _ R COMP2 R 54 1 2 130_0402_1% 5
GND
X D P_TRST# R 55 1 G5
2 51_0402_5% 9,10,11,13,32 S M B _ DATA_S3 8 9 S M B _CLK_S3 9,10,11,13,32 6
SMDATA SMCLK G6
Layout Note:Please these ACES_85205-04001
17
resistors near Processor
15,20 H _ T H E R MTRIP# H _ T H E R MTRIP# R51 1 2 0_0402_5% 2009/01/20 Compal HW
Add 0ohm and 0.1u Add in this map at 11/24
2009/02/20 HP DB-2 2009/04/10 HP DB-3
EMC2103 (default) EMC2113
REMOTE Thermal sensor Install R1060 R794,R1061

D D
Don't Install R794,R1061 R1060

1
C
R E M OTE2+ 2 Q1
B M MBT3904WH_SOT323-3
E
3
2 Layout Note:
C4
2200P_0402_50V7K place near the hottest spot area for S ecurity Classification Compal Secret Data Compal Electronics, Inc.
1 NB & top SODIMM. Issued Date 2008/09/15 Deciphered Date 2009/12/31 Title
R E MOTE2-
ARD/CFD(1/5)-Thermal/XDP
C u s t om L A -4 9 0 1 P 1 .0
1 2 3 4 5
1 2 3 4 5
Layout rule ： tra ce

length < 0.5"
JCPU1A C O NN@ JCPU1E C ONN@
1
B26 E X P _ICOMPI 1 R 56 2 49.9_0402_1%
PEG_ICOMPI
A26 AJ13
PEG_ICOMPO R 1220 @ RSVD32
14 D M I _CRX_PTX_N0 A24 B27 AJ12
DMI_RX#[0] PEG_RCOMPO E X P _RBIAS RSVD33
14 D M I _CRX_PTX_N1 C23 A25 1 R 57 2 750_0402_1% Q88 100K_0402_5%
DMI_RX#[1] PEG_RBIAS A P2302GN_SOT23
14 D M I _CRX_PTX_N2 B22 AP25
2
DMI_RX#[2] P C I E_CRX_GTX_N[0..15] 20 RSVD1
14 D M I _CRX_PTX_N3 A21 K35 P C I E_CRX_GTX_N0 AL25 AH25
DMI_RX#[3] PEG_RX#[0] P C I E_CRX_GTX_N1 RSVD2 RSVD34
J34 1 3 AL24 AK26
S
PEG_RX#[1] + V _ D D R _ C P U_REF0 RSVD3 RSVD35
14 D M I_CRX_PTX_P0 B24 J33 P C I E_CRX_GTX_N2 AL22
DMI_RX[0] PEG_RX#[2] P C I E_CRX_GTX_N3 RSVD4
14 D M I_CRX_PTX_P1 D23 G35 AJ33 AL26
DMI_RX[1] PEG_RX#[3] RSVD5 RSVD36
DMI
B23 G32 P C I E_CRX_GTX_N4 AG9 AR2
G
14 D M I_CRX_PTX_P2
2
DMI_RX[2] PEG_RX#[4] P C I E_CRX_GTX_N5 RSVD6 RSVD_NCTF_37
A 14 D M I_CRX_PTX_P3 A22 F34 M27 A
DMI_RX[3] PEG_RX#[5] P C I E_CRX_GTX_N6 RSVD7
F31 L28 AJ26
PEG_RX#[6] P C I E_CRX_GTX_N7 RSVD8 RSVD38
14 D M I _CTX_PRX_N0 D24 D35 J17 AJ27
DMI_TX#[0] PEG_RX#[7] P C I E_CRX_GTX_N8 SA_DIMM_VREF RSVD39
G24 E33 1 3 H17
S
14 D M I _CTX_PRX_N1 DMI_TX#[1] PEG_RX#[8] + V _ D D R _ C P U_REF1 SB_DIMM_VREF
F23 C33 P C I E_CRX_GTX_N9 A P 2302GN_SOT23 G25
14 D M I _CTX_PRX_N2 DMI_TX#[2] PEG_RX#[9] RSVD11
H23 D32 P C I E_CRX_GTX_N10 Q 89 G17
14 D M I _CTX_PRX_N3 DMI_TX#[3] PEG_RX#[10] RSVD12
1
B32 P C I E_CRX_GTX_N11 E31 AP1
G
2
PEG_RX#[11] P C I E_CRX_GTX_N12 RSVD13 RSVD_NCTF_40
14 D M I_CTX_PRX_P0 D25 C31 E30 AT2
DMI_TX[0] PEG_RX#[12] P C I E_CRX_GTX_N13 2009/07/21 HP SI-2 R 1222 @ RSVD14 RSVD_NCTF_41
14 D M I_CTX_PRX_P1 F24 B28
DMI_TX[1] PEG_RX#[13] P C I E_CRX_GTX_N14 100K_0402_5%
14 D M I_CTX_PRX_P2 E23 B30 AT3
G23 DMI_TX[2] PEG_RX#[14] A31 P C I E_CRX_GTX_N15 RSVD_NCTF_42 AR1
2
14 D M I_CTX_PRX_P3 DMI_TX[3] PEG_RX#[15] RSVD_NCTF_43
P C I E_CRX_GTX_P[0..15] 20
J35 P C IE_CRX_GTX_P0 4,15 P C H _ D D R _ RST
PEG_RX[0] P C IE_CRX_GTX_P1
H34
PEG_RX[1] P C IE_CRX_GTX_P2
H33 AL28
PEG_RX[2] P C IE_CRX_GTX_P3 C FG 0 RSVD45
E22 F35 4 C FG 0 AM30 AL29
FDI_TX#[0] PEG_RX[3] P C IE_CRX_GTX_P4 C FG 1 CFG[0] RSVD46
D21 G33 4 C FG 1 AM28 AP30
FDI_TX#[1] PEG_RX[4] P C IE_CRX_GTX_P5 C FG 2 CFG[1] RSVD47
D19 E34 4 C FG 2 AP31 AP32
D18 FDI_TX#[2] PEG_RX[5] F32 P C IE_CRX_GTX_P6 C FG 3 AL32 CFG[2] RSVD48 AL27
FDI_TX#[3] PEG_RX[6] 4 C FG 3 CFG[3] RSVD49
G21 D34 P C IE_CRX_GTX_P7 C FG 4 AL30 AT31
PCI EXPRESS -- GRAPHICS

E19 F33 P C IE_CRX_GTX_P8 C FG 5 AM31 AT32
F21 B33 P C IE_CRX_GTX_P9 C FG 6 AN29 AP33
Intel(R) FDI
G18 D31 P C IE_CRX_GTX_P10 C FG 7 AM32 AR33
A32 P C IE_CRX_GTX_P11 C FG 8 AK32 AT33
PEG_RX[11] 4 C FG 8 CFG[8] RSVD_NCTF_54
C30 P C IE_CRX_GTX_P12 C FG 9 AK31 AT34
RESERVED
PEG_RX[12] 4 C FG 9 CFG[9] RSVD_NCTF_55
D22 A28 P C IE_CRX_GTX_P13 C F G 10 AK28 AP35
FDI_TX[0] PEG_RX[13] 4 CFG 1 0 CFG[10] RSVD_NCTF_56
C21 B29 P C IE_CRX_GTX_P14 C F G 11 AJ28 AR35
FDI_TX[1] PEG_RX[14] 4 CFG 1 1 CFG[11] RSVD_NCTF_57
D20 A30 P C IE_CRX_GTX_P15 C F G 12 AN30 AR32
FDI_TX[2] PEG_RX[15] 4 CFG 1 2 CFG[12] RSVD58
C18 C F G 13 AN32
FDI_TX[3] P C I E_CTX_GRX_N[0..15] 20 4 CFG 1 3 CFG[13]
G22 L33 P C I E _CTX_GRX_C_N0 C5 1 2 0.1U_0402_10V7K P C I E_CTX_GRX_N0 C F G 14 AJ32
FDI_TX[4] PEG_TX#[0] 4 CFG 1 4 CFG[14]
E20 M35 P C I E _CTX_GRX_C_N1 C6 1 2 0.1U_0402_10V7K P C I E_CTX_GRX_N1 C F G 15 AJ29 E15
FDI_TX[5] PEG_TX#[1] 4 CFG 1 5 CFG[15] RSVD_TP_59
F20 M33 P C I E _CTX_GRX_C_N2 C7 1 2 0.1U_0402_10V7K P C I E_CTX_GRX_N2 C F G 16 AJ30 F15
FDI_TX[6] PEG_TX#[2] 4 CFG 1 6 CFG[16] RSVD_TP_60
G19 M30 P C I E _CTX_GRX_C_N3 C8 1 2 0.1U_0402_10V7K P C I E_CTX_GRX_N3 C F G 17 AK30 A2
FDI_TX[7] PEG_TX#[3] 4 CFG 1 7 CFG[17] KEY
L31 P C I E _CTX_GRX_C_N4 C9 1 2 0.1U_0402_10V7K P C I E_CTX_GRX_N4 T22 C F G 18 H16 D15
R 58 PEG_TX#[4] RSVD_TP_86 RSVD62
1 2 1K_0402_5% F17 K32 P C I E _CTX_GRX_C_N5 C10 1 2 0.1U_0402_10V7K P C I E_CTX_GRX_N5 C15
B
R 59 1 2 1K_0402_5% E17 FDI_FSYNC[0] PEG_TX#[5] M29 P C I E _CTX_GRX_C_N6 C11 1 2 0.1U_0402_10V7K P C I E_CTX_GRX_N6 RSVD63 AJ15 R60 1 @ 2 0_0402_5%
B
FDI_FSYNC[1] PEG_TX#[6] C12 0.1U_0402_10V7K RSVD64 R61 @
J31 P C I E _CTX_GRX_C_N7 1 2 P C I E_CTX_GRX_N7 AH15 1 2 0_0402_5%
R 62 1 2 1K_0402_5% C17 PEG_TX#[7] K29 P C I E _CTX_GRX_C_N8 C13 1 2 0.1U_0402_10V7K P C I E_CTX_GRX_N8 RSVD65
FDI_INT PEG_TX#[8] P C I E _CTX_GRX_C_N9 C14 0.1U_0402_10V7K P C I E_CTX_GRX_N9
H30 1 2 B19
R 63 PEG_TX#[9] RSVD15
1 2 1K_0402_5% F18 H29 P C I E_CTX_GRX_C_N10 C15 1 2 0.1U_0402_10V7K P C I E_CTX_GRX_N10 A19 2009/02/19 HP DB-2
R 64 FDI_LSYNC[0] PEG_TX#[10] RSVD16
1 2 1K_0402_5% D17 F29 P C I E_CTX_GRX_C_N11 C16 1 2 0.1U_0402_10V7K P C I E_CTX_GRX_N11
FDI_LSYNC[1] PEG_TX#[11] C17 0.1U_0402_10V7K R 65 @
E28 P C I E_CTX_GRX_C_N12 1 2 P C I E_CTX_GRX_N12 1 2 0_0402_5% A20
PEG_TX#[12] P C I E_CTX_GRX_C_N13 C18 0.1U_0402_10V7K P C I E_CTX_GRX_N13 R 66 @ RSVD17
D29 1 2 1 2 0_0402_5% B20
PEG_TX#[13] D27 P C I E_CTX_GRX_C_N14 C19 1 2 0.1U_0402_10V7K P C I E_CTX_GRX_N14 RSVD18 AA5
PEG_TX#[14] P C I E_CTX_GRX_C_N15 C20 0.1U_0402_10V7K P C I E_CTX_GRX_N15 RSVD_TP_66
C26 1 2 U9 AA4
PEG_TX#[15] T9 RSVD19 RSVD_TP_67 R8
P C IE_CTX_GRX_P[0..15] 20 RSVD20 RSVD_TP_68
L34 P C I E_CTX_GRX_C_P0 C21 1 2 0.1U_0402_10V7K P C IE_CTX_GRX_P0 AD3
PEG_TX[0] M34 P C I E_CTX_GRX_C_P1 C22 1 2 0.1U_0402_10V7K P C IE_CTX_GRX_P1 AC9 RSVD_TP_69 AD2
PEG_TX[1] P C I E_CTX_GRX_C_P2 C23 0.1U_0402_10V7K P C IE_CTX_GRX_P2 RSVD21 RSVD_TP_70
M32 1 2 AB9 AA2
L30 1 2 AA1
PEG_TX[3] M31 P C I E_CTX_GRX_C_P4 C25 0.1U_0402_10V7K P C IE_CTX_GRX_P4 RSVD_TP_72
1 2 R9
PEG_TX[4] P C I E_CTX_GRX_C_P5 C26 0.1U_0402_10V7K P C IE_CTX_GRX_P5 RSVD_TP_73
K31 1 2 AG7
M28 1 2 C1 AE3
PEG_TX[6] P C I E_CTX_GRX_C_P7 C28 0.1U_0402_10V7K P C IE_CTX_GRX_P7 RSVD_NCTF_23 RSVD_TP_75
H31 1 2 A3
PEG_TX[7] P C I E_CTX_GRX_C_P8 C29 0.1U_0402_10V7K P C IE_CTX_GRX_P8 RSVD_NCTF_24
K28 1 2
PEG_TX[8] G30 P C I E_CTX_GRX_C_P9 C30 0.1U_0402_10V7K P C IE_CTX_GRX_P9
1 2 V4
G29 1 2 V5
PEG_TX[10] F28 P C I E_CTX_GRX_C_P11 C32 1 2 0.1U_0402_10V7K P C IE_CTX_GRX_P11 RSVD_TP_77 N2
PEG_TX[11] E27 P C I E_CTX_GRX_C_P12 C33 0.1U_0402_10V7K P C IE_CTX_GRX_P12 RSVD_TP_78
1 2 J29 AD5
D28 1 2 J28 AD7
C27 1 2 W3
C25 1 2 A34 W2
PEG_TX[15] RSVD_NCTF_28 RSVD_TP_82
A33 N3
RSVD_NCTF_29 RSVD_TP_83
AE5
RSVD_TP_84
C35 AD9
I C , A U B _ C F D _rPGA,R1P0 RSVD_NCTF_30 RSVD_TP_85
B35
RSVD_NCTF_31
AP34
VSS
C C
CFG Straps for PROCESSOR I C , A U B _ C F D_rPGA,R1P0
C FG 0 R67 1 @ 2 3.01K_0402_1% C FG 7 R68 1 @ 2 3.01K_0402_1%

Only temporary for early CFD samples (rPGA/BGA)
PCI-Express Configuration Select
1: Single PEG
CFG0 0: Bifurcation enabled
Not applicable for Clarksfield Processor
C FG 3 R69 1 2 3.01K_0402_1%
CFG3-PCI Express Static Lane Reversal

1: Normal Operation
CFG3 0: Lane Numbers Reversed
15 -> 0, 14 ->1, .....
C FG 4 R70 1 @ 2 3.01K_0402_1%
CFG4-Display Port Presence

1: Disabled; No Physical Display Port
attached to Embedded Display Port
CFG4
0: Enabled; An external Display Port
device is connected to the Embedded
D D
Display Port

ARD/CFD(2/5)-DMI/PEG/FDI
C u s t om L A - 4901P 1 .0
1 2 3 4 5
1 2 3 4 5
J CPU1D C ONN@
J CPU1C C ONN@
10 D D R _ B _ D[0..63] W8 M _ C L K _DDR2 10
SB_CK[0]
AA6 M _ C L K _DDR0 9 W9 M _ C L K _DDR#2 10
SA_CK[0] D D R _ B _D0 SB_CK#[0]
A
9 D D R _ A _ D[0..63] AA7 M _ C L K _DDR#0 9 B5 M3 D D R _ C K E 2 _DIMMB 10
A
SA_CK#[0] D D R _ B _D1 SB_DQ[0] SB_CKE[0]
P7 D D R _ C K E 0 _DIMMA 9 A5
D D R _ A _D0 SA_CKE[0] D D R _ B _D2 SB_DQ[1]
A10 C3
D D R _ A _D1 SA_DQ[0] D D R _ B _D3 SB_DQ[2]
C10 B3 V7 M _ C L K _DDR3 10
D D R _ A _D2 SA_DQ[1] D D R _ B _D4 SB_DQ[3] SB_CK[1]
C7 E4 V6 M _ C L K _DDR#3 10
D D R _ A _D3 SA_DQ[2] D D R _ B _D5 SB_DQ[4] SB_CK#[1]
A7 Y6 M _ C L K _DDR1 9 A6 M2 D D R _ C K E 3 _DIMMB 10
D D R _ A _D4 SA_DQ[3] SA_CK[1] D D R _ B _D6 SB_DQ[5] SB_CKE[1]
B10 Y5 M _ C L K _DDR#1 9 A4
D D R _ A _D5 SA_DQ[4] SA_CK#[1] D D R _ B _D7 SB_DQ[6]
D10 P6 D D R _ C K E 1 _DIMMA 9 C4
D D R _ A _D6 SA_DQ[5] SA_CKE[1] D D R _ B _D8 SB_DQ[7]
E10 D1
A8 D2
D D R _ A _D8 D8 SA_DQ[7] D D R _ B _D10 F2 SB_DQ[9] AB8
SA_DQ[8] SB_DQ[10] SB_CS#[0] D D R _ C S 2 _DIMMB# 10
D D R _ A _D9 F10 AE2 D D R _ B _D11 F1 AD6
SA_DQ[9] SA_CS#[0] D D R _ C S 0 _DIMMA# 9 SB_DQ[11] SB_CS#[1] D D R _ C S 3 _DIMMB# 10
D D R _ A _D10 E6 AE8 D D R _ B _D12 C2
SA_DQ[10] SA_CS#[1] D D R _ C S 1 _DIMMA# 9 SB_DQ[12]
D D R _ A _D11 F7 D D R _ B _D13 F5
E9 F3
B7 G4 AC7 M _ ODT2 10
D D R _ A _D14 SA_DQ[13] D D R _ B _D16 SB_DQ[15] SB_ODT[0]
E7 AD8 M _ ODT0 9 H6 AD1 M _ ODT3 10
D D R _ A _D15 SA_DQ[14] SA_ODT[0] D D R _ B _D17 SB_DQ[16] SB_ODT[1]
C6 AF9 M _ ODT1 9 G2
D D R _ A _D16 H10 SA_DQ[15] SA_ODT[1] D D R _ B _D18 J6 SB_DQ[17]
G8 J3
D D R _ A _D18 K7 SA_DQ[17] D D R _ B _D20 G1 SB_DQ[19]
SA_DQ[18] SB_DQ[20] D D R _ B _ DM[0..7] 10
D D R _ A _D19 J8 D D R _ B _D21 G5 D4 D D R _ B _DM0
D D R _ A _D20 G7 SA_DQ[19] D D R _ B _D22 J2 SB_DQ[21] SB_DM[0] E1 D D R _ B _DM1
D D R _ A _D21 G10 SA_DQ[20] D D R _ B _D23 J1 SB_DQ[22] SB_DM[1] H3 D D R _ B _DM2
SA_DQ[21] D D R _ A _ DM[0..7] 9 SB_DQ[23] SB_DM[2]
D D R _ A _D22 J7 B9 D D R _ A _DM0 D D R _ B _D24 J5 K1 D D R _ B _DM3
D D R _ A _D23 J10 SA_DQ[22] SA_DM[0] D7 D D R _ A _DM1 D D R _ B _D25 K2 SB_DQ[24] SB_DM[3] AH1 D D R _ B _DM4
D D R _ A _D24 SA_DQ[23] SA_DM[1] D D R _ A _DM2 D D R _ B _D26 SB_DQ[25] SB_DM[4] D D R _ B _DM5
L7 H7 L3 AL2
D D R _ A _D25 M6 SA_DQ[24] SA_DM[2] M7 D D R _ A _DM3 D D R _ B _D27 M1 SB_DQ[26] SB_DM[5] AR4 D D R _ B _DM6
D D R _ A _D26 SA_DQ[25] SA_DM[3] D D R _ A _DM4 D D R _ B _D28 SB_DQ[27] SB_DM[6] D D R _ B _DM7
M8 AG6 K5 AT8
D D R _ A _D27 SA_DQ[26] SA_DM[4] D D R _ A _DM5 D D R _ B _D29 SB_DQ[28] SB_DM[7]
L9 AM7 K4
D D R _ A _D28 SA_DQ[27] SA_DM[5] D D R _ A _DM6 D D R _ B _D30 SB_DQ[29]
L6 AN10 M4
D D R _ A _D29 SA_DQ[28] SA_DM[6] D D R _ A _DM7 D D R _ B _D31 SB_DQ[30]
K8 AN13 N5
D D R _ A _D30 SA_DQ[29] SA_DM[7] D D R _ B _D32 SB_DQ[31]
N8 AF3
P9 AG1 D D R _ B _ DQS#[0..7] 10
D D R _ A _D32 SA_DQ[31] D D R _ B _D34 SB_DQ[33] D D R _ B _ DQS#0
AH5 AJ3 D5
B
D D R _ A _D33 AF5 SA_DQ[32] D D R _ B _D35 AK1 SB_DQ[34] SB_DQS#[0] F4 D D R _ B _ DQS#1
B
SA_DQ[33] D D R _ A _ DQS#[0..7] 9 SB_DQ[35] SB_DQS#[1]
D D R _ A _D34 AK6 C9 D D R _ A _ DQS#0 D D R _ B _D36 AG4 J4 D D R _ B _ DQS#2
DDR SYSTEM MEMORY A
D D R _ A _D35 AK7 SA_DQ[34] SA_DQS#[0] F8 D D R _ A _ DQS#1 D D R _ B _D37 AG3 SB_DQ[36] SB_DQS#[2] L4 D D R _ B _ DQS#3
D D R _ A _D36 SA_DQ[35] SA_DQS#[1] D D R _ A _ DQS#2 D D R _ B _D38 SB_DQ[37] SB_DQS#[3] D D R _ B _ DQS#4
AF6 J9 AJ4 AH2
SA_DQ[36] SA_DQS#[2] SB_DQ[38] SB_DQS#[4]
DDR SYSTEM MEMORY - B

D D R _ A _D37 AG5 N9 D D R _ A _ DQS#3 D D R _ B _D39 AH4 AL4 D D R _ B _ DQS#5
AJ7 AH7 AK3 AR5
AJ6 AK9 AK4 AR8
D D R _ A _D40 SA_DQ[39] SA_DQS#[5] D D R _ A _ DQS#6 D D R _ B _D42 SB_DQ[41] SB_DQS#[7]
AJ10 AP11 AM6
D D R _ A _D41 AJ9 SA_DQ[40] SA_DQS#[6] AT13 D D R _ A _ DQS#7 D D R _ B _D43 AN2 SB_DQ[42]
D D R _ A _D42 SA_DQ[41] SA_DQS#[7] D D R _ B _D44 SB_DQ[43]
AL10 AK5
D D R _ A _D43 AK12 SA_DQ[42] D D R _ B _D45 AK2 SB_DQ[44]
AK8 AM4
D D R _ A _D45 AL7 SA_DQ[44] D D R _ B _D47 AM3 SB_DQ[46]
SA_DQ[45] D D R _ A _ D QS[0..7] 9 SB_DQ[47] D D R _ B _ D QS[0..7] 10
D D R _ A _D46 AK11 C8 D D R _ A _ DQS0 D D R _ B _D48 AP3 C5 D D R _ B _ DQS0
D D R _ A _D47 SA_DQ[46] SA_DQS[0] D D R _ A _ DQS1 D D R _ B _D49 SB_DQ[48] SB_DQS[0] D D R _ B _ DQS1
AL8 F9 AN5 E3
D D R _ A _D48 AN8 SA_DQ[47] SA_DQS[1] H9 D D R _ A _ DQS2 D D R _ B _D50 AT4 SB_DQ[49] SB_DQS[1] H4 D D R _ B _ DQS2
AM10 M9 AN6 M5
AR11 AH8 AN4 AG2
AL11 AK10 AN3 AL5
AM9 AN11 AT5 AP5
D D R _ A _D53 AN9 SA_DQ[52] SA_DQS[6] AR13 D D R _ A _ DQS7 D D R _ B _D55 AT6 SB_DQ[54] SB_DQS[6] AR7 D D R _ B _ DQS7
D D R _ A _D54 SA_DQ[53] SA_DQS[7] D D R _ B _D56 SB_DQ[55] SB_DQS[7]
AT11 AN7
D D R _ A _D55 AP12 SA_DQ[54] D D R _ B _D57 AP6 SB_DQ[56]
D D R _ A _D56 AM12 SA_DQ[55] D D R _ B _D58 AP8 SB_DQ[57]
AN12 D D R _ A _MA[0..15] 9 AT9
D D R _ A _D58 SA_DQ[57] D D R _ A _MA0 D D R _ B _D60 SB_DQ[59]
AM13 Y3 AT7
D D R _ A _D59 SA_DQ[58] SA_MA[0] D D R _ A _MA1 D D R _ B _D61 SB_DQ[60]
AT14 W1 AP9
D D R _ A _D60 SA_DQ[59] SA_MA[1] D D R _ A _MA2 D D R _ B _D62 SB_DQ[61]
AT12 AA8 AR10 D D R _ B _MA[0..15] 10
D D R _ A _D61 SA_DQ[60] SA_MA[2] D D R _ A _MA3 D D R _ B _D63 SB_DQ[62] D D R _ B _MA0
AL13 AA3 AT10 U5
D D R _ A _D62 SA_DQ[61] SA_MA[3] D D R _ A _MA4 SB_DQ[63] SB_MA[0] D D R _ B _MA1
AR14 V1 V2
D D R _ A _D63 SA_DQ[62] SA_MA[4] D D R _ A _MA5 SB_MA[1] D D R _ B _MA2
AP14 AA9 T5
SA_DQ[63] SA_MA[5] D D R _ A _MA6 SB_MA[2] D D R _ B _MA3
V8 V3
SA_MA[6] T1 D D R _ A _MA7 SB_MA[3] R1 D D R _ B _MA4
SA_MA[7] Y9 D D R _ A _MA8 AB1 SB_MA[4] T8 D D R _ B _MA5
SA_MA[8] 10 D D R _ B _BS0 SB_BS[0] SB_MA[5]
C AC3 U6 D D R _ A _MA9 W5 R2 D D R _ B _MA6 C
9 D D R _ A _BS0 SA_BS[0] SA_MA[9] 10 D D R _ B _BS1 SB_BS[1] SB_MA[6]
AB2 AD4 D D R _ A_MA10 R7 R6 D D R _ B _MA7
9 D D R _ A _BS1 SA_BS[1] SA_MA[10] 10 D D R _ B _BS2 SB_BS[2] SB_MA[7]
U7 T2 D D R _ A_MA11 R4 D D R _ B _MA8
9 D D R _ A _BS2 SA_BS[2] SA_MA[11] SB_MA[8]
U3 D D R _ A_MA12 R5 D D R _ B _MA9
SA_MA[12] AG8 D D R _ A_MA13 AC5 SB_MA[9] AB5 D D R _ B_MA10
SA_MA[13] 10 D D R _ B _ C AS# SB_CAS# SB_MA[10]
T3 D D R _ A_MA14 Y7 P3 D D R _ B_MA11
SA_MA[14] 10 D D R _ B _ R AS# SB_RAS# SB_MA[11]
AE1 V9 D D R _ A_MA15 AC6 R3 D D R _ B_MA12
9 D D R _ A _ CAS# SA_CAS# SA_MA[15] 10 D D R _ B _ W E# SB_WE# SB_MA[12]
AB3 AF7 D D R _ B_MA13
9 D D R _ A _ RAS# SA_RAS# SB_MA[13]
AE9 P5 D D R _ B_MA14
9 D D R _ A _ WE# SA_WE# SB_MA[14] N1 D D R _ B_MA15
SB_MA[15]
I C , A U B _ C F D _rPGA,R1P0
D D

ARD/CFD(3/5)-DDR3
C u s t om L A -4 9 0 1 P 1 .0
1 2 3 4 5
1 2 3 4 5
+ C P U _ C ORE
J CPU1F C O NN@
45W J C P U 1G C O NN@
AT21
VAXG1
AT19 AR22
+VCCP +VCCP + C P U _ C ORE VAXG2 VAXG_SENSE
SENSE
LINES
52A 18A AT18 AT22
VAXG3 VSSAXG_SENSE
AT16 15A
VAXG4
AG35 AH14 AR21
VCC1 VTT0_1 VAXG5
10U_0805_6.3V6M
10U_0805_6.3V6M
22U_0805_6.3V6M
47P_0402_50V8J
47P_0402_50V8J
47P_0402_50V8J
47P_0402_50V8J
47P_0402_50V8J
47P_0402_50V8J
47P_0402_50V8J
47P_0402_50V8J
A AG34 AH12 AR19 A
VCC2 VTT0_2 VAXG6
AG33 AH11 AR18
VCC3 VTT0_3 VAXG7
C 37
C 38
C 40
C 41
C 42
C 43
C 44
C 59
C 60
C 61
C 62
AG32 AH10 1 1 1 1 1 1 1 1 1 1 1 AR16 AM22
VCC4 VTT0_4 VAXG8 GFX_VID[0]
AG31 J14 AP21 AP22
GRAPHICS VIDs
AG30 J13 AP19 AN22
VCC6 VTT0_6 @ @ @ @ @ @ @ @ VAXG10 GFX_VID[2]
AG29 H14 AP18 AP23
VCC7 VTT0_7 2 2 2 2 2 2 2 2 2 2 2 VAXG11 GFX_VID[3]
AG28 H12 AP16 AM23
AG27 G14 AN21 AP24
GRAPHICS
AG26 G13 AN19 AN24
AF35 G12 AN18
VCC11 VTT0_11 VAXG15
10U_0805_6.3V6M
10U_0805_6.3V6M
22U_0805_6.3V6M
AF34 G11 AN16
AF33 F14 AM21 AR25
VCC13 VTT0_13 VAXG17 GFX_VR_EN
C 45
C 46
C 48
AF32 F13 1 1 1 AM19 AT25
VCC14 VTT0_14 VAXG18 GFX_DPRSLPVR R71
AF31 F12 AM18 AM24 2 1 1K_0402_5%
VCC15 VTT0_15 VAXG19 GFX_IMON
AF30 F11 AM16
AF29 E14 AL21
VCC17 VTT0_17 2 2 2 VAXG21
AF28 E12 AL19
VCC18 VTT0_18 VAXG22 + 1 . 5 V _ CPU_VDDQ
AF27 D14 AL18
AF26 VCC19 VTT0_19 D13 AL16 VAXG23
1.1V RAIL POWER
AD35 D12 AK21 AJ1 2009/07/02 HP SI-2

VCC21 VTT0_21 VAXG25 VDDQ1
1 U_0603_10V4Z
1 U_0603_10V4Z
1 U_0603_10V4Z
1 U_0603_10V4Z
1 U_0603_10V4Z
AD34 D11 AK19 AF1
- 1.5V RAILS
C50
C51
C52
C53
C54
AD33 C14 AK18 AE7 1 1 1 1 1
AD32 VCC23 VTT0_23 C13 AK16 VAXG27 VDDQ3 AE4
AD31 VCC24 VTT0_24 C12 AJ21 VAXG28 VDDQ4 AC1
AD30 C11 AJ19 AB7
AD29 VCC26 VTT0_26 B14 AJ18 VAXG30 VDDQ6 AB4 2 2 2 2 2
AD28 B12 AJ16 Y1
AD27 VCC28 VTT0_28 A14 AH21 VAXG32 VDDQ8 W7
POWER
AD26 A13 AH19 6A W4
AC35 A12 AH18 U1
3 3 0 U _D2_2VY_R7M
10U_0805_6.3V6M
10U_0805_6.3V6M
AC34 A11 AH16 T7
C63
AC33 T4 1
VCC33 +VCCP VDDQ13
C 64
C 65
AC32 P1 1 1
VCC34 VDDQ14 +
AC31 N7
VCC35 +VCCP VDDQ15
AC30 AF10 N4
B VCC36 VTT0_33 VDDQ16 B
DDR3
10U_0805_6.3V6M
10U_0805_6.3V6M
AC29 AE10 L1
VCC37 VTT0_34 VDDQ17 2 2 2
AC28 AC10 J24 H1
VCC38 VTT0_35 VTT1_45 VDDQ18
CPU CORE SUPPLY
C 56
C 57
10U_0805_6.3V6M
22U_0805_6.3V6M
FDI
AC27 AB10 1 1 J23
VCC39 VTT0_36 VTT1_46
AC26 Y10 H25
VCC40 VTT0_37 VTT1_47 +VCCP
C68
C69
AA35 W10 1 1
VCC41 VTT0_38
AA34 U10
VCC42 VTT0_39 2 2
AA33 T10 P10
22U_0805_6.3V6M
22U_0805_6.3V6M
AA32 J12 N10
AA31 VCC44 VTT0_41 J11 2 2 VTT0_60 L10
C70
C71
AA30 J16 K10 1 1
AA29 VCC46 VTT0_43 J15 VTT0_62
VCC47 VTT0_44
AA28
AA27 VCC48
VCC49 +VCCP 2 2
AA26
VCC50
1.1V
Y35 J22
Y34 VCC51 K26 VTT1_63 J20 + V C CP
22U_0805_6.3V6M
22U_0805_6.3V6M
Y33 J27 J18
PEG & DMI

Y32 J26 H21
10U_0805_6.3V6M
C74
C75
Y31 1 1 J25 H20
Y30 H27 H19
C 77
Y29 G28 1
VCC57 VTT1_53
Y28 G27
Y27 VCC58 2 2 G26 VTT1_54
Y26 VCC59 F26 VTT1_55
VCC60 VTT1_56 2
V35 AN33 P S I# 46 E26 L26
VCC61 PSI# VTT1_57 VCCPLL1
1.8V
V34 2009/07/22 HP SI-2 E25 L27
POWER
VCC62 VTT1_58 VCCPLL2 + 1.8VS

V33
VCC63 H _ V ID0
H _ V I D[0..6] 46 1.1A VCCPLL3
M26
V32 AK35
VCC64 VID[0] H _ V ID1
V31 AK33
VCC65 VID[1]
1 U_0603_10V4Z
1 U_0603_10V4Z
2 . 2U_0603_6.3V4Z
10U_0805_6.3V6M
4 .7U_0603_6.3V6K
V30 AK34 H _ V ID2
VCC66 VID[2]
C 78
C 79
C 80
C 81
C 82
V29 AL35 H _ V ID3 1 1 1 1 1
VCC67 VID[3]
CPU VIDS
V28 AL33 H _ V ID4

V27 VCC68 VID[4] AM33 H _ V ID5
VCC69 VID[5]
CPU
V26 AM35 H _ V ID6

VCC70 VID[6] P M _ D P R S LPVR_R 1 I C , A U B _ C F D_rPGA,R1P0 2 2 2 2 2
C U35 AM34 2 P R O C _ D P R S LPVR 46
C
U34 VCC71 PROC_DPRSLPVR R 74 0_0402_5%
VCC72
U33
U32 VCC73
U31 VCC74 G15
VCC75 VTT_SELECT H _ V TTVID1 43
U30
VCC76
U29
VCC77
U28
VCC78
H_VTTVID1 = Low, 1.1V
U27
VCC79
U26
VCC80
H_VTTVID1 = High, 1.05V
R35
R34 VCC81
VCC82
R33
R32 VCC83 AN35
R31
R30
VCC84
VCC85
ISENSE I M V P _IMON 46
+1.5V to +1.5V_CPU_VDDQ Transfer
VCC86
R29
VCC87
1 R75 2 0_0402_5%
SENSE LINES
R28 AJ34 VCCSENSE

VCC88 VCC_SENSE V C C S E N S E 46 + 1.5V + 1 . 5 V _ CPU_VDDQ
R27 AJ35 1 2 V S S S E NSE + 1 . 5 V _ CPU_VDDQ
VCC89 VSS_SENSE V S S S E N SE 46
R26 R76 0_0402_5% 2009/07/21 HP SI-2 2009/07/02 HP SI-1b
VCC90 SIS406DN-T1-GE3_PAK1212-8-5
P35
P34 VCC91 B15 Q 91
VCC92 VTT_SENSE V T T _SENSE 43
P33 A15 V S S _ SENSE_VTT 43 1
1
VCC93 VSS_SENSE_VTT C 991
P32 2 1 2 0.1U_0402_10V6K
P31 VCC94 3 + 1.5V + 1 . 5 V _ CPU_VDDQ R 1223
VCC95 C 992
P30 5 1 2 0.1U_0402_10V6K 510_0402_5%
P29 VCC96
VCC97 C 994
0.1U_0402_10V6K
C 995
0.1U_0402_10V6K
P28 C 993 1 2 0.1U_0402_10V6K
2
P27 VCC98 R 1224
VCC99 1 1
P26 1 2 C 996 1 2 0.1U_0402_10V6K
VCC100
1
0_0402_5% D
38 S LP_S3 S LP_S3 2 Q92

Close to CPU + C P U _ C ORE 2 2 G S S M3K7002F_SC59-3
S
3
VCCSENSE 1 2
D D
R77 100_0402_1% R U NON R U NON 38
Stich CAP between 1.5V and 1.5V-CPU_VDDQ
V S S S E NSE 1 2
R78 100_0402_1%

ARD/CFD(4/5)-PWR
C u s t om L A -4 9 0 1 P 1 .0
1 2 3 4 5
1 2 3 4 5
+ C P U _ C ORE
CPU CORE
J CPU1H C ONN@ JCPU1I C ONN@ Inside cavity
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
AT20 AE34
VSS1 VSS81
C 83
C 84
C 85
C 86
C 87
C 89
C 90
C 91
C 92
C 94
C 114
C 117
C 118
C 119
AT17 AE33 1 1 1 1 1 1 1 1 1 1 1 1 1 1
VSS2 VSS82
AR31 AE32 K27
VSS3 VSS83 VSS161
AR28 AE31 K9
VSS4 VSS84 VSS162
AR26 AE30 K6
VSS5 VSS85 VSS163 2 2 2 2 2 2 2 2 2 2 2 2 2 2
AR24 AE29 K3
VSS6 VSS86 VSS164
AR23 AE28 J32
VSS7 VSS87 VSS165
AR20 AE27 J30
VSS8 VSS88 VSS166
AR17 AE26 J21
VSS9 VSS89 VSS167
A AR15 AE6 J19 A
AR12
VSS10
VSS11
VSS90
VSS91
AD10 H35
VSS168
VSS169
between Inductor and socket
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
AR9 AC8 H32
VSS12 VSS92 VSS170
AR6 AC4 H28
VSS13 VSS93 VSS171
C 9 74
C 9 71
C 9 70
C 1 00
C 1 02
C 1 01
C 1 20
C 1 03
C88
C93
C95
C98
C99
AR3 AC2 H26 1 1 1 1 1 1 1 1 1 1 1 1 1
VSS14 VSS94 VSS172
AP20 AB35 H24
VSS15 VSS95 VSS173
AP17 AB34 H22
VSS16 VSS96 VSS174
AP13 AB33 H18
VSS17 VSS97 VSS175 2 2 2 2 2 2 2 2 2 2 2 2 2
AP10 AB32 H15
VSS18 VSS98 VSS176
AP7 AB31 H13
AP4 VSS19 VSS99 AB30 H11 VSS177
VSS20 VSS100 VSS178
AP2 AB29 H8
AN34 VSS21 VSS101 AB28 H5 VSS179
VSS22 VSS102 VSS180
AN31 AB27 H2
VSS23 VSS103 VSS181
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
3 3 0 U_D2_2.5VM_R6M
3 3 0 U_D2_2.5VM_R6M
3 3 0 U_D2_2.5VM_R6M
3 3 0 U_D2_2.5VM_R6M
4 7 0 U_D2_2VM_R4.5M
AN23 AB26 G34
VSS24 VSS104 VSS182
C 105
C 109
C 107
C 108
C 106
AN20 AB6 G31 1 1 1 1 1
VSS25 VSS105 VSS183
C 111
C 975
C 976
C 969
C 104
C 973
C 112
C 113
C 115
C 116
C 977
C96
C97
AN17 AA10 G20 1 1 1 1 1 1 1 1 1 1 1 1 1
VSS26 VSS106 VSS184 @ @ @ @ @ @ @ @ + + + + @ +
AM29 Y8 G9
AM27 VSS27 VSS107 Y4 G6 VSS185
VSS28 VSS108 VSS186
AM25 Y2 G3
AM20 VSS29 VSS109 W35 F30 VSS187 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
VSS30 VSS110 VSS188
AM17 W34 F27
AM14 VSS31 VSS111 W33 F25 VSS189
AM11 VSS32 VSS112 W32 F22 VSS190
AM8
VSS33
VSS34
VSS113
VSS114
W31 F19
VSS191
VSS192
Under cavity
AM5 W30 F16
VSS35 VSS115 VSS193
AM2 W29 E35
AL34 VSS36 VSS116 W28 E32 VSS194
AL31
AL23
VSS37
VSS38
VSS39
VSS VSS117
VSS118
VSS119
W27
W26
E29
E24
VSS195
VSS196
VSS197
VSS
AL20 W6 E21
VSS40 VSS120 VSS198
AL17 V10 E18
VSS41 VSS121 VSS199
AL12 U8 E13
VSS42 VSS122 VSS200
AL9 U4 E11
VSS43 VSS123 VSS201 + 3VS
AL6 U2 E8
B
AL3 VSS44 VSS124 T35 E5 VSS202 B
VSS45 VSS125 VSS203 V S S _ N C TF1_R
AK29 T34 E2 AT35
AK27 VSS46 VSS126 T33 D33 VSS204 VSS_NCTF1 AT1 V S S _ N C TF2_R
1
VSS47 VSS127 VSS205 VSS_NCTF2 V S S _ N C TF3_R
AK25 T32 D30 AR34 T23
VSS48 VSS128 VSS206 VSS_NCTF3 V S S _ N C TF4_R R 79
AK20 T31 D26 B34 T24
AK17 T30 D9 B2 T25
NCTF
VSS50 VSS130 VSS208 VSS_NCTF5 C R A C K _ BGA 17,35
AJ31 T29 D6 B1 V S S _ N C TF6_R 100K_0402_5%
6
AJ23 T28 D3 A35
2
AJ20 VSS52 VSS132 T27 C34 VSS210 VSS_NCTF7
VSS53 VSS133 VSS211 Q 2A
AJ17 T26 C32
AJ14 VSS54 VSS134 T6 C29 VSS212 V S S _ N C TF2_R 2 N 7 002DWH_SOT363-6
2
VSS55 VSS135 VSS213
AJ11 R10 C28
AJ8 VSS56 VSS136 P8 C24 VSS214
1
AJ5 P4 C22
VSS58 VSS138 VSS216
AJ2 P2 C20
AH35 VSS59 VSS139 N35 C19 VSS217
VSS60 VSS140 VSS218
AH34 N34 C16
1
VSS61 VSS141 VSS219
AH33 N33 B31
VSS62 VSS142 VSS220 R 80
AH32 N32 B25
VSS63 VSS143 VSS221 C R A C K _ BGA
AH31 N31 B21
AH30 VSS64 VSS144 N30 B18 VSS222 100K_0402_5%
VSS65 VSS145 VSS223
3
AH29 N29 B17
2
AH28 VSS66 VSS146 N28 B13 VSS224
AH27 VSS67 VSS147 N27 B11 VSS225 Q 2B
VSS68 VSS148 VSS226 V S S _ N C TF1_R 2 N 7 002DWH_SOT363-6
AH26 N26 B8 5
VSS69 VSS149 VSS227
AH20 N6 B6
VSS70 VSS150 VSS228
AH17 M10 B4
4
VSS71 VSS151 VSS229
AH13 L35 A29
AH9 L32 A27
VSS73 VSS153 VSS231
AH6 L29 A23
VSS74 VSS154 VSS232
AH3 L8 A9
VSS75 VSS155 VSS233
AG10 L5
1
AF8 VSS76 VSS156 L2 C R A C K _ BGA
AF4 VSS77 VSS157 K34 R 81
VSS78 VSS158
C AF2 K33 C
6
AE35 VSS79 VSS159 K30 100K_0402_5%
VSS80 VSS160
2
Q 5A
V S S _ N C TF6_R 2 2 N 7 002DWH_SOT363-6
I C , A U B _ C F D _rPGA,R1P0 I C , A U B _ C F D _rPGA,R1P0
1
+ 3VS
1
R 82 C R A C K _ BGA
3
100K_0402_5%
2
Q 5B
V S S _ N C TF7_R 5 2 N 7 002DWH_SOT363-6
4
BGA Ball Cracking Prevention and Detection
D D

ARD/CFD(5/5)-GND/Bypass
C u s t om L A -4 9 0 1 P 1 .0
1 2 3 4 5
1 2 3 4 5
+ V R E F _ D Q_DIMMA +1.5V + 1.5V

3 A @ 1 .5V + 1.5V
6 D D R _ A _D[0..63]
DDR3 SO-DIMM A 6 D D R _ A _ DM[0..7]
1
J D I M A1 C O NN@ R83
6 D D R _ A _ DQS[0..7]
+ V R E F _ D Q_DIMMA 1 2 1K_0402_1%
VREF_DQ VSS1 D D R _ A _D4 + V _ D D R _ C P U _REFA
3 4 6 D D R _ A _ DQS#[0..7]
VSS2 DQ4
0 .1U_0402_16V4Z
2.2U_0603_6.3V6K
D D R _ A _D0 5 6 D D R _ A _D5
2
DQ0 DQ5
C 1 21
C 1 22
1 1 D D R _ A _D1 7 8
DQ1 VSS3 6 D D R _ A _MA[0..15]
9 10 D D R _ A _ DQS#0
D D R _ A _DM0 VSS4 DQS#0 D D R _ A _ DQS0
11 12
1
DM0 DQS0
13 14
2 2 D D R _ A _D2 VSS5 VSS6 D D R _ A _D6 R84
15 16
D D R _ A _D3 DQ2 DQ6 D D R _ A _D7 1K_0402_1%
17 18
DQ3 DQ7
A 19 20 A
D D R _ A _D8 VSS7 VSS8 D D R _ A _D12
21 22
2
D D R _ A _D9 DQ8 DQ12 D D R _ A _D13
23 24
DQ9 DQ13
25 26
D D R _ A _ DQS#1 VSS9 VSS10 D D R _ A _DM1 + V R E F _ D Q_DIMMA + V _ D D R _ C P U _REFA
27 28
D D R _ A _ DQS1 DQS#1 DM1 D R A M R ST#
29 30 D R A M R ST# 4,10
DQS1 RESET#
31 32
D D R _ A _D10 VSS11 VSS12 D D R _ A _D14 R 991 1
33 34 2 0_0402_5%
D D R _ A _D11 DQ10 DQ14 D D R _ A _D15
35 36
DQ11 DQ15
37 38
D D R _ A _D16 39 VSS13 VSS14 40 D D R _ A _D20
D D R _ A _D17 DQ16 DQ20 D D R _ A _D21
41 42
43 DQ17 DQ21 44 + V _ D D R _ C P U_REF0
D D R _ A _ DQS#2 VSS15 VSS16 D D R _ A _DM2 2009/04/10 HP DB-3
45 46
D D R _ A _ DQS2 DQS#2 DM2
47 48
DQS2 VSS17 D D R _ A _D22 R86
49 50 1 2 0_0402_5%
D D R _ A _D18 VSS18 DQ22 D D R _ A _D23
51 52
D D R _ A _D19 DQ18 DQ23
53 54
55 DQ19 VSS19 56 D D R _ A _D28
57 58
D D R _ A _D25 59 DQ24 DQ29 60
DQ25 VSS21 D D R _ A _ DQS#3
61 62
D D R _ A _DM3 63 VSS22 DQS#3 64 D D R _ A _ DQS3
65 DM3 DQS3 66
67 68
D D R _ A _D27 69 DQ26 DQ30 70 D D R _ A _D31
DQ27 DQ31
71 72
VSS25 VSS26
6 D D R _ C K E 0 _DIMMA D D R _ C K E 0 _DIMMA
73 74 D D R _ C K E 1 _DIMMA
CKE0 CKE1 D D R _ C K E 1 _DIMMA 6
75 76
VDD1 VDD2 D D R _ A_MA15
77 78
D D R _ A _BS2 NC1 A15 D D R _ A_MA14
6 D D R _ A _BS2 79 80
BA2 A14
81 82
B
D D R _ A_MA12 83 VDD3 VDD4 84 D DR_A_MA11
B
D D R _ A _MA9 A12/BC# A11 D D R _ A _MA7

85 86
87 A9 A7 88
D D R_A_MA8 VDD5 VDD6 D D R_A_MA6
89 90
D D R _ A _MA5 A8 A6 D D R _ A _MA4
91 92
A5 A4
93 94
D D R _ A _MA3 VDD7 VDD8 D D R _ A _MA2
95 96
D D R _ A _MA1 A3 A2 D D R _ A _MA0
97 98
99 A1 A0 100 2009/04/10 HP DB-3
M _ C L K _DDR0 VDD9 VDD10 M _ C L K _DDR1
6 M _ C L K _DDR0 101 102 M _ C L K _DDR1 6
M _ C L K _DDR#0 103 CK0 CK1 104 M _ C L K _DDR#1
6 M _ C L K _DDR#0 CK0# CK1# M _ C L K _DDR#1 6 +1.5V
105 106
D D R _ A_MA10 107 VDD11 VDD12 108 D D R _ A _BS1
A10/AP BA1 D D R _ A _BS1 6
6 D D R _ A _BS0 D D R _ A _BS0 109 110 D D R _ A _ RAS#
BA0 RAS# D D R _ A _ RAS# 6
111 112
1
D D R _ A _ WE# 113 VDD13 VDD14 114 D D R _ C S 0 _DIMMA#
6 D D R _ A _ WE# WE# S0# D D R _ C S 0 _DIMMA# 6
6 D D R _ A _ CAS# D D R _ A _ CAS# 115 116 M _ ODT0 R 1182
CAS# ODT0 M _ ODT0 6
117 118 1K_0402_1%
D D R _ A_MA13 VDD15 VDD16 M _ ODT1 + V R E F _CA
119 120 M _ ODT1 6
D D R _ C S 1 _DIMMA# A13 ODT1
6 D D R _ C S 1 _DIMMA# 121 122
2
123 S1# NC2 124
VDD17 VDD18 + V R E F _ CA
125 126
127 NCTEST VREF_CA 128
VSS27 VSS28
0 .1U_0402_16V4Z
2.2U_0603_6.3V6K
D D R _ A _D32 129 130 D D R _ A _D36
DQ32 DQ36
1
D D R _ A _D33 131 132 D D R _ A _D37
DQ33 DQ37
C 141
C 142
133 134 1 1 R 1183
D D R _ A _ DQS#4 VSS29 VSS30 D D R _ A _DM4 1K_0402_1% 2009/04/10 HP DB-3
135 136
137 138
DQS4 VSS31 D D R _ A _D38
139 140
2
D D R _ A _D34 VSS32 DQ38 D D R _ A _D39 2 2
141 142
D D R _ A _D35 DQ34 DQ39
143 144
DQ35 VSS33 D D R _ A _D44
145 146
D D R _ A _D40 147 VSS34 DQ44 148 D D R _ A _D45
D D R _ A _D41 149 DQ40 DQ45 150
C 151 152 C
D D R _ A _DM5 153 VSS36 DQS#5 154 D D R _ A _ DQS5
DM5 DQS5
155 156
D D R _ A _D42 157 VSS37 VSS38 158 D D R _ A _D46
D D R _ A _D43 159 DQ42 DQ46 160 D D R _ A _D47
DQ43 DQ47
161 162
163 164
D D R _ A _D49 DQ48 DQ52 D D R _ A _D53
165 166
167 DQ49 DQ53 168
D D R _ A _ DQS#6 169 VSS41 VSS42 170 D D R _ A _DM6
171 172
173 DQS6 VSS43 174 D D R _ A _D54
175 176
D D R _ A _D51 177 DQ50 DQ55 178
DQ51 VSS45 D D R _ A _D60
179 180
181 182
D D R _ A _D57 DQ56 DQ61
183 184
D D R _ A _DM7
185
VSS48 DQS#7
186
D D R _ A _ DQS7
Layout Note: Layout Note:
187 188
DM7 DQS7 Pla c e near JDIMMA Place near JDIMMA.203 & JDIMMA.204
189 190
191 192
D D R _ A _D59 193 DQ58 DQ62 194 D D R _ A _D63
DQ59 DQ63
195 196
R 87 1 VSS51 VSS52
2009/02/16 HP DB-2 2 10K_0402_5% 197 198 P M_EXTTS#1_R
P M_EXTTS#1_R 4 ,10
199 SA0 EVENT# 200 S M B _DATA_S3 + 0.75VS
+ 3VS VDDSPD SDA S M B _ DATA_S3 4,10,11,13,32
2.2U_0402_6.3V6M
0 .1U_0402_16V4Z
201 202 S M B _CLK_S3 +1.5V

SA1 SCL S M B _CLK_S3 4,10,11,13,32
C 143
C 144
1 1 203 204 + 0.75VS

VTT1 VTT2
1 10K_0402_5%
R88
205 206 0 . 6 5 A @0.75V

G1 G2
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
0 .1U_0402_16V4Z
0 .1U_0402_16V4Z
0 .1U_0402_16V4Z
0 .1U_0402_16V4Z
3 3 0 U _ D2_2VY_R7M
C 123
C 136
1U_0402_6.3V6K
C 137
1U_0402_6.3V6K
C 138
C 139
1U_0402_6.3V6K
C 140
10U_0603_6.3V6M
C 124
10U_0603_6.3V6M
C 125
10U_0603_6.3V6M
1U_0402_6.3V6K
2 2 1
C 1 26
C 1 27
C 1 28
C 1 29
C 1 30
C 1 31
C 1 32
C 1 33
C 1 34
C 1 35
F O X _ AS0A626-U2RN-7F +0.75V 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
+
2
@ @ @ @ @
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
D D
J P 20 2009/04/24 HP SI-1
TOP SLOT S M B _DATA_S3

S M B _CLK_S3
3
2
1
3
2
1
G2
G1
5
4
ACES_85204-03001
Reserved C ONN@
2008/09/15 2009/12/31 Title
For ME/iAMT debug Issued Date Deciphered Date
DDRIII-SODIMM SLOT1
C u s t om L A -4 9 0 1 P 1 .0
1 2 3 4 5
1 2 3 4 5
DDR3 SO-DIMM B
+ V R E F _ D Q_DIMMB +1.5V REVERSE + 1.5V
6 D D R _ B _ DQS#[0..7]
+ V R E F _ D Q_DIMMB + V _ D D R _ C P U _REFB + 1.5V
6 D D R _ B _D[0..63]
1
3 A @ 1 .5V R 89 1 2 0_0402_5%
C O NN@ R 1184
6 D D R _ B _ DM[0..7]
J D I M B1 1K_0402_1%
+ V R E F _ D Q_DIMMB 1 2 + V _ D D R _ C P U_REF1 + V _ D D R _ C P U _REFB
VREF_DQ VSS1 6 D D R _ B _ DQS[0..7] 2009/04/10 HP DB-3
3 4 D D R _ B _D4
2
VSS2 DQ4
2.2U_0603_6.3V6K
0 .1U_0402_16V4Z
D D R _ B _D0 5 6 D D R _ B _D5
DQ0 DQ5 6 D D R _ B _MA[0..15]
1 1 D D R _ B _D1 7 8 R 90 1 2 0_0402_5%
DQ1 VSS3 D D R _ B _ DQS#0 2009/04/10 HP DB-3
9 10
1
VSS4 DQS#0
C 145
C 146
D D R _ B _DM0 11 12 D D R _ B _ DQS0
DM0 DQS0 R 1185
13 14
2 2 D D R _ B _D2 VSS5 VSS6 D D R _ B _D6 1K_0402_1%
A 15 16 A
D D R _ B _D3 DQ2 DQ6 D D R _ B _D7
17 18
DQ3 DQ7
19 20
2
D D R _ B _D8 VSS7 VSS8 D D R _ B _D12
21 22
D D R _ B _D9 DQ8 DQ12 D D R _ B _D13
23 24
DQ9 DQ13
25 26
D D R _ B _ DQS#1 VSS9 VSS10 D D R _ B _DM1
27 28
D D R _ B _ DQS1 DQS#1 DM1 D R A M R ST#
29 30 D R A M R ST# 4,9
DQS1 RESET#
31 32
33 34
D D R _ B _D11 35 DQ10 DQ14 36 D D R _ B _D15
DQ11 DQ15
37 38
D D R _ B _D16 39 VSS13 VSS14 40 D D R _ B _D20
D D R _ B _D17 DQ16 DQ20 D D R _ B _D21
41 42
DQ17 DQ21
43 44
D D R _ B _ DQS#2 VSS15 VSS16 D D R _ B _DM2
45 46
D D R _ B _ DQS2 DQS#2 DM2
47 48
DQS2 VSS17 D D R _ B _D22
49 50
D D R _ B _D18 51 VSS18 DQ22 52 D D R _ B _D23
D D R _ B _D19 DQ18 DQ23
53 54
55 DQ19 VSS19 56 D D R _ B _D28
D D R _ B _D24 VSS20 DQ28 D D R _ B _D29
57 58
D D R _ B _D25 59 DQ24 DQ29 60
61 DQ25 VSS21 62 D D R _ B _ DQS#3
D D R _ B _DM3 VSS22 DQS#3 D D R _ B _ DQS3
63 64
65 DM3 DQS3 66
67 68
D D R _ B _D27 69 DQ26 DQ30 70 D D R _ B _D31
DQ27 DQ31
71 72
VSS25 VSS26
6 D D R _ C K E 2 _DIMMB D D R _ C K E 2 _DIMMB 73 74 D D R _ C K E 3 _DIMMB

CKE0 CKE1 D D R _ C K E 3 _DIMMB 6
75 76
VDD1 VDD2 D D R _ B_MA15
77 78
B
D D R _ B _BS2 79 NC1 A15 80 D D R _ B_MA14
B
6 D D R _ B _BS2 BA2 A14
81 82 2009/04/10 HP DB-3
D D R _ B_MA12 83 VDD3 VDD4 84 DDR_B_MA11
D D R _ B _MA9 A12/BC# A11 D D R _ B _MA7
85 86
A9 A7
87 88
D DR_B_MA8 VDD5 VDD6 D DR_B_MA6
89 90
D D R _ B _MA5 A8 A6 D D R _ B _MA4
91 92
A5 A4
93 94
D D R _ B _MA3 95 VDD7 VDD8 96 D D R _ B _MA2
D D R _ B _MA1 A3 A2 D D R _ B _MA0
97 98
99 A1 A0 100 2008/11/07 HP
M _ C L K _DDR2 VDD9 VDD10 M _ C L K _DDR3
6 M _ C L K _DDR2 101 102 M _ C L K _DDR3 6
M _ C L K _DDR#2 103 CK0 CK1 104 M _ C L K _DDR#3
6 M _ C L K _DDR#2 CK0# CK1# M _ C L K _DDR#3 6 +1.5V
105 106
D D R _ B_MA10 VDD11 VDD12 D D R _ B _BS1
107 108 D D R _ B _BS1 6
D D R _ B _BS0 109 A10/AP BA1 110 D D R _ B _ RAS#
6 D D R _ B _BS0 BA0 RAS# D D R _ B _ RAS# 6
111 112
1
D D R _ B _ WE# VDD13 VDD14 D D R _ C S 2 _DIMMB#
6 D D R _ B _ WE# 113 114 D D R _ C S 2 _DIMMB# 6
D D R _ B _ CAS# WE# S0# M _ ODT2 R 1187
6 D D R _ B _ CAS# 115 116 M _ ODT2 6
CAS# ODT0 1K_0402_1%
117 118
D D R _ B_MA13 119 VDD15 VDD16 120 M _ ODT3 + V R E F _CB
A13 ODT1 M _ ODT3 6
6 D D R _ C S 3 _DIMMB# D D R _ C S 3 _DIMMB# 121 122
2
123 S1# NC2 124
125 VDD17 VDD18 126 + V R E F _ CB
NCTEST VREF_CA
127 128
VSS27 VSS28
0 .1U_0402_16V4Z
2.2U_0603_6.3V6K
D D R _ B _D32 129 130 D D R _ B _D36
DQ32 DQ36
1
D D R _ B _D33 131 132 D D R _ B _D37
DQ33 DQ37
C 159
C 160
133 134 1 1 R 1188
D D R _ B _ DQS#4 VSS29 VSS30 D D R _ B _DM4 1K_0402_1% 2009/04/24 SI-1
135 136
137 138
DQS4 VSS31 D D R _ B _D38
139 140
2
D D R _ B _D34 VSS32 DQ38 D D R _ B _D39 2 2
141 142
D D R _ B _D35 143 DQ34 DQ39 144
145 DQ35 VSS33 146 D D R _ B _D44
C 147 148 C
D D R _ B _D41 149 DQ40 DQ45 150
DQ41 VSS35 D D R _ B _ DQS#5
151 152
D D R _ B _DM5 153 VSS36 DQS#5 154 D D R _ B _ DQS5
155 DM5 DQS5 156
157 158
D D R _ B _D43 DQ42 DQ46 D D R _ B _D47
159 160
DQ43 DQ47
161 162
D D R _ B _D48 163 VSS39 VSS40 164 D D R _ B _D52
D D R _ B _D49 165 DQ48 DQ52 166 D D R _ B _D53
DQ49 DQ53
167 168
D D R _ B _ DQS#6 169 VSS41 VSS42 170 D D R _ B _DM6
171 172
173 DQS6 VSS43 174 D D R _ B _D54
175 176
D D R _ B _D51 DQ50 DQ55
177
DQ51 VSS45
178
D D R _ B _D60
Layout Note:
179 180
D D R _ B _D56 VSS46 DQ60 D D R _ B _D61 Pla c e near JDIMMB
D D R _ B _D57
181
DQ56 DQ61
182 Layout Note:
183 184
DQ57 VSS47 D D R _ B _ DQS#7 Place near JDIMMB.203 & JDIMMB.204
185 186
D D R _ B _DM7 VSS48 DQS#7 D D R _ B _ DQS7
187 188
189 DM7 DQS7 190
191 192
D D R _ B _D59 DQ58 DQ62 D D R _ B _D63
193 194
1 R91 2 195 DQ59 DQ63 196 + 1.5V +0.75VS
2009/02/16 HP DB-2 10K_0402_5% VSS51 VSS52 P M_EXTTS#1_R
197 198 P M_EXTTS#1_R 4 ,9
199 SA0 EVENT# 200 S M B _DATA_S3 2009/04/24 HP SI-1
+ 3VS VDDSPD SDA S M B _ DATA_S3 4,9,11,13,32
2.2U_0402_6.3V6M
0 .1U_0402_16V4Z
201 202 S M B _CLK_S3

SA1 SCL S M B _CLK_S3 4,9,11,13,32
C 165
C 166
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
0 .1U_0402_16V4Z
0 .1U_0402_16V4Z
0 .1U_0402_16V4Z
0 .1U_0402_16V4Z
3 3 0 U _D2_2VY_R7M
1 1 1 2 203 204 + 0.75VS 1
VTT1 VTT2
C 149
C 150
C 151
C 152
C 153
C 154
C 155
C 156
C 157
C 158
C 961
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
R92 10K_0402_5% 1 1 1 1 1 1 1 1 1 1
C 1 61
C 1 62
C 1 63
C 1 64
205 206 0 . 6 5 A @0.75V +
G1 G2 1 1 1 1
2 2 +0.75V @ @ @ @ @
2 2 2 2 2 2 2 2 2 2 2
2 2 2 2
D D
2009/04/24 HP SI-1
BOT SLOT
DDRIII-SODIMM SLOT2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS L A -4 9 0 1 P 1 .0
1 2 3 4 5
1 2 3 4 5
A A
+ 3VS_+1.5VS
2009/06/30 HP SI-2
+ 3 VS_CK505 + 1.05VS_CK505 + 3 VS_CK505 + 1 .05VS_CK505

250mA 80mA U2
1 32 S M B _CLK_S3
VDD_DOT SCL S M B _CLK_S3 4,9,10,13,32
2 31 S M B _DATA_S3
VSS_DOT SDA S M B _DATA_S3 4,9,10,13,32
C L K _ B UF_DOT96 R93 1 2 0_0402_5% L _ C L K _BUF_DOT96 3 30 R E F _ 0 / C PU_SEL 33_0402_1% 1 2 R 94 C L K _ 14M_PCH
13 C L K _ B U F_DOT96 DOT_96 REF_0/CPU_SEL C L K _ 14M_PCH 13
C L K _ B UF_DOT96# R95 1 2 0_0402_5% L _ C L K_BUF_DOT96# 4 96MHz 29 1
13 C L K _ B UF_DOT96# DOT_96# VDD_REF
5 28 C L K_XTAL_IN
R96 VDD_27 XTAL_IN
20 2 7 M_CLK
2 7 M_CLK 1 2 0_0402_5% L _27M_CLK 6 27 C LK_XTAL_OUT C 8 31 @
2 7 M_SSC R97 1 2 22_0402_1%L _ 27M_SSC 7 27MHZ XTAL_OUT 26
20 2 7 M _SSC 10P_0402_50V8C
8 27MHZ_SS VSS_REF 25 CK_PWRGD 2
2009/02/27 Nvidia DB-2 NV care VSS_27 CKPWRGD/PD#
9 24
C L K _ B U F _ C K SSCD R 9 9 1 VSS_SATA VDD_CPU
13 C L K _ B U F _ C K SSCD 2 0_0402_5% L _ C L K _ B U F _CKSSCD 10 23 R _ C L K _ B UF_BCLK R 102 1 2 0_0402_5% C L K _ B U F _BCLK
C L K _ B U F_BCLK 13
C L K _ B U F _ C KSSCD# R 100 1 2 0_0402_5% L _ C L K _ B U F _CKSSCD# SRC_1/SATA CPU_0 R _ C L K _ B UF_BCLK# R 104 1 2 0_0402_5% C L K _ B U F_BCLK#
SRC_1#/SATA#100MHz 133MHz CPU_0#
13 C L K _ B U F _ C K SSCD# 11 22 C L K _ B U F_BCLK# 13
12 21
R 101 1 VSS_SRC VSS_CPU
13 C L K _ DMI
C L K _ DMI 2 0_0402_5% L _ C LK_DMI 13 20
C L K _DMI# R 103 1 2 0_0402_5% L _ C LK_DMI# SRC_2 CPU_1
13 C L K _ DMI# 14
SRC_2# 100MHz CPU_1#
19
15 18
C P U _ STOP# VDD_SRC_IO VDD_CPU_IO
16 17
CPU_STOP# VDD_SRC
TGND
B B
RTM890N-632_QFN32_5X5
33
2009/06/30 HP SI-2
+ 3VS_+1.5VS 2009/09/14 HP SI-2b + 3VS + 1 .5VS
+ 1.05VS + 1 .05VS_CK505 + 3VS_CK505 + 3 VS + 3 VS_CK505 R 1214 1 @ 2 0_0603_5%

Close to U2 Close to U2
C 1 2 C P U _ STOP# R 127 1 2 10K_0402_5% 1 2 R 1215 1 2 0_0603_5% C
R 1 28 0_0603_5% R 1 09 0_0603_5% CK_PWRGD R98 1 2 10K_0402_5% + 3 VS_CK505
10U_0603_6.3V6M
1 0U_0805_10V4Z
0 .1U_0402_16V4Z
0 .1U_0402_16V4Z
0 .1U_0402_16V4Z
47P_0402_50V8J
10U_0603_6.3V6M
0 .1U_0402_16V4Z
0 .1U_0402_16V4Z
0 .1U_0402_16V4Z
0 .1U_0402_16V4Z
0 .1U_0402_16V4Z
47P_0402_50V8J
C 178
C 179
C 180
C 181
C 182
C 183
C 171
C 172
C 173
C 174
C 175
C 176
C 177
1 1 1 1 1 1 1 1 1 1 1 1 1
1 @ 2 R E F _ 0 / C PU_SEL
1
C 1 84 10P_0402_50V8C D
2 C L K _ EN# 46
2 2 2 2 2 2 2 2 2 2 2 2 2
EMI Capacitor G
S
3
Q8
S S M 3K7002FU_SC70-3
14.31818MHZ_20P_1BX14318BE1A
Close to U2
C LK_XTAL_OUT
C L K_XTAL_IN
Y1
2 1
2009/02/06 HP DB-2
+ 1.05VS
2 2
D PIN 30 CPU_0 CPU_1 D
R 1 42 1 @ 2 10K_0402_5% R E F _ 0 / C PU_SEL C 167 C 1 68
33P_0402_50V8J 33P_0402_50V8J
0 (Default) 133MHz 133MHz 1 1
R 1 44 1 2 10K_0402_5%
1 100MHz 100MHz

CLOCK GENERATOR
1 2 3 4 5
1 2 3 4 5
P C H _ RTCX1
+ R T C V CC + 3VS
RTC Conn.
1 2 P C H _ RTCX2 2009/02/06 HP DB-2
R 1 59 10M_0402_5% 1 2 S M _ I N T R UDER# 1 2 SIRQ
R 160 1M_0402_5% R 1 61 10K_0402_5% + R T C V CC + VREG3_51125 B ATT1.1 J B AT1
1 2 P C H _ I N T V RMEN 1 2 H D A _ S P KR C ONN@
1
2
3 2 .768KHZ_12.5PF_Q13MC14610002
R 162 330K_0402_5% R 1 63 @ 1K_0402_5% ACES_85205-0200
High = Internal VR Enabled(Default) D1
LOW=Default HIGH=No Reboot 2
1 R 1 98
1
4
18P_0402_50V8J
T127 P C H _ R T C RST# W=20mils 3 1 2

1 1 1 W=20mils W=20mils
OSC
OSC
C 1 90 C 191 C 215 D A N 2 02U_SC70 1K_0402_5%

18P_0402_50V8J 1 U_0603_10V4Z
A U4A Place near IBEX-M A
2 2 2
NC
NC
Y3 1 P C H _ RTCX1 B13 D33 L P C _LAD0 28,33,35,36
1
+ R T C V CC C L R P1 P C H _ RTCX2 RTCX1 FWH0 / LAD0
D13 B33
2
RTCX2 FWH1 / LAD1 L P C _LAD1 28,33,35,36

C 192 C32
FWH2 / LAD2 L P C _LAD2 28,33,35,36
1 U_0603_10V4Z S H O R T P ADS A32
2
2 FWH3 / LAD3 L P C _LAD3 28,33,35,36
1 2 P C H _ R T C RST# C14
R 164 20K_0402_1% RTCRST# + 3VS
C34 L P C _ L FRAME# 28,33,35,36
2009/04/13 DB-3 Compal WLAN nosie P C H _ S R T CRST# FWH4 / LFRAME#
1 2 D17
SRTCRST#
1 @ 2 H D A _ B I T _CLK_MDC R 165 20K_0402_1% A34 1 2 N A N D _ D ET#
RTC
LPC
1 LDRQ0# L P C _LDRQ#0 36
C 193 22P_0402_50V8J S M _ I N T R UDER# A16 F34 N A N D _ D ET# R 1159 10K_0402_5%
INTRUDER# LDRQ1# / GPIO23
1 @ 2 H D A _ B I T _ C LK_CODEC C 195 2009/02/18 HP DB-2 2009/05/02 HP SI-1
C 194 22P_0402_50V8J 1 U_0603_10V4Z 2009/04/24 HP SI-1 P C H _ I N T V RMEN A14 AB9 SIRQ 2009/08/30 HP PV
2 INTVRMEN SERIRQ SIRQ 30,33,35,36
1 @ 2 H D A _ S D O U T_MDC
C 200 22P_0402_50V8J 2009/02/11 HP DB-2
1 @ 2 H D A _ S D O U T _ CODEC
C 201 22P_0402_50V8J R 167 1 2 33_0402_5% H D A _ B IT_CLK A30
31 H D A _ B I T _CLK_MDC HDA_BCLK
R 168 1 2 33_0402_5% AK7 S A TA_PRX_DTX_N0 S A TA_PRX_DTX_N0 T130
31 H D A _ B I T _ CLK_CODEC SATA0RXN S A TA_PRX_DTX_N0 29
R 169 1 2 33_0402_5% H DA_SYNC D29 AK6 S ATA_PRX_DTX_P0 S ATA_PRX_DTX_P0 T131
31 H D A _ S Y N C _ M DC HDA_SYNC SATA0RXP S ATA_PRX_DTX_P0 29
R 170 1 2 33_0402_5% HDD AK11 S A TA_PTX_DRX_N0 S A TA_PRX_DTX_N1 T132
31 H D A _ S Y N C _ C O D EC SATA0TXN S A TA_PTX_DRX_N0 29
H D A _ S P KR P1 AK9 S ATA_PTX_DRX_P0 S ATA_PRX_DTX_P1 T133
31 H D A _ S P KR SPKR SATA0TXP S ATA_PTX_DRX_P0 29
R 172 1 2 33_0402_5% H D A _ R ST# C30
31 H D A _ R S T#_MDC HDA_RST#
R 173 1 2 33_0402_5% AH6 S A TA_PRX_DTX_N1 S A TA_PRX_DTX_N2 T134
31 H D A _ R S T # _CODEC SATA1RXN S A TA_PRX_DTX_N1 29
AH5 S ATA_PRX_DTX_P1 S ATA_PRX_DTX_P2 T135
SATA1RXP S ATA_PRX_DTX_P1 29 + 3VS
31 H D A _ S D IN0 H D A _ S D IN0 G30 ODD AH9 S A TA_PTX_DRX_N1 S A TA_PRX_DTX_N5 T136
HDA_SDIN0 SATA1TXN S A TA_PTX_DRX_N1 29
AH8 S ATA_PTX_DRX_P1 S ATA_PRX_DTX_P5 T137
SATA1TXP S ATA_PTX_DRX_P1 29
31 H D A _ S D IN1 H D A _ S D IN1 F30
HDA_SDIN1 S A TA_PRX_DTX_N2
AF11 S A TA_PRX_DTX_N2 34
SATA2RXN
1
E32 AF9 S ATA_PRX_DTX_P2
IHDA
HDA_SDIN2 SATA2RXP S ATA_PRX_DTX_P2 34
DOCKINGSATA2TXN AF7 S A TA_PTX_DRX_N2 R 6 81 @ R 790 @
S A TA_PTX_DRX_N2 34 10K_0402_5%
F32 AF6 S ATA_PTX_DRX_P2 330K_0402_5%
HDA_SDIN3 SATA2TXP S ATA_PTX_DRX_P2 34
AH3 2009/02/06 HP DB-2 S A TA_PRX_DTX_N4 T140
2
R 176 1 SATA3RXN
31 H D A _ S D O U T_MDC 2 33_0402_5% H D A _ S D OUT B29 AH1 S ATA_PRX_DTX_P4 T141
2008/12/12 HP A Q U A W H I T E_BATLED
B
R 177 1 2 33_0402_5% HDA_SDO SATA3RXP AF3
B
31 H D A _ S D O U T _ CODEC SATA3TXN
1
D 2009/02/06 HP DB-2
AF1
A Q U A W H I T E_BATLED R 1144 1 2 1K_0402_5% G PIO33 H32 SATA3TXP 2 Q 63
SATA
HDA_DOCK_EN# / GPIO33 31,35 A Q U A W H I T E_BATLED#
2009/02/20 HP DB-2 AD9 S A TA_PRX_DTX_N4 G 2N7002H_SOT23-3
SATA4RXN S A TA_PRX_DTX_N4 29
+ 3 V ALW 1 2 J30 AD8 S ATA_PRX_DTX_P4 S
3
HDA_DOCK_RST# / GPIO13 SATA4RXP S ATA_PRX_DTX_P4 29
R 1225 10K_0402_5% E-SATASATA4TXN AD6 S A TA_PTX_DRX_N4 2009/05/12 HP SI-1
S A TA_PTX_DRX_N4 29
AD5 S ATA_PTX_DRX_P4
P C H _ J T AG_TCK M3 AD3 S A TA_PRX_DTX_N5
iTPM ENABLE/DISABLE JTAG_TCK SATA5RXN
SATA5RXP
AD1 S ATA_PRX_DTX_P5
S A TA_PRX_DTX_N5
S ATA_PRX_DTX_P5
34
34
P C H _ J TAG_TMS K3 DOCKINGSATA5TXN AB3 S A TA_PTX_DRX_N5
+ 3VS JTAG_TMS S A TA_PTX_DRX_N5 34
AB1 S ATA_PTX_DRX_P5
P C H _ J TAG_TDI K1
JTAG_TDI + 3 VS
JTAG
1 2 K B C _ S PI_SI_R P C H _ J TAG_TDO J2 AF16
R 1 86 @ 1K_0402_5% JTAG_TDO SATAICOMPO
P C H _ J TAG_RST# J4 AF15 1 2 + 1.05VS
Enable=Stuff Disable=No Stuff JTAG_RST# SATAICOMPI R 180 37.4_0402_1%
1
R 183 R 184 @
R 1026 1 2 15_0402_5% P C H _ S P I_CLK BA2 10K_0402_5% 10K_0402_5%
for SMSC EC 35 K B C _ S P I_CLK_R SPI_CLK
R 181 1 2 0_0402_5% P C H _ S PI_CS0# AV3 1 2 + 3VS
35 K B C _ S PI_CS0#_R
2
SPI_CS0# R 182 10K_0402_1%
R 185 1 2 0_0402_5% P C H _ S PI_CS1# AY3 T3 S A TA_DET#0
35 K B C _ S PI_CS1#_R SPI_CS1# SATALED# S A TA_LED# 31,34
R 1027 1 2 15_0402_5% P C H _ S PI_SI AY1 Y9 S A TA_DET#0 H D D _ H A L TLED

35 K B C _ S PI_SI_R SPI_MOSI SATA0GP / GPIO21
notice KBC state
SPI
35 K B C _ SPI_SO
2009/02/06 HP DB-2 AV1 V1 H D D _ H A L TLED_RR 1096 1 2 0_0402_5%
SPI_MISO SATA1GP / GPIO19 H D D _ H A L TLED 31
I B E X PEAK-M_FCBGA1071
C C
GPIO33 iAMT Enable /Disable
Hi Disable
Lo Enable Default PCH XDP Conn.
J P 15
1 2
GND0 GND1 R 796 1 @
3 4 X D P _FN17 2 33_0402_5% P C H _ XDP_GPIO28 15 GPIO_28
5 OBSFN_A0 OBSFN_C0 6 X D P _FN16 R 797 1 @ 2 33_0402_5%
OBSFN_A1 OBSFN_C1 P C H _ XDP_GPIO0 15 GPIO_0
7 8
33_0402_5% 1 @ 2 R 798 X D P _FN0 9 GND2 GND3 10 X D P _FN8 R 799 1 @ 2 33_0402_5%
15 U S B _ OC#0 OBSDATA_A0 OBSDATA_C0 P C H _ XDP_GPIO20 13
33_0402_5% 1 @ 2 R 800 X D P _FN1 11 12 X D P _FN9 R 801 1 @ 2 33_0402_5%
15 U S B _ OC#1 OBSDATA_A1 OBSDATA_C1 P C H _ XDP_GPIO18 13
13 14
+ 3 VALW + 3 V ALW + 3 V ALW + 3 V ALW 33_0402_5% 1 @ GND4 GND5
15 U S B _ OC#2 2 R 802 X D P _FN2 15 16 X D P _FN10 R 803 1 @ 2 33_0402_5% S A TA_DET#0
33_0402_5% 1 @ OBSDATA_A2 OBSDATA_C2
15 U S B _ OC#3 2 R 804 X D P _FN3 17 18 X D P _FN11 R 805 1 @ 2 33_0402_5% H D D _ H A L TLED_R
19 OBSDATA_A3 OBSDATA_C3 20
1
GND6 GND7 2009/02/16 HP DB-2

21 22
R 188 R 189 R 1 90 R 191 @ OBSFN_B0 OBSFN_D0
23 24
200_0402_5% 200_0402_5% 200_0402_5% 20K_0402_5% 2008/12/12 HP 25 OBSFN_B1 OBSFN_D1 26
33_0402_5% 1 @ GND8 GND9 GPIO_36
2009/03/08 HP SI-1
15 U S B _ OC#4 2 R 1095 27 28 X D P _FN12 R 807 1 @ 2 33_0402_5% P C H _ XDP_GPIO36 15 GPIO_37
33_0402_5% 1 @ OBSDATA_B0 OBSDATA_D0
15 U S B _ OC#5 2 R 808 X D P _FN5 29 30 X D P _FN13 R 809 1 @ 2 33_0402_5% P C H _ XDP_GPIO37 15,19
2
P C H _ J TAG_TMS P C H _ J TAG_TDO P C H _ J TAG_TDI P C H _ J TAG_RST# 31 OBSDATA_B1 OBSDATA_D1 32

33_0402_5% 1 @ GND10 GND11 GPIO_16
15 U S B _ OC#6 2 R 810 X D P _FN6 33 34 X D P _FN14 R 811 1 @ 2 33_0402_5% P C H _ XDP_GPIO16 15 GPIO_49
1
33_0402_5% 1 @ OBSDATA_B2 OBSDATA_D2

15 U S B _ OC#7 2 R 812 X D P _FN7 35 36 X D P _FN15 R 813 1 @ 2 33_0402_5% P C H _ XDP_GPIO49 15
R 194 R 195 R 1 96 OBSDATA_B3 OBSDATA_D3
37 38
100_0402_1% 100_0402_1% 100_0402_1% R 197 @ PWR_GD 39 GND12 GND13 40
10K_0402_5% 35,37 P W R _ G D PWRGOOD/HOOK0 ITPCLK/HOOK4
R 814 1 2 X D P _ P W RBTN#_R 41 42
4,14 P M _ P W R B TN#_R HOOK1 ITPCLK#/HOOK5
+ 3VS 0_0402_5% 43 44 + 3 VS
2
VCC_OBS_AB VCC_OBS_CD R 815 1

45 46 2 1K_0402_5% P LT_RST# 4,15,20,26,28,31,33
+ 1.05VS HOOK2 RESET#/HOOK6
47 48 X D P _ DBRESET# 4,14
2009/02/06 HP DB-2 HOOK3 DBR#/HOOK7
49 50
51 GND14 GND15 52 P C H _ J T AG_TDO#_R R 816 1 2 0_0402_5% P C H _ J TAG_TDO
D T128 SDA TD0 D
P C H _ J TAG_TDO R 1105 1 @ 2 51_0402_5% T129 53 54 P C H _ J T AG_RST#_R R 817 1 @ 2 0_0402_5% P C H _ J TAG_RST#
PCH Pin RefDes PCH JTAG Pre-Production PCH JTAG Production PWR_GD SCL TRST# P C H _ J T AG_TDI_R R 818 0_0402_5% P C H _ J TAG_TDI
55 56 1 2
P C H _ J TAG_TMS R 1106 @ TCK1 TDI
ES1 ES2 MP 1 2 51_0402_5% P C H _ J T AG_TCK 1 2 P C H _ J T AG_TCK_R 57 58 P C H _ J TAG_TMS_R R 820 1 2 0_0402_5% P C H _ J TAG_TMS
R189 No Install 200ohm No Install R 819 0_0402_5% 59 TCK0 TMS 60
1 GND16 GND17
PCH_JTAG_TDO R195 No Install 100ohm No Install P C H _ J TAG_TDI R 1107 1 @ 2 51_0402_5%
R No Install No Install 51ohm C 9 98 @ SAMTE_BSH-030-01-L-D-A C ONN@
R188 200ohm 200ohm No Install P C H _ J TAG_RST# R 1108 1 @ 2 51_0402_5% 0.1U_0402_25V4K
PCH_JTAG_TMS R
R194 100ohm 100ohm No Install 2
R No Install No Install 51ohm P C H _ J T AG_TCK R 199 1 2 51_0402_5%
PCH_JTAG_TDI
R190
R196
200ohm
100ohm
200ohm
100ohm
No Install
No Install
2009/09/15 Compal ESD PV S ecurity Classification Compal Secret Data Compal Electronics, Inc.
R No Install No Install 51ohm
PCH_JTAG_TCK R199 51ohm 51ohm 51ohm
IBEX-M(1/6)-HDA/JTAG/SATA
R191 20Kohm 20Kohm No Install Size D o c u m ent Number Rev
PCH_JTAG_RST# R197 10Kohm 10Kohm No Install
C u s t om L A -4 9 0 1 P 1 .0
R No Install No Install 51ohm MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1 2 3 4 5
1 2 3 4 5
S M B _CLK_S3 R 200 1 2 10K_0402_5% + 3VS S M B CLK R 201 1 2 2.2K_0402_5% + 3 V ALW

S M B _DATA_S3 R 202 1 2 10K_0402_5% S M B D ATA R 203 1 2 2.2K_0402_5%
S M L0CLK R 205 1 2 2.2K_0402_5%

2009/01/20 intel WoW
S M L 0DATA R 207 1 2 2.2K_0402_5%
P E G _ C LKREQ# R 209 1 2 10K_0402_5%
2009/02/20 HP DB-2
A A
S M L1ALERT# R 211 1 2 10K_0402_5%
S M L0ALERT# R 958 1 2 10K_0402_5%

2009/08/30 HP PV
U 4B L _ L ID_SW# R 959 1 2 10K_0402_5%
BG30 B9 L _ L ID_SW# 2009/07/03 SI-1b S M L1CLK R 1092 1 2 4.7K_0402_5%

PERN1 SMBALERT# / GPIO11 2009/08/30 HP PV
BJ30
PERP1 S M B CLK S M L 1DATA R 1093 1
BF29 H14 2 4.7K_0402_5%
PETN1 SMBCLK
BH29
PETP1 C8 S M B D ATA 2009/02/20 HP DB-2
P C I E_PRX_DTX_N2 AW30 SMBDATA DDR
31 P C I E_PRX_DTX_N2 PERN2
31 P C I E_PRX_DTX_P2 P C IE_PRX_DTX_P2 BA30
C 216 1 PERP2
EXP 31 P C I E _PTX_C_DRX_N2 2 0.1U_0402_10V7K P C I E_PTX_DRX_N2 BC30 J14 S M L0ALERT#
C 217 1 PETN2 SML0ALERT# / GPIO60
31 P C I E_PTX_C_DRX_P2 2 0.1U_0402_10V7K P C IE_PTX_DRX_P2 BD30
PETP2 S M L0CLK
C6 S M L0CLK 26
AU30 SML0CLK
Intel LAN
SMBus
PERN3 S M L 0DATA Q 6A
AT30 G8 S M L0DATA 26
AU32 PERP3 SML0DATA 2 N 7 002DWH_SOT363-6
PETN3 S M B CLK S M B _CLK_S3
AV32 S M B CLK 6 1 S M B _CLK_S3 4,9,10,11,32
PETP3 M14 S M L1ALERT#
P C I E_PRX_DTX_N4 BA32 SML1ALERT# / GPIO74
28 P C I E_PRX_DTX_N4 PERN4
28 P C I E_PRX_DTX_P4 P C IE_PRX_DTX_P4 BB32 E10 S M L1CLK
2
C 218 1 PERP4 SML1CLK / GPIO58
WLAN 28 P C I E _PTX_C_DRX_N4 2 0.1U_0402_10V7K P C I E_PTX_DRX_N4 BD32 CBB
C 219 1 PETN4
28 P C I E_PTX_C_DRX_P4 2 0.1U_0402_10V7K P C IE_PTX_DRX_P4 BE32 G12 S M L 1DATA
PETP4 SML1DATA / GPIO75 Q 6B
PCI-E*
BF33 2 N 7 002DWH_SOT363-6
PERN5 S M B D ATA 3 S M B _DATA_S3
BH33 T13 4
Controller
PERP5 CL_CLK1 C L _ CLK 28 S M B D ATA S M B _DATA_S3 4,9,10,11,32
BG32
PETN5 + 3VS
BJ32 T11 C L _ DATA 28
PETP5 CL_DATA1
Link
5
26 P C I E_PRX_DTX_N6 P C I E_PRX_DTX_N6 BA34 T9
PERN6 CL_RST1# C L _RST# 28
26 P C I E_PRX_DTX_P6 P C IE_PRX_DTX_P6 AW34
B
C 222 1 2 0.1U_0402_10V7K P C I E_PTX_DRX_N6 BC34 PERP6 B
NIC 26 P C I E _PTX_C_DRX_N6
C 223 1 PETN6
26 P C I E_PTX_C_DRX_P6 2 0.1U_0402_10V7K P C IE_PTX_DRX_P6 BD34
PETP6 H1 P E G _ C LKREQ#
PEG_A_CLKRQ# / GPIO47
AT34
PERN7
AU34
PERP7
AU36 AD43 C L K _PEG_VGA# 20
PETN7 CLKOUT_PEG_A_N R 1146 1 @
AV36 100MHz CLKOUT_PEG_A_P AD45 C L K _ PEG_VGA 20
S M B CLK 2 0_0402_5% S M L1CLK
PETP7
BG34 AN4 S M B D ATA R 1147 1 @ 2 0_0402_5% S M L 1DATA
PERN8 CLKOUT_DMI_N C LK_EXP# 4
PEG
BJ34
PERP8
100MHz CLKOUT_DMI_P
AN2 C LK_EXP 4
BG36
PETN8 R 913 1
BJ36 2 0_0402_5% C A P _ CLK 31,35
PETP8 AT1 C L K _DP#
CLKOUT_DP_N / CLKOUT_BCLK1_N T27
120/133MHz AT3 C L K _ DP T28 Q7A Q 76A
CLKOUT_DP_P / CLKOUT_BCLK1_P 2 N 7 002DWH_SOT363-6 2 N 7 002DWH_SOT363-6
AK48
AK47 CLKOUT_PCIE0N S M L1CLK S M L 1_CLK_R
1 6 6 1 S M L1_CLK 20
CLKOUT_PCIE0P
From CLK BUFFER

AW24 C L K _DMI# 11
R 8 21 1 CLKIN_DMI_N
+ 3 V ALW 2 10K_0402_5% P9 100MHz BA24 C L K _DMI 11
PCIECLKRQ0# / GPIO73 CLKIN_DMI_P
2
12 P C H _ XDP_GPIO18
AM43 AP3 09/02/22 HP DB-2
CLKOUT_PCIE1N CLKIN_BCLK_N C L K _ B U F_BCLK# 11
26 C L K _ P C IE_LAN_REQ1# AM45 133MHz AP1 Q7B Q 76B
CLKOUT_PCIE1P CLKIN_BCLK_P C L K _ B U F_BCLK 11
2009/05/02 HP SI-1 2 N 7 002DWH_SOT363-6 2 N 7 002DWH_SOT363-6
+ 3VS R 212 1 2 10K_0402_5% R 1198 1 2 0_0402_5% U4 S M L 1DATA 4 3 S M L 1_DATA_R 3 4
PCIECLKRQ1# / GPIO18 S M L 1_DATA 20
F18 C L K _ B UF_DOT96# 11
R 213 CLKIN_DOT_96N + 3 VALW + 3VS
96MHz CLKIN_DOT_96P
E18 C L K _ B UF_DOT96 11
1 2 0_0402_5% C L K _ PCIE_EXP#_R AM47
5
31 C L K _PCIE_EXP# CLKOUT_PCIE2N
2 0_0402_5% C L K _ PCIE_EXP_R
CLKOUT_PCIE2P 100MHz
EXP 31 C L K _ PCIE_EXP 1 AM48
R 214 AH13
CLKIN_SATA_N / CKSSCD_N C L K _ B U F _ C KSSCD# 11
12 P C H _ XDP_GPIO20 N4 100MHz CLKIN_SATA_P / CKSSCD_P AH12 R 914 1 2 0_0402_5%
PCIECLKRQ2# / GPIO20 C L K _ B U F _ C KSSCD 11 C A P _ DAT 31,35
+ 3VS R 2 04 1 2 10K_0402_5%
2008/12/12 HP AH42 P41
CLKOUT_PCIE3N REFCLK14IN C L K _ 14M_PCH 11
31 C L K REQ_EXP# R 1009 1 2 0_0402_5% AH41
C
CLKOUT_PCIE3P C
+ 3 V ALW R 2 06 1 2 10K_0402_5% A8 J42
PCIECLKRQ3# / GPIO25 CLKIN_PCILOOPBACK C L K _ P CI_FB 15
R 216
28 C L K _ P C I E _MCARD# 1 2 0_0402_5% C L K _ P C I E _ MCARD#_R AM51 AH51 XTAL25_IN
CLKOUT_PCIE4N XTAL25_IN
2 0_0402_5% C L K _ P C I E _ MCARD_R XTAL25_OUT
WLAN CLKOUT_PCIE4P 100MHz
28 C L K _ P C I E _MCARD 1 AM53 AH53
R 217 XTAL25_OUT
28 C L K R E Q _ WLAN# M9 AF38 R 218 1 2 90.9_0402_1% + 1.05VS
PCIECLKRQ4# / GPIO26 XCLK_RCOMP
2009/02/06 HP DB-2
+ 3 V ALW R 3 54 1 2 10K_0402_5% AJ50 T45 T93
AJ52 CLKOUT_PCIE5N CLKOUTFLEX0 / GPIO64
CLKOUT_PCIE5P
R 3 53 1 2 10K_0402_5% H6 P43
Clock Flex
+ 3 V ALW PCIECLKRQ5# / GPIO44 CLKOUTFLEX1 / GPIO65 T94
AK53 T42 C L K_14M_SIO_P R 222 1 2 22_0402_5% This circuit will add/delete in INTEL ES2 sample to test.
CLKOUT_PEG_B_N CLKOUTFLEX2 / GPIO66 C L K_14M_SIO 36
XTAL25_IN
CLKOUT_PEG_B_P 100MHz
AK51
2009/02/06 HP DB-2 2009/05/19 HP SI-1
+ 3 V ALW R 1138 1 2 10K_0402_5% P13 N50 1 XTAL25_OUT 1 @ 2
PEG_B_CLKRQ# / GPIO56 CLKOUTFLEX3 / GPIO67 C 833 @ R 215 1M_0402_5%
10P_0402_50V8C Y4
I B E X P EAK-M_FCBGA1071
For SMSC SIO 14MHz CLK out 2 1 2
@
2 5 M HZ_20P_1BG25000CK1A
18P_0402_50V8J
18P_0402_50V8J
1 C 226 1 C 2 27
@
2009/04/10 HP DB-3
2 2
the P/N is chaged to SD028000080

D D

IBEX-M(2/6)-PCI-E/SMBUS/CLK
C u s t om L A -4 9 0 1 P 1 .0
1 2 3 4 5
1 2 3 4 5
U 4C U 4D
BA18 T48 BJ46
D M I_CTX_PRX_N0 BC24 FDI_RXN0 BH17 T47 L_BKLTEN SDVO_TVCLKINN BG46
5 D M I_CTX_PRX_N0 DMI0RXN FDI_RXN1 L_VDD_EN SDVO_TVCLKINP
5 D M I_CTX_PRX_N1 D M I_CTX_PRX_N1 BJ22 BD16
D M I_CTX_PRX_N2 AW20 DMI1RXN FDI_RXN2
5 D M I_CTX_PRX_N2 BJ16 Y48 BJ48
D M I_CTX_PRX_N3 BJ20 DMI2RXN FDI_RXN3 L_BKLTCTL SDVO_STALLN
5 D M I_CTX_PRX_N3 BA16 BG48
DMI3RXN FDI_RXN4 SDVO_STALLP
BE14 AB48
D M I_CTX_PRX_P0 FDI_RXN5 L_DDC_CLK
5 D M I_CTX_PRX_P0 BD24 BA14 Y45 BF45
D M I_CTX_PRX_P1 DMI0RXP FDI_RXN6 L_DDC_DATA SDVO_INTN
5 D M I_CTX_PRX_P1 BG22 BC12 BH45
D M I_CTX_PRX_P2 DMI1RXP FDI_RXN7 SDVO_INTP
5 D M I_CTX_PRX_P2 BA20 AB46
D M I_CTX_PRX_P3 DMI2RXP L_CTRL_CLK
5 D M I_CTX_PRX_P3 BG20 BB18 V48
DMI3RXP FDI_RXP0 L_CTRL_DATA
BF17
D M I_CRX_PTX_N0 BE22 FDI_RXP1
A
5 D M I_CRX_PTX_N0 BC16 AP39 T51 A
D M I_CRX_PTX_N1 BF21 DMI0TXN FDI_RXP2 LVD_IBG SDVO_CTRLCLK
5 D M I_CRX_PTX_N1 BG16 AP41 T53
D M I_CRX_PTX_N2 BD20 DMI1TXN FDI_RXP3 LVD_VBG SDVO_CTRLDATA
5 D M I_CRX_PTX_N2 AW16
D M I_CRX_PTX_N3 BE18 DMI2TXN FDI_RXP4
5 D M I_CRX_PTX_N3 BD14 AT43
DMI3TXN FDI_RXP5 LVD_VREFH
BB14 AT42 BG44
D M I_CRX_PTX_P0 FDI_RXP6 LVD_VREFL DDPB_AUXN
5 D M I_CRX_PTX_P0 BD22 BD12 BJ44
D M I_CRX_PTX_P1 DMI0TXP FDI_RXP7 DDPB_AUXP
5 D M I_CRX_PTX_P1 BH21 AU38
DMI1TXP DDPB_HPD
LVDS
D M I_CRX_PTX_P2 BC20 AV53
5 D M I_CRX_PTX_P2 DMI2TXP LVDSA_CLK#
D M I_CRX_PTX_P3 BD18 BJ14 R 1165 1 2 1K_0402_5% AV51 BD42
5 D M I_CRX_PTX_P3 DMI3TXP FDI_INT LVDSA_CLK DDPB_0N
BC42
DMI
FDI
R 1166 1 DDPB_0P
BF13 2 1K_0402_5% BB47 BJ42
FDI_FSYNC0 LVDSA_DATA#0 DDPB_1N
Digital Display Interface

+ 1.05VS BH25 BA52 BG42
DMI_ZCOMP BH13 R 1167 1 2 1K_0402_5% AY48 LVDSA_DATA#1 DDPB_1P BB40
D M I _ I R COMP FDI_FSYNC1 LVDSA_DATA#2 DDPB_2N
1 2 BF25 AV47 BA40
R 227 49.9_0402_1% DMI_IRCOMP R 1168 1 LVDSA_DATA#3 DDPB_2P
BJ12 2 1K_0402_5% AW38
FDI_LSYNC0 DDPB_3N
BB48 BA38
R 1169 1 LVDSA_DATA0 DDPB_3P
BG14 2 1K_0402_5% BA50
FDI_LSYNC1 LVDSA_DATA1
AY49
AV48 LVDSA_DATA2 Y49
LVDSA_DATA3 DDPC_CTRLCLK
AB49
DDPC_CTRLDATA
AP48
AP47 LVDSB_CLK# BE44
LVDSB_CLK DDPC_AUXN BD44
DDPC_AUXP
4,12 X D P _ D BRESET# 1 2 S Y S _ R ST# T6 J12 P C I E _ W AKE#
P C I E _ W AKE# 28,31 AY53 AV40
R 228 0_0402_5% SYS_RESET# WAKE# AT49 LVDSB_DATA#0 DDPC_HPD
LVDSB_DATA#1
AU52 BE40
V G ATE M6 Y1 P M _ C L K RUN# AT53 LVDSB_DATA#2 DDPC_0N BD40
35,46 V G ATE SYS_PWROK CLKRUN# / GPIO32 P M _ C L K RUN# 30,33,35,36 LVDSB_DATA#3 DDPC_0P
System Power Management

BF41
DDPC_1N
AY51 BH41
LVDSB_DATA0 DDPC_1P
B17 AT48 BD38
PWROK LVDSB_DATA1 DDPC_2N
AU50 BC38
LVDSB_DATA2 DDPC_2P
AT51 BB36
1 2 S U S _STAT# LVDSB_DATA3 DDPC_3N
37 M _ P W R OK K5 P8 T142 BA36
R 2 30 0_0402_5% MEPWROK SUS_STAT# / GPIO61 2009/08/30 HP PV DDPC_3P
B B
1 A U X P W ROK A10
2 F3 S U S _ CLK T30 AA52 U50
R 2 31 0_0402_5% LAN_RST# SUSCLK / GPIO62 AB53 CRT_BLUE DDPD_CTRLCLK U52
CRT_GREEN DDPD_CTRLDATA
AD53
P M _ D R A M _ P WRGD D9 CRT_RED
4 P M _ D R A M _ P WRGD E4 S L P_S5# 34
DRAMPWROK SLP_S5# / GPIO63
BC46
R 232 1 DDPD_AUXN
42 R P G O O D 2 0_0402_5% V51 BD46
CRT_DDC_CLK DDPD_AUXP
35 P M _ R SMRST# 1 2 C16 H7 S L P_S4# 38,45 V53 AT38
R 233 10K_0402_5% RSMRST# SLP_S4# CRT_DDC_DATA DDPD_HPD
+ 3 V ALW R 1063 1 2 10K_0402_5% BJ40
M1 P12 Y53 DDPD_0N BG40
35 S U S _ P W R _ ACK SUS_PWR_ACK / GPIO30 SLP_S3# S L P_S3# 31,35,37,38,40,42,43,44,48 CRT_HSYNC DDPD_0P
Y51 BJ38
CRT_VSYNC DDPD_1N BG38
4,12 P M _ P W R B TN#_R DDPD_1P
CRT
31 O N / O F F B TN# 1 2 P5 K8 P M _SLP_M# 35,37,38 BF37
R 234 0_0402_5% PWRBTN# SLP_M# DDPD_2N
AD48 BH37
DAC_IREF DDPD_2P
1K_0402_0.5%
AB51 BE36
CRT_IRTN DDPD_3N
1
R 235
20,35 A C _ P R E SENT P7 N2 BD36
ACPRESENT / GPIO31 TP23 DDPD_3P
L O W _BAT#_R A6 BJ10
BATLOW# / GPIO72 PMSYNCH H _ PM_ SYN C 4
2
2008/12/06 follow UMA
I BEX_R# F14 F6 P M _ SLP_LAN#
RI# SLP_LAN# P M _ SLP_LAN# 35,38,45
I B E X P EAK-M_FCBGA1071
+ 3 VS
V G ATE T120 P M _ C L K RUN# R 2 37 1 2 10K_0402_5%

C S LP_S3# T121 C
P M_SLP_M# T122
A U X P W ROK + 3 V ALW
T123
S U S _ P W R _ ACK T124
2009/01/22 HP DB-2
P M _ R SMRST# T125 S Y S _ R ST# R 2 39 1 @ 2 10K_0402_5%
M _ P W R OK T126
L O W _BAT#_R R 2 40 1 2 10K_0402_5% V G ATE R 229 1 2 10K_0402_5%
P M _ SLP_LAN# R 2 41 1 2 10K_0402_5%
I BEX_R# R 2 42 1 2 10K_0402_5% S LP_S3# R 915 1 @ 2 10K_0402_5%

2009/09/15 HP SI-2b
P C I E _ W AKE# R 2 43 1 2 10K_0402_5% S LP_S4# R 916 1 @ 2 10K_0402_5%
A C _ P R E SENT R 9 18 1 @ 2 10K_0402_5% S LP_S5# R 917 1 @ 2 10K_0402_5%
2009/05/16 HP SI-1
D D

IBEX-M(3/6)-DMI/GPIO/LVDS
C u s t om L A - 4 9 0 1 P 1 .0
1 2 3 4 5
1 2 3 4 5
30 P C I _ A D[0..31] U4E U4F

P C I _ AD0 H40 AY9 R 223
AD0 NV_CE#0 R 244 1
P C I _ AD1 N34 BD1 + 3VS 2 10K_0402_5% P C H _ XDP_GPIO0 Y3 AH45 C L K _ P C IE_LAN#_R 1 2 0_0402_5% C L K _ P CIE_LAN# 26
P C I _ AD2 AD1 NV_CE#1 BMBUSY# / GPIO0 CLKOUT_PCIE6N C L K _ P C IE_LAN_R 1
C44 AP15 12 P C H _ XDP_GPIO0 AH46 2 0_0402_5% C L K _ P CIE_LAN 26 LAN
P C I _ AD3 A38 AD2 NV_CE#2 BD8 C38 CLKOUT_PCIE6P R 225
AD3 NV_CE#3 47 O C P# TACH1 / GPIO1
P C I _ AD4 C36
P C I _ AD5 J34 AD4 AV9 R U N S C I _ EC# D37
AD5 NV_DQS0 35 R U N S C I _ EC# TACH2 / GPIO6
P C I _ AD6 A40 BG8 AF48
AD6 NV_DQS1 CLKOUT_PCIE7N
MISC
P C I _ AD7 D45 T H E R M _SCI# J32 AF47
AD7 4 T H E R M _SCI# TACH3 / GPIO7 CLKOUT_PCIE7P
P C I _ AD8 E36 AP7
AD8 NV_DQ0 / NV_IO0 10K_0402_5%
P C I _ AD9 H48 AP6 4,5 P C H _ D D R _ RST F10 1 2 R 247 + 3VS
P C I _ AD10 AD9 NV_DQ1 / NV_IO1 2009/08/30 HP PV 2009/07/02 HP SI-1b 2009/04/10 HP DB-3 GPIO8
E40 AT6
P C I _ AD11 AD10 NV_DQ2 / NV_IO2
C40 AT9 26,27 L A N _DIS# K9 U2 G ATEA20 35
P C I _ AD12 AD11 NV_DQ3 / NV_IO3 LAN_PHY_PWR_CTRL / GPIO12 A20GATE
M48 BB1
P C I _ AD13 AD12 NV_DQ4 / NV_IO4 G PIO15
M45 AV6 T7
P C I _ AD14 AD13 NV_DQ5 / NV_IO5 GPIO15
F53 BB3
P C I _ AD15 AD14 NV_DQ6 / NV_IO6 P C H _ XDP_GPIO16
A M40 BA4 12 P C H _ XDP_GPIO16 AA2 AM3 C L K _ C P U_BCLK# 4
A
AD15 NV_DQ7 / NV_IO7 SATA4GP / GPIO16 CLKOUT_BCLK0_N / CLKOUT_PCIE8N
NVRAM
P C I _ AD16 M43 BE4
P C I _ AD17 AD16 NV_DQ8 / NV_IO8 A L S _EN#
J36 BB6 19 A L S_EN# F38 AM1 C L K _ C P U_BCLK 4
P C I _ AD18 AD17 NV_DQ9 / NV_IO9 TACH0 / GPIO17 CLKOUT_BCLK0_P / CLKOUT_PCIE8P
K48 BD6
AD18 NV_DQ10 / NV_IO10 P C H _ P E C I_R 0_0402_5%1
P C I _ AD19 F40 BB7 28 W W A N _ D E T# W W A N _ D E T# Y7 BG10 2 R 248 H _ P E CI 4
AD19 NV_DQ11 / NV_IO11 SCLOCK / GPIO22 PECI
GPIO
P C I _ AD20 C42 BC8
P C I _ AD21 AD20 NV_DQ12 / NV_IO12 2009/04/10 HP DB-3 G PIO24 K B _ RST#
K46 BJ8 H10 T1 K B _RST# 35
P C I _ AD22 AD21 NV_DQ13 / NV_IO13 MEM_LED / GPIO24 RCIN#
M51 BJ6
P C I _ AD23 AD22 NV_DQ14 / NV_IO14 W W A N _ T R A N S M IT_OFF#
J52 BG6 28,33 W W A N _ T R A N S M IT_OFF# AB12 BE10 H_CPUPWRGD 4
AD23 NV_DQ15 / NV_IO15 GPIO27 PROCPWRGD
CPU
P C I _ AD24 K51
P C I _ AD25 L34 AD24 BD3 N V _ ALE V13 BD10 H _ T H E RMTRIP#_L
12 P C H _ XDP_GPIO28 1 2 H _ T H E RMTRIP# 4,20
P C I _ AD26 AD25 NV_ALE N V _ C LE GPIO28 THRMTRIP# 54.9_0402_1% R 249
F42 AY6
1
P C I _ AD27 J40 AD26 NV_CLE S T P _PCI# M11
AD27 S T P _PCI# STP_PCI# / GPIO34
P C I _ AD28 G46
P C I _ AD29 AD28 @ 2009/08/30 HP PV S A T A _ CLKREQ# R 250
F44 AU2 1 2 S A T A _CLKREQ# V6
P C I _ AD30 AD29 NV_RCOMP R 251 32.4_0402_1% SATACLKREQ# / GPIO35 56_0402_5%
M47
AD30
PCI
P C I _ AD31 H36 AV7 P C H _ XDP_GPIO36 AB7 BA22 T33
2
AD31 NV_RB# 12 P C H _ XDP_GPIO36 SATA2GP / GPIO36 TP1
+VCCP
J50 AY8 P C H _ XDP_GPIO37 AB13 AW22 T34
30 P C I _ CBE0# C/BE0# NV_WR#0_RE# 12,19 P C H _ XDP_GPIO37 SATA3GP / GPIO37 TP2
30 P C I _ CBE1# G42 AY5
H47 C/BE1# NV_WR#1_RE# D O C K _ ID0 V3 BB22
30 P C I _ CBE2# C/BE2# 34 D O C K _ ID0 SLOAD / GPIO38 TP3 T35
G34 AV11 2009/01/20 HP
30 P C I _ CBE3# C/BE3# NV_WE#_CK0 BF5 D O C K _ ID1 P3 AY45 T36
NV_WE#_CK1 34 D O C K _ ID1 SDATAOUT0 / GPIO39 TP4
P C I _ P IRQA# G38
P C I _ P IRQB# PIRQA#
H51 26 C L K _ P C IE_LAN_REQ# H3 AY46 T37
P C I _ P IRQC# B37 PIRQB# H18 U S B 20_N0 PCIECLKRQ6# / GPIO45 TP5
PIRQC# USBP0N U S B 20_N0 32 2008/12/12 HP
P C I _ P IRQD# A44 J18 U S B20_P0 CONN G PIO46 F1 AV43 T38
PIRQD# USBP0P U S B20_P0 32 PCIECLKRQ7# / GPIO46 TP6
A18 U S B 20_N1
USBP1N U S B 20_N1 32
P C I _ REQ0# F51 C18 U S B20_P1 CONN G PIO48 AB6 AV45 T39
REQ0# USBP1P U S B20_P1 32 SDATAOUT1 / GPIO48 TP7
P C I _ REQ1# A46 N20 U S B 20_N2
REQ1# / GPIO50 USBP2N U S B 20_N2 32
30 P C I _ REQ2# P C I _ REQ2# B45 P20 U S B20_P2 CONN P C H _ XDP_GPIO49 AA4 AF13 T40
REQ2# / GPIO52 USBP2P U S B20_P2 32 12 P C H _ XDP_GPIO49 SATA5GP / GPIO49 TP8
P C I _ REQ3# M53 J20 U S B 20_N3
REQ3# / GPIO54 USBP3N U S B 20_N3 32
L20 U S B20_P3 CONN W L A N _ T R A N SMIT_OFF# F8 M18 T41
USBP3P U S B20_P3 32 28 W L A N _ T R A N SMIT_OFF# GPIO57 TP9
P C I _GNT0# F48 F20 U S B 20_N4
GNT0# USBP4N U S B 20_N4 31
M O D E M _DISABLE# K45 G20 U S B20_P4 EXPRESS N18 T42
B M O D E M _DISABLE# GNT1# / GPIO51 USBP4P U S B20_P4 31 TP10 B
P C I _GNT2# F36 A20
30 P C I _GNT2# GNT2# / GPIO53 USBP5N
P C I _GNT3# H53 C20 A4 AJ24 T43
GNT3# / GPIO55 USBP5P M22 A49 VSS_NCTF_1 TP11
NCTF
USBP6N VSS_NCTF_2
RSVD
P C I _ P IRQE# B41 N22 A5 AK41 T44
30 P C I _ P IRQE# PIRQE# / GPIO2 USBP6P VSS_NCTF_3 TP12
29 O D D _ DET# O D D _ DET# K53 B21 A50
P C I _ PIRQG# PIRQF# / GPIO3 USBP7N VSS_NCTF_4
30 P C I _ PIRQG# A36 D21 A52 AK42 T45
A C C E L_INT# PIRQG# / GPIO4 USBP7P U S B 20_N8 VSS_NCTF_5 TP13
32 A C C E L_INT# A48 H22 U S B 20_N8 32 17 P C H _ N C TF6 A53
PIRQH# / GPIO5 USBP8N U S B20_P8 VSS_NCTF_6
J22 U S B20_P8 32 Bluetooth 17 P C H _ N C TF7 B2 M32 T46
USBP8P VSS_NCTF_7 TP14
USB
P C I _ RST# K6 E22 U S B 20_N9 B4 + 3 VM_LAN

28,30 P C I _RST# PCIRST# USBP9N U S B 20_N9 28 VSS_NCTF_8
F22 U S B20_P9 WWAN B52 N32 T47
USBP9P U S B20_P9 28 VSS_NCTF_9 TP15
P C I _ S ERR# E44 A22 U S B 20_N10 B53 2009/04/10 HP DB-3
30,33,35 P C I _ S ERR# SERR# USBP10N U S B20_N10 33 VSS_NCTF_10
P C I _ P ERR# E50 C22 U S B20_P10 Fingerprint BE1 M30 T48 L A N _ DIS# R 286 1 2 10K_0402_5%
30 P C I _ P ERR# PERR# USBP10P U S B20_P10 33 VSS_NCTF_11 TP16
G24 U S B 20_N11 BE53
USBP11N U S B20_N11 34 VSS_NCTF_12
H24 U S B20_P11 DOCK BF1 N30 T49
USBP11P U S B20_P11 34 VSS_NCTF_13 TP17 + 3VS
P C I _ I R D Y# A42 L24 U S B 20_N12 BF53
30 P C I _ I R D Y# IRDY# USBP12N U S B20_N12 19 VSS_NCTF_14
P C I _ P AR H44 M24 U S B20_P12 USB Camera BH1 H12 T50
30 P C I _ PAR PAR USBP12P U S B20_P12 19 VSS_NCTF_15 TP18
P C I _ D EVSEL# F46 A24 U S B 20_N13 BH2 N P C I _ RST# R 255 1 2 10K_0402_5%
30 P C I _ D EVSEL# DEVSEL# USBP13N U S B20_N13 34 VSS_NCTF_16
P C I _ F R AME# C46 C24 U S B20_P13 DOCK BH52 AA23 T51
30 P C I _ F R AME# FRAME# USBP13P U S B20_P13 34 VSS_NCTF_17 TP19
BH53 S A T A _ CLKREQ# R 260 1 2 10K_0402_5%
P C I _ LOCK# VSS_NCTF_18
D49 17 P C H _ N C TF19 BJ1 AB45 T52
PLOCK# U S B R B I AS VSS_NCTF_19 NC_1 P C H _ XDP_GPIO49 R 264 1
B25 1 2 BJ2 2 10K_0402_5%
P C I _STOP# USBRBIAS# R 252 22.6_0402_1% VSS_NCTF_20
30 P C I _STOP# D41 BJ4 AB38 T53
P C I _ T R DY# C48 STOP# D25 BJ49 VSS_NCTF_21 NC_2 W W A N _ D E T# R 266 1 2 100K_0402_5%
30 P C I _ T R DY# TRDY# USBRBIAS W ithin VSS_NCTF_22
BJ5 AB42 T54
500 mils VSS_NCTF_23 NC_3 R 268 1
M7 BJ50 A L S _EN# 2 10K_0402_5%
PME# U S B _ OC#0 VSS_NCTF_24
N16 U S B _ OC#0 12 BJ52 AB41 T55
OC0# / GPIO59 VSS_NCTF_25 NC_4 R 271 1
4,12,20,26,28,31,33 P LT_RST# D5 J16 U S B _ OC#1
U S B _ OC#1 12 17 P C H _ N C TF26 BJ53 R U N S C I _ EC# 2 10K_0402_5%
PLTRST# OC1# / GPIO40 U S B _ OC#2 VSS_NCTF_26
F16 U S B _ OC#2 12 D1 T39 T56
C L K _ P C I _KBC_RN52 OC2# / GPIO41 U S B _ OC#3 VSS_NCTF_27 NC_5 2009/06/09 HP SI-2
L16 U S B _ OC#3 12 D2
C L K _ P C I_FB_R P53 CLKOUT_PCI0 OC3# / GPIO42 U S B _ OC#4 VSS_NCTF_28
E14 U S B _ OC#4 12 D53
C L K _ P CI_TPM_RP46 CLKOUT_PCI1 OC4# / GPIO43 U S B _ OC#5 VSS_NCTF_29 P C H _ XDP_GPIO16 R 276 1
G16 U S B _ OC#5 12 E1 P6 T57 2 10K_0402_5%
C L K _PCI_1394_RP51 CLKOUT_PCI2 OC5# / GPIO9 U S B _ OC#6 VSS_NCTF_30 INIT3_3V#
F12 U S B _ OC#6 12 E53
C L K _ P CI_DB_P P48 CLKOUT_PCI3 OC6# / GPIO10 T15 U S B _ OC#7 VSS_NCTF_31 C10 D O C K _ ID0 R 278 1 2 10K_0402_5%
CLKOUT_PCI4 OC7# / GPIO14 U S B _ OC#7 12 TP24 T58
C I B E X PEAK-M_FCBGA1071 D O C K _ ID1 R 280 1 2 10K_0402_5% C
2009/01/21 Intel WoW G PIO48 R 282 1 2 10K_0402_5%
R 919 1 2 22_0402_5%
36 C L K _ PCI_SIO
S T P _PCI# R 285 1 2 10K_0402_5%
R 920 1 2 22_0402_5% C L K _ P C I _KBC_R Danbury Technology Enable
35 C L K _ P CI_KBC
2009/07/23 Add Cap. SI-2 Compal RF NV_ALE High=Endabled K B _ RST# R 694 1 2 10K_0402_5%
+ 3 VS 2009/11/02 Del Cap. MV Compal RF R 921 1 2 22_0402_5% Low=Disable (@) 2009/01/20 For BIOS
28 C L K _ P C I _DEBUG + 3 V ALW
R 922 1 2 22_0402_5% C L K _ P CI_DB_P
33 C L K _ P CI_DB + V _ N V R A M_VCCQ
2009/03/23 Compal DB-3 R 923 1 2 22_0402_5% C L K _ P C I_FB_R
13 C L K _ P CI_FB
R P 59 R 924 1 2 22_0402_5% C L K _ P CI_TPM_R 2009/05/02 HP SI-1
33 C L K _ PCI_TPM
P C I _STOP# 1 8 2009/01/22 HP N V _ ALE 1 2 U S B _ OC#2 R 1193 1 2 10K_0402_5%
P C I _ T R DY# 2 7 R 925 1 2 22_0402_5% C L K _PCI_1394_R R 270 @ 1K_0402_5%
30 C L K_PCI_1394
P C I _ D EVSEL# 3 6 W L A N _ T R A N SMIT_OFF# R 257 1 2 10K_0402_5%
C 9 51
C 9 52
C 9 53
C 9 54
C 9 55
C 9 56
C 9 49
P C I _ F R AME# 4 5
1 1 1 1 1 1 1 W W A N _ T R A N S M IT_OFF# R 262 1 2 10K_0402_5%
8 .2K_0804_8P4R_5% DMI Termination Voltage
NV_CLE Set to Vss when LOW G PIO24 R 265 1 2 10K_0402_5%
R P6 @ @ @ @ @ @ @ Set to Vcc when HIGH
P C I _ LOCK# 1 8 2 2 2 2 2 2 2 G PIO15 R 267 1 2 1K_0402_5%
+ 3 VS
22P_0402_50V8J
22P_0402_50V8J
22P_0402_50V8J
22P_0402_50V8J
22P_0402_50V8J
22P_0402_50V8J
22P_0402_50V8J
P C I _ REQ0# 2 7 2009/02/06 HP DB-2

P C I _ P IRQB# 3 6 I S O _ PREP# R 269 1 2 10K_0402_5%
O D D _ DET# 4 5 N V _ C LE 1 2
R 283 @ 1K_0402_5% C L K _ P C I E_LAN_REQ# R 272 1 2 10K_0402_5%
8 .2K_0804_8P4R_5%
2009/07/21 HP SI-2 U S B _ OC#0 R 275 1 2 10K_0402_5%
R P8 U S B _ OC#7 R 1227 1 2 0_0402_5% C P P E # 31
P C I _ P IRQA# 1 8 U S B _ OC#6 R 1139 1 2 0_0402_5% 2009/07/22 HP SI-2 C P P E# R 279 1 2 10K_0402_5%
L E D _ L I NK_LAN#_R 26,27
P C I _ P IRQD# 2 7 U S B _ OC#5 R 1097 1 2 0_0402_5% I S O _ PREP# 34
P C I _ REQ3# 3 6 U S B _ OC#4 R 281 1 2 10K_0402_5%
P C I _ P ERR# 4 5 1 2 U S B _ OC#1 R 1004 1 2 0_0402_5%
B T _ O FF 32
R 274 0_0402_5% U S B _ OC#2 R 1005 1 2 0_0402_5% 2009/04/10 HP DB-3
WEBC AM_ O FF
8 .2K_0804_8P4R_5% U S B _ OC#3 R 1006 1 2 0_0402_5%
+ 3VS + 3VS F P R _ O F F 33
P C H _ XDP_GPIO36 R 1007 1 2 0_0402_5%
D
2009/07/02 HP SI-1b N P C I _ RST# 35,36 D
R P7 T H E R M _SCI# R 1028 1 2 8.2K_0402_5% P C I _GNT0# R 254 1 @ 2 1K_0402_5% Boot BIOS Strap P C H _ XDP_GPIO28 R 1099 1 2 10K_0402_5%
P C I _ REQ2# 1 8 PCI_GNT0# MODEM_DISABLE# Boot BIOS Location 2008/12/12 HP
5
P C I _ REQ1# 2 7 M O D E M _DISABLE# R 259 1 @ 2 1K_0402_5% 0 0 LPC* G PIO46 R 498 1 2 10K_0402_5%

A C C E L_INT# 3 6 P C I _GNT3# R 287 1 @ 2 1K_0402_5% 1 P L T_RST# 0 1 Reserved(NAND)
P
IN1 R 1142 1
P C I _ S ERR# 4 5 4 B U F _ P LT_RST# 4 1 0 PCI L E D _ L INK_LAN#_R 2 10K_0402_5%
O 2 1 1 SPI 2009/02/06 HP DB-2
IN2
G
8 .2K_0804_8P4R_5% A16 swap overide Strap/Top-Block

Swap Override jumper U5 @
3
R P9 Low=A16 swap S N 7 4 A H C 1 G08DCKR_SC70-5

P C I _ P IRQE# 1 8 PCI_GNT3# override/Top-Block 2009/02/19 HP DB-2 2008/09/15 2009/12/31 Title
P C I _ PIRQG# Swap Override enabled Issued Date Deciphered Date
2 7
P C I _ P IRQC# 3 6 High=Default
IBEX-M(4/6)-PCI/USB/RSVD
P C I _ I R D Y# 4 5 Size D o c u m ent Number Rev
C u s t om L A -4 9 0 1 P 1 .0
8 .2K_0804_8P4R_5% MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1 2 3 4 5
1 2 3 4 5
+ 3 V S _ V C CDAC + 3VS
+1.05VS L40
+ 1.05VM POWER
+ 1.05VS U4G POWER 1 2
0.01U_0603_16V7K
10U_0805_6.3V6M
0 .1U_0402_16V4Z
U 4J AB24 AE50 M U R A T A_BLM18AG601SN1D_0603
VCCCORE[1] VCCADAC[1]
AB26
VCCCORE[2]
1 U_0603_10V4Z
10U_0805_6.3V6M
C 232
C 233
C 234
T112 AP51 V24 AB28 0.069A AE52 1 1 1
VCCACLK[1] VCCIO[5] VCCCORE[3] VCCADAC[2]
1U_0402_6.3V6K
C 230
C 231
0.052A V26 AD26
1 VCCIO[6] 1 1 VCCCORE[4]1.524A
CRT
T113 AP53 Y24 1 AD28 AF53
VCCACLK[2] VCCIO[7] C 236 VCCCORE[5] VSSA_DAC[1] @ @ @
Y26 AF26
VCCIO[8] VCCCORE[6] 2 2 2
C 235
VCC CORE
2009/01/22 HP DB-2 1U_0402_6.3V6K AF28 AF51
2 2 2 VCCCORE[7] VSSA_DAC[2]
AF23 V28 AF30
VCCLAN[1] VCCSUS3_3[1] 2 VCCCORE[8]
0.344A U28 AF31
VCCSUS3_3[2] VCCCORE[9]
AF24 U26 AH26
VCCLAN[2] VCCSUS3_3[3] VCCCORE[10]
A T59 U24 AH28 A
P28 AH30
1 2 VCCSUS3_3[5] VCCCORE[12]
Y20 P26 AH31 0.030A AH38
C 237 0 .1U_0402_16V4Z DCPSUSBYP VCCSUS3_3[6] VCCCORE[13] VCCALVDS
N28 AJ30
N26 AJ31 AH39
VCCSUS3_3[8] VCCCORE[15] VSSA_LVDS
AD38 M28
VCCME[1] VCCSUS3_3[9] + 3 V ALW
M26
VCCSUS3_3[10] 2009/04/13 Compal DB-3
AD39 L28 AP43
USB
+ 1.05VM VCCME[2] VCCSUS3_3[11] + 1.05VS VCCTX_LVDS[1]
L26 0.059A AP45
VCCSUS3_3[12] VCCTX_LVDS[2]
0 .1U_0402_16V4Z
0 .1U_0402_16V4Z
AD41 J28 AT46
LVDS
VCCME[3] VCCSUS3_3[13] VCCTX_LVDS[3]
C 238
C 239
J26 1 1 AK24 AT45
VCCSUS3_3[14] VCCIO[24] VCCTX_LVDS[4]
1U_0402_6.3V6K
AF43 H28
VCCME[4] VCCSUS3_3[15]
C 240
1 H26
VCCSUS3_3[16]
AF41 0.163AVCCSUS3_3[17] G28 T114 BJ24 0.042A
VCCME[5] 2 2 VCCAPLLEXP
G26 AB34
VCCSUS3_3[18] 2009/01/22 HP DB-2 VCC3_3[2]
AF42 F28
2 VCCME[6] VCCSUS3_3[19] + 3 VS
1.998A VCCSUS3_3[20]
F26 AN20
VCCIO[25] VCC3_3[3]
AB35
V39 E28 AN22
HVCMOS
VCCME[7] VCCSUS3_3[21] VCCIO[26]
Clock and Miscellaneous

E26 AN23 AD35 1 2
VCCSUS3_3[22] VCCIO[27] VCC3_3[4] C 242 0 .1U_0402_16V4Z
V41 C28 AN24
22U_0805_6.3V6M
22U_0805_6.3V6M
1U_0402_6.3V6K
C26 AN26
VCCSUS3_3[24] VCCIO[29]
V42 B27 AN28
C 243
C 244
C 245
1 1 1 A28 BJ26
Y39 VCCSUS3_3[26] A26 BJ28 VCCIO[31]
AT26
Y41 U23 +1.05VS AT28 VCCIO[33]
2009/02/05 HP DB-2 2 2 2 VCCME[11] VCCSUS3_3[28] VCCIO[34]
AU26
Y42 V23 AU28 VCCIO[35] + 1 .8VS
VCCME[12] VCCIO[56] + 1.05VS VCCIO[36]
1U_0402_6.3V6K
1U_0402_6.3V6K
AV26
VCCIO[37]
C 2 47
C 2 48
>1mA F24 I C H _ V 5 R E F_SUS 1 1 AV28 AT24
C 246 V5REF_SUS VCCIO[38] VCCVRM[2]
AW26
+ V C C RTCEXT VCCIO[39]
1 2 V9 AW28
DCPRTC VCCIO[40] +VCCP
DMI
0 .1U_0402_16V4Z BA26 AT16
2 2 VCCIO[41] VCCDMI[1]
BA28 0.061A
I C H _ V 5 R E F _ RUN VCCIO[42]
B 0.035A >1mA V5REF
K49 BB26
VCCIO[43] VCCDMI[2]
AU16
C 249
1 2
1 U_0603_10V4Z
B
AU24 BB28
PCI/GPIO/LPC
+ 1.8VS VCCVRM[3] VCCIO[44]

BC26
+ 3VS VCCIO[45]
PCI E*
0.072A J38 BC28
VCC3_3[8] VCCIO[46]
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0805_6.3V6M
BB51 BD26 + V _ N V R A M_VCCQ
+ V 1 . 0 5S_VCCA_A_DPL VCCADPLLA[1] VCCIO[47]
BB53 L38 BD28
VCCADPLLA[2] VCC3_3[9] VCCIO[48]
C 251
C 252
C 253
1 1 1 1 BE26 AM16 R 508 1 2 0_0603_5% + 1.8VS
C 250 VCCIO[49] VCCPNAND[1]
0.073A VCC3_3[10]
M36 BE28
VCCIO[50] VCCPNAND[2]
AK16
0 .1U_0402_16V4Z
+ V 1 . 0 5S_VCCA_B_DPL BD51 0.357A 0 .1U_0402_16V4Z BG26 AK20
VCCADPLLB[1] VCCIO[51] VCCPNAND[3]
C 254
BD53 N36 BG28 AK19 1 2009/08/30 HP PV
+ 1.05VS VCCADPLLB[2] VCC3_3[11] 2 2 2 2 VCCIO[52] VCCPNAND[4]
BH27
VCCIO[53] 0.156A VCCPNAND[5] AK15
AH23 P36 AK13
VCCIO[21] VCC3_3[12] VCCPNAND[6]
AJ35 AN30 AM12
VCCIO[22] VCCIO[54] VCCPNAND[7] 2
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
NAND / SPI
AH35 U35 AN31 AM13
VCCIO[23] VCC3_3[13] VCCIO[55] VCCPNAND[8]
C 255
C 256
C 257
+ 3VS + 3 VS AM15
1 1 1 VCCPNAND[9]
AF34
VCCIO[2] 3.208A 0 .1U_0402_16V4Z 1 @
AD13 1 2 2 C 8 81 AN35
VCC3_3[14] C 258 0 .1U_0402_16V4Z VCC3_3[1]
AH34
2 2 2 VCCIO[3]
AF32 R 674 1 2 0_0402_5% AT22 + 3VM
VCCIO[4] + 1.8VS VCCVRM[1] 0.035A
AK3 T115
+ V C C SST VCCSATAPLL[1]
1 2 V12 0.032A VCCSATAPLL[2] AK1 T116 T117 BJ18 6mA AM8
DCPSST VCCFDIPLL VCCME3_3[1]
0 .1U_0402_16V4Z
0 .1U_0402_16V4Z 2009/01/22 HP DB-2 AM9
VCCME3_3[2]
FDI
C 261
C 259 2009/01/22 HP DB-2
+ 1.05VS AM23 0.085A AP11 1
VCCIO[1] VCCME3_3[3] AP9
+ V 1 . 1 A _ INT_VCCSUS VCCME3_3[4]
1 2 Y22
0 .1U_0402_16V4Z DCPSUS
AH22
C 260 VCCIO[9] 2
+ 3 VALW P18 AT20
VCCSUS3_3[29] VCCVRM[4] + 1.8VS
1 2 0 . 2 A @3.3V U19
SATA
VCCSUS3_3[30] +1.05VS
PCI/GPIO/LPC
0 .1U_0402_16V4Z AH19
C 264 U20 VCCIO[10]
VCCSUS3_3[31] AD20
VCCIO[11]
1 U_0402_6.3V6K
C U22 C
VCCSUS3_3[32]
C 265
AF22 1
+ 3VS VCCIO[12] + 1.05VS
AD19 L5
0 . 4 A @3.3V VCCIO[13] + V 1 . 0 5S_VCCA_A_DPL
1 2 V15 AF20 1 2 + V 1 . 0 5S_VCCA_A_DPL
0 .1U_0402_16V4Z VCC3_3[5] VCCIO[14] 2 10UH_LB2012T100MR_20%_0805
AF19 1
C 266 VCCIO[15] 2009/01/22 HP DB-2
V16 AH20 1
VCC3_3[6] VCCIO[16] @ C 268 + C 267 @
Y16 AB19 1U_0402_6.3V6K 2 20U_B2_2.5VM_R15
VCC3_3[7] VCCIO[17] AB20
+ V C CP VCCIO[18] 2 2
AB22
VCCIO[19] AD22 + 1.05VM 2009/04/24 HP SI-1
0 . 1 A @1.1V VCCIO[20]
AT18
V_CPU_IO[1]
4.7U_0603_6.3V6K
0 .1U_0402_16V4Z
0 .1U_0402_16V4Z
AA34 + P C H _VCC1_1_20 1 R 295 2 0_0402_5%

CPU
VCCME[13]
C 270
C 271
C 272
Y34 + P C H _VCC1_1_21 1 R 296 2 0_0402_5% L6 + 5 V ALW + 3 V ALW + 5 VS + 3VS

1 1 1 >1mA VCCME[14] R 297 0_0402_5%
AU18 Y35 + P C H _VCC1_1_22 1 2 1 2 + V 1 . 0 5S_VCCA_B_DPL + V 1 . 0 5S_VCCA_B_DPL
V_CPU_IO[2] VCCME[15] + P C H _VCC1_1_23 R 298 0_0402_5% 10UH_LB2012T100MR_20%_0805
AA35 1 2
VCCME[16]
2
2 2 2 1
+VCCSUSHDA R 299 D2 R 300 D3
1
RTC
A12 L30 R 3 01 1 2 0_0402_5% @ C 274 + C 273 @ 100_0402_5% 100_0402_5%

+ R T C V CC VCCRTC 2mA 6mA VCCSUSHDA + 3 VALW
HDA
1U_0402_6.3V6K 2 20U_B2_2.5VM_R15 C H 751H-40PT_SOD323-2 C H 751H-40PT_SOD323-2
1
2 m A @ 3.3V I B E X P EAK-M_FCBGA1071 2 2 2009/02/03 HP DB-2
1
1U_0402_6.3V6K
0 .1U_0402_16V4Z
0 .1U_0402_16V4Z
I C H _ V 5 R E F_SUS I C H _ V 5 R E F _ RUN
C 911
C 276
C 277
1 1 1 C 2 75 20 mils 20 mils
1 U_0402_6.3V6K 2009/02/03 HP DB-2 1 1
2 C 278 C 2 79
1U_0402_6.3V6K 1 U_0402_6.3V6K
2 2 2
2 2
D D

IBEX-M(5/6)-PWR
C u s t om L A -4 9 0 1 P 1 .0
1 2 3 4 5
1 2 3 4 5
U4I U 4H
AY7 H49 AB16
B11 VSS[159] VSS[259] H5 VSS[0]
VSS[160] VSS[260]
B15 J24 AA19 AK30
VSS[161] VSS[261] VSS[1] VSS[80]
B19 K11 AA20 AK31
VSS[162] VSS[262] VSS[2] VSS[81]
B23 K43 AA22 AK32
VSS[163] VSS[263] VSS[3] VSS[82]
B31 K47 AM19 AK34
VSS[164] VSS[264] VSS[4] VSS[83]
B35 K7 AA24 AK35
VSS[165] VSS[265] VSS[5] VSS[84]
B39 L14 AA26 AK38
VSS[166] VSS[266] VSS[6] VSS[85]
B43 L18 AA28 AK43
VSS[167] VSS[267] VSS[7] VSS[86]
B47 L2 AA30 AK46
VSS[168] VSS[268] VSS[8] VSS[87]
B7 L22 AA31 AK49
VSS[169] VSS[269] VSS[9] VSS[88]
A BG12 L32 AA32 AK5 A
VSS[170] VSS[270] VSS[10] VSS[89]
BB12 L36 AB11 AK8
VSS[171] VSS[271] VSS[11] VSS[90]
BB16 L40 AB15 AL2
VSS[172] VSS[272] VSS[12] VSS[91]
BB20 L52 AB23 AL52
VSS[173] VSS[273] VSS[13] VSS[92]
BB24 M12 AB30 AM11
VSS[174] VSS[274] VSS[14] VSS[93]
BB30 M16 AB31 BB44
VSS[175] VSS[275] VSS[15] VSS[94]
BB34 M20 AB32 AD24
VSS[176] VSS[276] VSS[16] VSS[95]
BB38 N38 AB39 AM20
VSS[177] VSS[277] VSS[17] VSS[96]
BB42 M34 AB43 AM22
VSS[178] VSS[278] VSS[18] VSS[97]
BB49 M38 AB47 AM24
BB5 VSS[179] VSS[279] M42 AB5 VSS[19] VSS[98] AM26
VSS[180] VSS[280] VSS[20] VSS[99]
BC10 M46 AB8 AM28
BC14 VSS[181] VSS[281] M49 AC2 VSS[21] VSS[100] BA42
VSS[182] VSS[282] VSS[22] VSS[101]
BC18 M5 AC52 AM30
VSS[183] VSS[283] VSS[23] VSS[102]
BC2 M8 AD11 AM31
VSS[184] VSS[284] VSS[24] VSS[103]
BC22 N24 AD12 AM32
VSS[185] VSS[285] VSS[25] VSS[104]
BC32 P11 AD16 AM34
VSS[186] VSS[286] VSS[26] VSS[105]
BC36 AD15 AD23 AM35
BC40 VSS[187] VSS[287] P22 AD30 VSS[27] VSS[106] AM38
VSS[188] VSS[288] VSS[28] VSS[107]
BC44 P30 AD31 AM39
BC52 VSS[189] VSS[289] P32 AD32 VSS[29] VSS[108] AM42
VSS[190] VSS[290] VSS[30] VSS[109]
BH9 P34 AD34 AU20
BD48 VSS[191] VSS[291] P42 AU22 VSS[31] VSS[110] AM46
BD49 VSS[192] VSS[292] P45 AD42 VSS[32] VSS[111] AV22
VSS[193] VSS[293] VSS[33] VSS[112]
BD5 P47 AD46 AM49
BE12 VSS[194] VSS[294] R2 AD49 VSS[34] VSS[113] AM7
VSS[195] VSS[295] VSS[35] VSS[114]
BE16 R52 AD7 AA50
BE20 VSS[196] VSS[296] T12 AE2 VSS[36] VSS[115] BB10
VSS[197] VSS[297] VSS[37] VSS[116]
BE24 T41 AE4 AN32
VSS[198] VSS[298] VSS[38] VSS[117]
BE30 T46 AF12 AN50
VSS[199] VSS[299] VSS[39] VSS[118] + 3 VS
BE34 T49 Y13 AN52
VSS[200] VSS[300] VSS[40] VSS[119]
BE38 T5 AH49 AP12
VSS[201] VSS[301] VSS[41] VSS[120]
BE42 T8 AU4 AP42
VSS[202] VSS[302] VSS[42] VSS[121]
BE46 U30 AF35 AP46
VSS[203] VSS[303] VSS[43] VSS[122]
1
BE48 U31 AP13 AP49
B
BE50 VSS[204] VSS[304] U32 AN34 VSS[44] VSS[123] AP5 R 302
B
VSS[205] VSS[305] VSS[45] VSS[124] C R A C K _ BGA 8,35
BE6 U34 AF45 AP8
6
BE8 VSS[206] VSS[306] P38 AF46 VSS[46] VSS[125] AR2 100K_0402_5%
VSS[207] VSS[307] VSS[47] VSS[126]
BF3 V11 AF49 AR52
2
VSS[208] VSS[308] VSS[48] VSS[127] Q9A
BF49 P16 AF5 AT11
VSS[209] VSS[309] VSS[49] VSS[128] 2 N 7 002DWH_SOT363-6
BF51 V19 AF8 BA12 15 P C H _ N C T F6 2
VSS[210] VSS[310] VSS[50] VSS[129]
BG18 V20 AG2 AH48
VSS[211] VSS[311] VSS[51] VSS[130]
BG24 V22 AG52 AT32
1
BG4 VSS[212] VSS[312] V30 AH11 VSS[52] VSS[131] AT36
VSS[213] VSS[313] VSS[53] VSS[132] + 3 VS
BG50 V31 AH15 AT41
BH11 VSS[214] VSS[314] V32 AH16 VSS[54] VSS[133] AT47
VSS[215] VSS[315] VSS[55] VSS[134]
BH15 V34 AH24 AT7
BH19 VSS[216] VSS[316] V35 AH32 VSS[56] VSS[135] AV12
1
VSS[217] VSS[317] VSS[57] VSS[136] C R A C K _ BGA
BH23 V38 AV18 AV16
VSS[218] VSS[318] VSS[58] VSS[137] R 303
BH31 V43 AH43 AV20
BH35 VSS[219] VSS[319] V45 AH47 VSS[59] VSS[138] AV24
VSS[220] VSS[320] VSS[60] VSS[139]
3
BH39 V46 AH7 AV30 100K_0402_5%
VSS[221] VSS[321] VSS[61] VSS[140]
BH43 V47 AJ19 AV34
2
VSS[222] VSS[322] VSS[62] VSS[141] Q9B
BH47 V49 AJ2 AV38
VSS[223] VSS[323] VSS[63] VSS[142] 2 N 7 002DWH_SOT363-6
BH7 V5 AJ20 AV42 15 P C H _ N C T F7 5
C12 VSS[224] VSS[324] V7 AJ22 VSS[64] VSS[143] AV46
VSS[225] VSS[325] VSS[65] VSS[144]
C50 V8 AJ23 AV49
4
D51 VSS[226] VSS[326] W2 AJ26 VSS[66] VSS[145] AV5
E12 VSS[227] VSS[327] W52 AJ28 VSS[67] VSS[146] AV8 + 3 VS
VSS[228] VSS[328] VSS[68] VSS[147]
E16 Y11 AJ32 AW14
VSS[229] VSS[329] VSS[69] VSS[148]
E20 Y12 AJ34 AW18
VSS[230] VSS[330] VSS[70] VSS[149]
E24 Y15 AT5 AW2
1
VSS[231] VSS[331] VSS[71] VSS[150] C R A C K _ BGA
E30 Y19 AJ4 BF9
VSS[232] VSS[332] VSS[72] VSS[151] R 304
E34 Y23 AK12 AW32
VSS[233] VSS[333] VSS[73] VSS[152]
E38 Y28 AM41 AW36
6
VSS[234] VSS[334] VSS[74] VSS[153] 100K_0402_5%
E42 Y30 AN19 AW40
VSS[235] VSS[335] VSS[75] VSS[154]
E46 Y31 AK26 AW52
2
E48 VSS[236] VSS[336] Y32 AK22 VSS[76] VSS[155] AY11 Q 10A
E6 VSS[237] VSS[337] Y38 AK23 VSS[77] VSS[156] AY43 2 N 7 002DWH_SOT363-6
15 P C H _ N C T F19 2
VSS[238] VSS[338] VSS[78] VSS[157]
C E8 Y43 AK28 AY47 C
F49 VSS[239] VSS[339] Y46 VSS[79] VSS[158]
1
VSS[240] VSS[340] I B E X PEAK-M_FCBGA1071 + 3 VS
F5 P49
G10 VSS[241] VSS[341] Y5
G14 VSS[242] VSS[342] Y6
VSS[243] VSS[343]
G18 Y8
1
VSS[244] VSS[344] C R A C K _ BGA
G2 P24
VSS[245] VSS[345] R 305
G22 T43
G32 VSS[246] VSS[346] AD51
3
G36 VSS[247] VSS[347] AT8 100K_0402_5%
VSS[248] VSS[348]
G40 AD47
2
G44 VSS[249] VSS[349] Y47 Q 10B
VSS[250] VSS[350] 2 N 7 002DWH_SOT363-6
G52 AT12 15 P C H _ N C T F26 5
AF39 VSS[251] VSS[351] AM6
VSS[252] VSS[352]
H16 AT13
4
VSS[253] VSS[353]
H20 AM5
VSS[254] VSS[354]
H30 AK45
VSS[255] VSS[355]
H34 AK39
H38 VSS[256] VSS[356] AV14
VSS[257] VSS[366]
H42
VSS[258]
BGA Ball Cracking Prevention and Detection
D D

IBEX-M(6/6)-GND
C u s t om L A - 4 9 0 1 P 1 .0
1 2 3 4 5
1 2 3 4 5
CRT Connector + 5VS + R C R T _ VCC

2
+CRTVDD V G A _ BLUE_R
V G A _ G RN_R
L7 L8 F1 W=40mils V G A _ R ED_R
CS0805-68NJ-S_0805 CS0805-68NJ-S_0805 1 2 1 D _ HSYNC
20 DAC_RED DAC_RED 1 2 D A C _ R E D _R 1 2 D4 D _VSYNC 2009/02/18 Compal DB-2 EMI
R E D _ R 34
L9 L 10 1 . 1 A_8V_SMD1812P110TF(HF) 3 C H 491DPT_SOT23-3
NC
CS0805-68NJ-S_0805 CS0805-68NJ-S_0805 1
1
D AN217GT146_SC59-3
D AN217GT146_SC59-3
D AN217GT146_SC59-3
D AN217GT146_SC59-3
D AN217GT146_SC59-3
20 DAC_GRN DAC_GRN 1 2 D A C _ G R N _R 1 2 C 280 D5 @ D6 @ D7 @ D8 @ D9 @
G R E E N _ R 34
L 11 L 12
CS0805-68NJ-S_0805 CS0805-68NJ-S_0805 GPU >> SW 0 .1U_0402_16V4Z
D A C _ B LU 1 2 D A C _ B L U_R 1 2 2
20 D A C _ B LU B L U E _R 34 2009/09/10 HP PV JP4 C O NN@
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
27P_0402_50V8J
27P_0402_50V8J
27P_0402_50V8J
G N D _ C RT 6
3
C 284
C 285
C 286
C 287
C 288
C 289
11
GPU 1 1 1 1 1 1
L48 1 2 F C M1608CF-121T03_2P V G A _ R ED_R 1 G 16 +CRTVDD
34 V G A _ RED
A 7 G 17 A
@ @ @ D _ D D C D A TA 12
2 2 2 2 2 2 L49 1 2 F C M1608CF-121T03_2P V G A _ G RN_R 2
L 34 V G A _ GRN
8
Place cloce to GPU 13
L50 1 2 F C M1608CF-121T03_2P V G A _ BLUE_R 3
34 V G A _BLU
9
R 312
R 313
R 314
14
4
SW >> Port
1
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
2009/02/18 Compal DB-2 EMI 10
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
C 281
C 282
C 283
1 1 1 R 1244 D_DDCCLK 15
C 942
C 943
C 944
1 1 1 0_0402_5% 5
S U Y I N _ 0 7 0912FR015S229ZR
2
2 2 2
75_0402_1%
75_0402_1%
75_0402_1%
+ 5VS + 5VS
2 2 2
C 290 C 291
0 .1U_0402_16V4Z 0 .1U_0402_16V4Z
1 2 1 2
G N D _ C RT
2008/12/06 Nvidia
5
U6 + C R T V DD + 3VS
D _ H S Y N C 34
7 4 AHCT1G125GW_SOT353-5
OE#
P
2 4 H S Y NC R 316 1 2 0_0402_5% D _ HSYNC

20 C R T _ H S Y N C A Y
G
R 318
R 319
R 320
R 321
U7
D _ V S Y N C 34
1
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
OE#
P
3
2 4 V S YNC R 317 1 2 0_0402_5% D _VSYNC 2009/02/24 Nvidia DB-2

20 C R T _ V S Y N C A Y
G
7 4 AHCT1G125GW_SOT353-5
1 1
3
2
2
C 292 C 293 Q4A
B B
5P_0402_50V8C 5P_0402_50V8C 6 1
2 2 34 D _ D D C D A TA C R T _ D D C _ DATA 20
L Place cloce to VGA 2 N 7 0 02KDWH_SOT363-6
5
Q 4B3 4
34 D _ D D C C L K C R T _ D D C _ CLK 20
layout note: D_HSYNC 2 N 7 0 02KDWH_SOT363-6

& D_VSYNC should be
L Place cloce to VGA
routed to docking
connector then to VGA
connector
R 1114 1 2 0_0402_5%
Display Port Connector + 3 V S_DP
JDP1 C ONN@
R 1112 1 2 0_0402_5% M B _ DPA_AUXL# 1 L44 @ 2 M B _ DPA_AUX#_L + 3 V S_DP 20
1 2 19 DP_PWR
DPA_HPD RTN
18
M B _ DPA_AUXL M B _ DPA_AUX_L M B _ DPA_AUX#_L HP_DET
4 3 17
L42 @ M B _DPA_TXN2_L 4 3
WCM-2012-900T_4P AUX_CH-
22 M B _DPA_TXN2 1 2 16
1 2 M B _ DPA_AUX_L GND
15
2009/02/12 Nvidia DB-2 AUX_CH+
14
M B_DPA_TXP2_L C A _ D ET GND
22 M B _DPA_TXP2 4 3 1 2 22 C A _ D ET 13 24
4 3
WCM-2012-900T_4P R 1117 0_0402_5% M B _DPA_TXN3_L C 351 CA_DET GND
1 2 0.1U_0402_10V7K D P A _TXN3_C 12 23
LANE3- GND
11 22
M B_DPA_TXP3_L C 352 1 2 0.1U_0402_10V7K D P A_TXP3_C 10 LANE3_shield GND 21
M B _DPA_TXN2_L C 353 LANE3+ GND
1 2 1 2 0.1U_0402_10V7K D P A _TXN2_C 9
R 1115 0_0402_5% LANE2-
C 8 C
+ 5 VS + 5VS M B_DPA_TXP2_L C 354 1 2 0.1U_0402_10V7K D P A_TXP2_C 7 LANE2_shield
C 355 LANE2+
2008/12/17 EMI DB M B _DPA_TXN1_L 1 2 0.1U_0402_10V7K D P A _TXN1_C 6
0.1U_0402_10V7K LANE1-
1 2 C 350 5
R 1118 1 LANE1_shield
2 0_0402_5% M B_DPA_TXP1_L C 356 1 2 0.1U_0402_10V7K D P A_TXP1_C 4
C 850 LANE1+
M B _DPA_TXN0_L 1 2 0.1U_0402_10V7K D P A _TXN0_C 3
2008/12/12 Nvidia request to P22 LANE0-
2
LANE0_shield
1
Q 65A Q 65B 2008/12/06 Nvidia M B_DPA_TXP0_L C 851 1 2 0.1U_0402_10V7K D P A_TXP0_C 1
1 L45 @ 2 M B_DPA_TXP1_L M B _ DPA_AUXL R 984 LANE0+
22 M B _DPA_TXP1 22 M B _ DPA_AUX 6 1 4 3
1 2 10K_0402_5% MOLEX_105020-0001
+ 3 VS
2
4 3 M B _DPA_TXN1_L 2 N 7 002KDWH_SOT363-6 2 N 7 002KDWH_SOT363-6
2
2
22 M B _DPA_TXN1 4 3
N A N O S M D C 0 5 0 F 0.5A 13.2V POLY-FUSE S DM10U45-7_SOD523-2

WCM-2012-900T_4P R 985
DDC1_EN 10K_0402_5% 2008/12/19 Nvidia
1
1 2 C A _ D ET R 1065 1 2 1M_0402_5%
D 65
R 1120 0_0402_5% 1 R 956
0_1206_5% 2009/02/12 Nvidia DB-2
C 957 2 @
2
2 N 7 002KDWH_SOT363-6 2 N 7 0 02KDWH_SOT363-6 0 .1U_0402_16V4Z 2 N 7 002KDWH_SOT363-6
2
2 Q 67A
1
3
R 1113 1 2 0_0402_5% 6 1 4 3 M B _ DPA_AUXL# Q 67B + D PA_3V
22 M B _ DPA_AUX# 2009/04/09 HP DB-3 2 N 7 002KDWH_SOT363-6
Q 66A Q 66B + 3VS
5 C A _ D ET
1 L43 @ 2 M B_DPA_TXP3_L 0.1U_0402_10V7K 1 2 C 349 M B _ DPA_AUX#_L R 973 1 2 100K_0402_5%
22 M B _DPA_TXP3 1 2 2009/02/26 Nvidia DB-2 + 3 VS_DP
4
1
R 974 1 @ 2 100K_0402_5%
4 3 M B _DPA_TXN3_L
22 M B _DPA_TXN3 4 3
WCM-2012-900T_4P
C 8 41
0 .1U_0402_16V4Z
C 8 42
1 0U_0805_10V4Z
F2
1 1
2
1 2
R 1116 0_0402_5% + 3VS
R 1088
D 2 2 D
1 2 DPA_HPD M B _ DPA_AUX_L R 960 1 @ 2 100K_0402_5%
22 M B _ D P _HPD
0_0402_5%
R 961 1 2 100K_0402_5%
R 1119 1 2 0_0402_5%
2009/06/30 SI-2
1
1 L46 @ 2 M B _DPA_TXN0_L R 1091

22 M B _DPA_TXN0 1 2 100K_0402_5%
2
4 3 M B_DPA_TXP0_L 2008/09/15 2009/12/31 Title

22 M B _DPA_TXP0 4 3
WCM-2012-900T_4P
Issued Date Deciphered Date
CRT & DP Connector
1 2 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS L A -4 9 0 1 P 1 .0
R 1121 0_0402_5% MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1 2 3 4 5
1 2 3 4 5
LCD/PANEL BD. CONN.

+ 3VS +LCDVDD
47P_0402_50V8J
680P_0402_50V7K
2008/12/06 Nvidia DB-1
C 297
C 298
1 1
1
C 296
680P_0402_50V7K
@
Key_Board_Light power Control 2009/03/08 DB-3
2
2 2 B+ R 1252 1 2 0_0805_5% I N V P W R _B+
SI2303CDS-T1-E3_SOT23-3 + 5 VKBL + 5 VS + 5 VS D I S P _ O FF# 1 2 E N A BLT E N A BLT 20

A @ R 1171 2K_0402_5% A
1
S
D
3 1 2008/12/06 Nvidia DB-1
10K_0402_5%
Q 71 2009/03/08 HP SI-1 R 3 33
1
0.22U_0603_25V7K
47P_0402_50V8J
1U_0805_25V6K
Q96 SI2301CDS-T1-GE3_SOT23-3 10K_0402_1%
C 1000
C 1001
C 1002
R 1134
2009/03/08 DB-3
G
1 1 1
2
1 3 L I D _ SW#
S
D
2
@ R 1248
D 14
220K_0402_5% @ @
2
2 2 2 L I D _ SW#
G
2 1
G
L I D _SW# 31,35
2
1 3 C H 751H-40PT_SOD323-2
S
Q72
1
2009/01/22 HP DB-2 2N7002H_SOT23-3
@ R 1249 2009/09/16 HP SI-2b
100K_0402_5%
2
2009/06/30 HP SI-1b
2009/08/30 HP PV
2009/01/20 Nvidia DB-2 DP add Cap. 2009/01/20 Nvidia DB-2 DP add Cap.
J E D P1 C O NN@
B B
21 D P D_TXP0 0.1U_0402_10V7K 1 2 C 916 D P D _TXP0_C 1 2
0.1U_0402_10V7K 1 1 2
21 D P D _TXN0 2 C 917 D P D _ TXN0_C 3 4
5 3 4 6 R 339 1 2 0_0402_5%
5 6 D P D _ A UX_C C 9 14 1
7 8 2 0.1U_0402_10V7K D P D _ AUX 21
7 8 D P D _ AUX#_C C 9 15 1
9 10 2 0.1U_0402_10V7K D P D _AUX# 21
9 10 L36 @
11 12 1 2 U S B20_P12 15
11 12 U S B 20_P12_R 1 2
20 I N V _ P WM 13 14
680P_0402_50V7K1 13 14
2 C 308 D I S P _ O FF# 15 16 U S B 2 0_N12_R
17 15 16 18 2009/04/24 SI-1 4 3
15 A L S _EN# 17 18 4 3 U S B 20_N12 15
+ 5VKBL 19 20 WCM-2012-900T_4P
19 20 D P D _ D P _ H PD 20
2008/12/12 for keyboard light 2009/06/02 SI-2 W E B C A M _ON 21 0.6A 22 + 5 VS
21 22 R 340 1
+ 3VS 23 24 2009/06/02 SI-2 2 0_0402_5%
25 23 24 26
0.6A
25 26 I N V P W R _B+
27 28
R 911 1 27 28
+ L C D V DD 2 0_0805_5% + L C D V D D_R 29 30 2009/06/30 Compal SI-2 U S B 2 0_N12_R U S B 20_P12_R
31 29 30 32
G1 G2
3
ACES_50238-03071-002 2009/04/24 SI-1
D 13 @
+ 3VS P J D LC05H_SOT23-3
2009/02/02 DB-2 change EDP CONN. D P D _ AUX#_C R 1050 1 2 100K_0402_5%

2009/09/15 SI-2b change EDP CONN.
D P D _ A UX_C R 1049 1 2 100K_0402_5%
1
+ 5 VS
C R 341 1 2 0_0402_5% W E B C A M _ON C
12,15 P C H _ XDP_GPIO37
100K_0402_5%
1
R 334
47P_0402_50V8J
0.01U_0402_16V7K
0 .1U_0402_16V4Z
4 .7U_0805_10V4Z
LCD POWER CIRCUIT

C 302
C 303
C 304
C 305
1 1 1 1
+LCDVDD +LCDVDD + 3VS
2
@ Q 15
2 2 2 2 SI2301CDS-T1-GE3_SOT23-3
1
2009/04/24 SI-1
R 3 42 1 3
S
D
100_0402_1%
G
2
2
R 343 1 2 1M_0402_5%
1
D
Q 11 2 R 3 44 1 2 47K_0402_5% C 309 1 2 0 .1U_0402_16V4Z
G
S S M3K7002F_SC59-3 S 1 1 1
3
C 310 C 311 C 312 @
0 .1U_0402_16V4Z 4 .7U_0805_10V4Z 4 .7U_0805_10V4Z
1
2 2 2
OUT
20 E NAVDD 2
IN
GND
1
Q 16
R 345 D T C 1 24EKAGZT146_SC59-3
3
10K_0402_1%
D D
2
2008/12/06 Nvidia

LCD & eDP CONN.
1 2 3 4 5
1 2 3 4 5
+ 3 VS 2008/12/12 Nvidia
2009/09/16 Compal SI-2R
2008/11/21 Swap PCIE for Layout U8A GP U _VID0 R 1067 1 2 10K_0402_5% N V _ GPIO11 R 1052 1 2 10K_0402_5%
P a rt 1 of 5
5 P C IE_CTX_GRX_P15 AE12 N1 G P U _ VID1 R 1068 1 2 10K_0402_5% N V _ GPIO14 R 1053 1 2 10K_0402_5%
PEX_RX0 GPIO0
5 P C I E_CTX_GRX_N15 AF12 G1 H P D - C 22
PEX_RX0_N GPIO1 I N V _ P WM G P U _ VID2 R 1087 1
5 P C IE_CTX_GRX_P14 AG12 C1 I N V _ P WM 19 2 10K_0402_5% I N V _ P WM R 1102 1 2 10K_0402_5%
PEX_RX1 GPIO2 E NA VDD
5 P C I E_CTX_GRX_N14 AG13 M2 E N A V D D 19
PEX_RX1_N GPIO3 R 1150 1 @
5 P C IE_CTX_GRX_P13 AF13 M3 E N A BLT
E N A BLT 19
2008/12/19 Nvidia J T A G_TRST 2 10K_0402_5%
PEX_RX2 GPIO4 G P U _ VID0
5 P C I E_CTX_GRX_N13 AE13 K3 G P U _ VID0 48
PEX_RX2_N GPIO5 G P U _ VID1 2009/02/12 Nvidia DB-2
5 P C IE_CTX_GRX_P12 AE15 K2 G P U _ VID1 48
PEX_RX3 GPIO6 G P U _ VID2
5 P C I E_CTX_GRX_N12 AF15 J2 G P U _ VID2 48
PEX_RX3_N GPIO7 T H E RM# 0_0402_5%1
5 P C IE_CTX_GRX_P11 AG15 C2 2 R 346 T H E R M#_VGA
GPIO
PEX_RX4 GPIO8 THM_ALERT 0_0402_5%1 @
5 P C I E_CTX_GRX_N11 AG16 M1 2 R 347 T H E R M _ALERT
PEX_RX4_N GPIO9
A 5 P C IE_CTX_GRX_P10 AF16 D2 A
PEX_RX5 GPIO10 N V _ GPIO11
5 P C I E_CTX_GRX_N10 AE16 D1
PEX_RX5_N GPIO11 AC_DET_R 0_0402_5%1 @ 2 R 348
5 P C IE_CTX_GRX_P9 AE18 J3 A C _ P R E SENT 14,35
PEX_RX6 GPIO12
5 P C I E_CTX_GRX_N9 AF18 J1
PEX_RX6_N GPIO13 N V _ GPIO14
5 P C IE_CTX_GRX_P8 AG18 K1
PEX_RX7 GPIO14
AG19 F3
5
5
P C I E_CTX_GRX_N8
P C IE_CTX_GRX_P7 AF19
PEX_RX7_N GPIO15
G3
D P E _ H PD 34 Docking
PEX_RX8 GPIO16
5 P C I E_CTX_GRX_N7 AE19 G2
PEX_RX8_N GPIO17
5 P C IE_CTX_GRX_P6 AE21 F1
PEX_RX9 GPIO18
5 P C I E_CTX_GRX_N6 AF21 F2 D P D _ D P _ H PD 19 e-DP
AG21 PEX_RX9_N GPIO19
5 P C IE_CTX_GRX_P5 PEX_RX10
5 P C I E_CTX_GRX_N5 AG22 AD2 C R T _ H S Y N C 18
AF22 PEX_RX10_N DACA_HSYNC AD1 Close to GPU
5 P C IE_CTX_GRX_P4 PEX_RX11 DACA_VSYNC C R T _ V S Y N C 18
AE22
DACA
5 P C I E_CTX_GRX_N4 PEX_RX11_N
5 P C IE_CTX_GRX_P3 AE24 AE2 DAC_RED DAC_RED R 349 1 @ 2 150_0402_1%
PEX_RX12 DACA_RED D A C _ R E D 18
5 P C I E_CTX_GRX_N3 AF24 AD3 D A C _ B LU
PEX_RX12_N DACA_BLUE D A C _ B LU 18
5 P C IE_CTX_GRX_P2 AG24 AE3 DAC_GRN DAC_GRN R 350 1 @ 2 150_0402_1%
PEX_RX13 DACA_GREEN D A C _ G R N 18
5 P C I E_CTX_GRX_N2 AF25
AG25 PEX_RX13_N AF1 D A CA_VREF C 313 1 2 0 .1U_0402_16V4Z 2009/01/20 DB-1 CRT issue for Compal D A C _ B LU R 351 1 @ 2 150_0402_1%
5 P C IE_CTX_GRX_P1 PEX_RX14 DACA_VREF
PCI EXPRESS
5 P C I E_CTX_GRX_N1 AG26 AE1 D A C A _ R S EF R 352 1 2 124_0402_1%
AF27 PEX_RX14_N DACA_RSET
5 P C IE_CTX_GRX_P0 PEX_RX15
5 P C I E_CTX_GRX_N0 AE27 U6
PEX_RX15_N DACB_HSYNC U4 + 3 VS
C 344 0.1U_0402_10V7K PCIE_CRX_GTX_G_P15 DACB_VSYNC
1 2 AD10
DACB
5 P C IE_CRX_GTX_P15 PEX_TX0
C 345 1 2 0.1U_0402_10V7K PCIE_CRX_GTX_G_N15 AD11 T5 T H E RM# R 1054 1 @ 2 2.2K_0402_5%
5 P C I E_CRX_GTX_N15 PEX_TX0_N DACB_RED
C 342 1 2 0.1U_0402_10V7K P C IE_CRX_GTX_G_P14 AD12 R4 T H M _ALERT R 1055 1 2 2.2K_0402_5%
5 P C IE_CRX_GTX_P14 PEX_TX1 DACB_BLUE
C 343 1 2 0.1U_0402_10V7K P C IE_CRX_GTX_G_N14 AC12 T4 2009/02/18 HP DB-2
5 P C I E_CRX_GTX_N14 PEX_TX1_N DACB_GREEN
C 340 1 2 0.1U_0402_10V7K P C IE_CRX_GTX_G_P13 AB11 I 2 C S _SCL R 355 1 2 10K_0402_5%
C 341 1 2 0.1U_0402_10V7K P C IE_CRX_GTX_G_N13 AB12 R6 I 2 C S _SDA R 356 1 2 10K_0402_5%
5 P C I E_CRX_GTX_N13 PEX_TX2_N DACB_VREF
C 338 1 2 0.1U_0402_10V7K P C IE_CRX_GTX_G_P12 AD13 V6
5 P C IE_CRX_GTX_P12 PEX_TX3 DACB_RSET
C 339 1 2 0.1U_0402_10V7K P C IE_CRX_GTX_G_N12 AD14 E D I D _ CLK R 788 1 2 2.2K_0402_5%
5 P C I E_CRX_GTX_N12 PEX_TX3_N
C 336 1 2 0.1U_0402_10V7K P C IE_CRX_GTX_G_P11 AD15 E D I D _ DATA R 789 1 2 2.2K_0402_5%
C 337 1 2 0.1U_0402_10V7K P C IE_CRX_GTX_G_N11 AC15
C 334 1 2 0.1U_0402_10V7K P C IE_CRX_GTX_G_P10 AB14 AF3 J T A G_TCK T60 H D C P _ S CL R 361 1 2 2.2K_0402_5%
5 P C IE_CRX_GTX_P10 PEX_TX5 JTAG_TCK
C 335 1 2 0.1U_0402_10V7K P C IE_CRX_GTX_G_N10 AB15 AG4 J T A G_TDI T61 HDCP_SDA R 364 1 2 2.2K_0402_5%
B 5 P C I E_CRX_GTX_N10 PEX_TX5_N JTAG_TDI B
C 332 1 2 0.1U_0402_10V7K P C IE_CRX_GTX_G_P9 AC16 AE4 J T A G_TDO
TEST
5 P C IE_CRX_GTX_P9 PEX_TX6 JTAG_TDO T62
C 333 1 2 0.1U_0402_10V7K P C I E_CRX_GTX_G_N9 AD16 AF4 J T AG_TMS T63 I 2 C B _SCL R 1069 1 2 2.2K_0402_5%
5 P C I E_CRX_GTX_N9 PEX_TX6_N JTAG_TMS
C 330 1 2 0.1U_0402_10V7K PCIE_CRX_GTX_G_P8 AD17 AG3 J T A G_TRST T64 I 2 C B _SDA R 1070 1 2 2.2K_0402_5%
5 P C IE_CRX_GTX_P8 PEX_TX7 JTAG_TRST_N
C 331 1 2 0.1U_0402_10V7K PCIE_CRX_GTX_G_N8 AD18
C 328 1 2 0.1U_0402_10V7K PCIE_CRX_GTX_G_P7 AC18 AD25 R 3 68 1 2 10K_0402_5%
5 P C IE_CRX_GTX_P7 PEX_TX8 TESTMODE
C 329 1 2 0.1U_0402_10V7K PCIE_CRX_GTX_G_N7 AB18
C 326 1 2 0.1U_0402_10V7K PCIE_CRX_GTX_G_P6 AB19
C 324 1 2 0.1U_0402_10V7K PCIE_CRX_GTX_G_P5 AD19 R1
5 P C IE_CRX_GTX_P5 PEX_TX10 I2CA_SCL C R T _ D D C _CLK 18
C 325 1 2 0.1U_0402_10V7K PCIE_CRX_GTX_G_N5 AD20 T3
5 P C I E_CRX_GTX_N5
C 322 1 2 0.1U_0402_10V7K PCIE_CRX_GTX_G_P4 AD21 PEX_TX10_N I2CA_SDA C R T _ D D C _ DATA 18 CRT
C 323 1 2 0.1U_0402_10V7K PCIE_CRX_GTX_G_N4 AC21 R2 I 2 C B _SCL
5 P C I E_CRX_GTX_N4 PEX_TX11_N I2CB_SCL
C 320 1 2 0.1U_0402_10V7K PCIE_CRX_GTX_G_P3 AB21 R3 I 2 C B _SDA GPIO I/O ACTIVE USAGE
5 P C IE_CRX_GTX_P3 PEX_TX12 I2CB_SDA
C 318 1 2 0.1U_0402_10V7K PCIE_CRX_GTX_G_P2 AC22 A2 E DID_CLK
5 P C IE_CRX_GTX_P2
I2C
C 319 0.1U_0402_10V7K PCIE_CRX_GTX_G_N2 PEX_TX13 I2CC_SCL E DID_DATA
5 P C I E_CRX_GTX_N2 1 2 AD22 B1 GPIO0 IN N/A HPD-C (used for IFPC)
C 316 0.1U_0402_10V7K PCIE_CRX_GTX_G_P1 PEX_TX13_N I2CC_SDA
5 P C IE_CRX_GTX_P1 1 2 AD23
C 317 0.1U_0402_10V7K PCIE_CRX_GTX_G_N1 PEX_TX14 H DCP_SCL
5 P C I E_CRX_GTX_N1 1 2 AD24 A3 H D C P _ S CL 21
C 314 1 2 0.1U_0402_10V7K PCIE_CRX_GTX_G_P0 PEX_TX14_N I2CH_SCL HD CP_SDA
AE25 A4 GPIO1 IN N/A 2nd DVI Hot-plug
5 P C IE_CRX_GTX_P0
C 315 1 2 0.1U_0402_10V7K PCIE_CRX_GTX_G_N0 AE26
PEX_TX15 I2CH_SDA H D C P _ S D A 21 HDCP
5 P C I E_CRX_GTX_N0 PEX_TX15_N T1 I 2 C S _SCL 0_0402_5%1 2 R 1085 SML1_CLK
13 C L K _ PEG_VGA AB10
I2CS_SCL
T2 I 2 C S _SDA 0_0402_5%1 2 R 1086 SML1_DATA
S M L1_CLK 13 EXT/THERMAL GPIO2 OUT H P anel Back-Light PWM
PEX_REFCLK I2CS_SDA S M L1_DATA 13
AC10 2008/12/05 Nvidia for thermal debug
13 C L K _ PEG_VGA# PEX_REFCLK_N
2 7 M_SSC 11
R 3 65 1 @ 2 200_0402_1% AF10 GPIO3 OUT H P anel Pow er Enable
PEX_TSTCLK_OUT 2 7 M_SSC R 3 69 1 @
AE10 D11 2 10K_0402_5%
PEX_TSTCLK_OUT_N XTAL_SSIN
R 3 66 1 2 2.49K_0402_1% AG10 E9 R 3 70 1 @ 2 10K_0402_5% GPIO4 OUT H Panel Back-Light Enable
PEX_TERMP XTAL_OUTBUFF
R 3 67 1 2 0_0402_5% P EX_RST# AD9 E10 X TALOUT
CLK
4,12,15,26,28,31,33 P LT_RST# PEX_RST_N XTAL_OUT 2008/12/05 Nvidia

R 1 24 1
GPIO5 OUT N/A NVVDD VID0
+ 3VS 2 10K_0402_5% AE9 D10 X TALIN
PEX_CLKREQ_N XTAL_IN
C N10M-GLM-S-A3_BGA533
GPIO6 OUT N/A NVVDD VID1 C
R 3 73 1
GPIO7 OUT N/A NVVDD VID2
11 2 7M_CLK 2 0_0402_5% X TALIN
+ 3 VS + 3VS
GPIO8 IN L OVERT
Y8 @
4 3 X TALIN GPIO9 OUT L T hermal Alert
GND OUT
1
X TALOUT 1 2
IN GND R 1157 R 1158
2 7MHZ_16PF_X7T027000BG1H-V 10K_0402_5% 10K_0402_5%
H _ T H E R MTRIP# 4,15 GPIO10 OUT N/A MEM_VREF
1 1
6
GPIO11 OUT L SLI SYNCO
2
C 824 @ C 825 @
20P_0402_50V8 20P_0402_50V8 Q 78A
2 2 2 N 7 002DWH_SOT363-6
2 GPIO12 IN N/A AC Detect
1
3
2009/02/18 HP DB-2
GPIO13 OUT L MEM_VID
T H E R M#_VGA 5 GPIO14 OUT H PS Control

Q 78B
2 N 7 002DWH_SOT363-6
4
GPIO15 IN N/A HPD-E (used for IFPE)
GPIO16 OUT N/A FAN PWM Control
GPIO17 N/A
D D
GPIO18 N/A
GPIO19 IN N/A HPD-D (used for IFPD)

PEG Interface
Custom 1 .0
LA-4901P
1 2 3 4 5
1 2 3 4 5
LVDS Interface
U 8C
P a rt 3 of 5
AC4 C15
IFPA_TXC NC
AD4 D15
NC
2009/01/20 Nvidia DB-2 IFPA_TXC_N NC
V5 J5
IFPA_TXD0 NC
V4
IFPA_TXD0_N
AA5
IFPA_TXD1
AA4
IFPA_TXD1_N
W4
IFPA_TXD2
Y4 T6
IFPA_TXD2_N RFU_1
A AB4 W6 A
RFU
IFPA_TXD3 RFU_2
AB5 Y6
IFPA_TXD3_N RFU_3
AA6
RFU_4
N3
RFU_5
AB3
IFPB_TXC
AB2
IFPB_TXC_N
W1
IFPB_TXD4 S T R AP0
V1 C7
IFPB_TXD4_N STRAP0
W3
LVDS / TMDS
STRAP
IFPB_TXD5 S T R AP1
W2 B9
AA2 IFPB_TXD5_N STRAP1
IFPB_TXD6 S T R AP2
AA3 A9
AB1 IFPB_TXD6_N STRAP2
IFPB_TXD7
AA1
IFPB_TXD7_N
D P A _AUX G4 N5
22 D P A _AUX IFPC_AUX_I2CW_SCL BUFRST_N
D P A _AUX# G5
22 D P A _AUX# IFPC_AUX_I2CW_SDA_N
22 D P A_TXP0 P4
IFPC_L0
N4
GENERAL
22 D P A_TXN0 IFPC_L0_N
M5 D8 VG A_THERMDC
22 D P A_TXP1 IFPC_L1 THERMDN V G A _ T H E RMDC 4
Quick SW 22 D P A_TXN1 M4
L4 IFPC_L1_N D9 VG A_THERMDA
22 D P A_TXP2 IFPC_L2 THERMDP V G A _ T H ERMDA 4
22 D P A_TXN2 K4
IFPC_L2_N
22 D P A_TXP3 H4
J4 IFPC_L3
22 D P A_TXN3 IFPC_L3_N
N2
CEC
D P D _ AUX D3 F9
19 D P D _ AUX IFPD_AUX_I2CX_SCL SPDIF 2009/02/26 Nvidia DB-2
D P D _ AUX# D4
19 D P D _ AUX# IFPD_AUX_I2CX_SDA_N + 3VS
19 D P D_TXP0 F5
IFPD_L0
19 D P D _TXN0 F4
IFPD_L0_N R O M _ CS# R 385 1
E4 B10 2 10K_0402_5%
eDP D5
IFPD_L1 ROM_CS_N
SERIAL
IFPD_L1_N R O M _ SCLK
C3 C9
B
C4 IFPD_L2 ROM_SCLK B
2009/01/20 Nvidia DB-2 IFPD_L2_N R O M _SI
B3 A10
B4 IFPD_L3 ROM_SI
IFPD_L3_N R O M _SO
C10
ROM_SO
D P E _AUX F7
34 D P E _AUX IFPE_AUX_I2CY_SCL
D P E _AUX# G6
34 D P E _AUX# IFPE_AUX_I2CY_SDA_N
34 D P E_TXP0 D6
C6 IFPE_L0 AB6 IFPAB_RSET R 386 1 @ 2 1K_0402_1%
34 D P E_TXN0 IFPE_L0_N IFPAB_RSET
A6
DOCKING 34 D P E_TXP1
A7 IFPE_L1 R5 IFPC_RSET R 387 1 2 1K_0402_1%
34 D P E_TXN1 IFPE_L1_N IFPC_RSET
34 D P E_TXP2 B6
B7 IFPE_L2 M6 I F P D _ R SET R 791 1 2 1K_0402_1%
34 D P E_TXN2 IFPE_L2_N IFPD_RSET
34 D P E_TXP3 E6
IFPE_L3 I F P E _ RSET R 975 1
34 D P E_TXN3 E7 F8 2 1K_0402_1%
IFPE_L3_N IFPE_RSET
N10M-GLM-S-A3_BGA533
D P A _AUX R 976 1 2 100K_0402_5%
D P A _AUX# R 977 1 2 100K_0402_5%
D P D _ AUX R 1056 1 2 100K_0402_5%
D P D _ AUX# R 1057 1 2 100K_0402_5%

GLM:SA000030V20 : S IC N10M-GLM-S-QS(GT218-920) BGA 533P
D P E _AUX R 1103 1 2 100K_0402_5%
D P E _AUX# R 1104 1 2 100K_0402_5%

C
Hynix : SD034150280 S RES 1/16W 15K +-1% 0402 C
Sam sung: SD034200280 S RES 1/16W 20K +-1% 0402
V-BIOS ROM HDCP ROM + 3 VS

Straps
+ 3VS
1 MULTI LEVEL STRAPS
U34 @ C 358 @ S T R AP0
R O M _SI 5 8 0 .1U_0402_16V4Z S T R AP1
SI VDD 2 S T R AP2 FB HW Strap for DDR3: (RAM_CFG @ROM_SI)
R O M _SO 2 7 R O M _SI - Hynix 64Mx16: 0000 (R395 pull-down 15K)
SO HOLD# U 11 @ R O M _SO - Samsung 64Mx16: 0001 (R395 pull-down 20K)
1
R O M _ SCLK 6 3 1 8 R O M _ SCLK
SCK WP# C 882 @ A0 VCC
2 7
R O M _ CS# 0.1U_0402_10V7K A1 WP H DCP_SCL + 3 VS
1 4 3 6 H D C P _ S CL 20
CE# VSS 2 4 A2 SCL 5 HD CP_SDA S t uff R394 --> N10M-GLM, N10M-NS
GND SDA H D C P _ S D A 20
S ST25VF512-20-4C-SAE_SO8 @ 1 R 389 2 1 R 390 2 S tuff R402 --> N10M-NS
A T 2 4 C 1 6BN-SHBY-B 5.1K_0402_1% 45.3K_0402_1% S tuff R403 --> N10M-GLM
H D C P _ S CL
@ 1 R 391 2 1 R 392 2
1
34.8K_0402_1% 34.8K_0402_1% R402/R403:
R 406 @ - 15K: VBIOS combined in SBIOS
10K_0402_5% @ 1 R 393 2 1 R 394 2 - 35K: use VBIOS rom chip
5.1K_0402_1% 24.9K_0402_1%
2
V R A M @ 1 R 395 2 @ 1 R 396 2
20K_0402_1% 5.1K_0402_1%
1 R 398 2 @ 1 R 399 2
10K_0402_1% 10K_0402_1%
N S @ 1 R 402 2 G L M@1 R 403 2

D D
15K_0402_1% 15K_0402_1%

N10M(2)_ LVDS&DP&HDCP
C u s t om L A -4 9 0 1 P 1 .0
1 2 3 4 5
1 2 3 4 5
+ 5VS
U61
C 8 71
0.01U_0402_16V7K
C 8 72
0.01U_0402_16V7K
C 8 73
0 .1U_0402_16V4Z
C 8 74
0 .1U_0402_16V4Z
C 8 75
1 U_0402_6.3V6K
C 8 76
1 U_0402_6.3V6K
1 1 1 1 1 1 2 56 M B _DPA_TXP0 18
8 VDD ML_A 0(p) 55
VDD ML_A 0(n) M B _DPA_TXN0 18
14
VDD
17 53 M B _DPA_TXP1 18
2 2 2 2 2 2 VDD ML_A 1(p)
23 65mA 52 M B _DPA_TXN1 18
VDD ML_A 1(n)
34 M/B DP
VDD
48 50 M B _DPA_TXP2 18
VDD ML_A 2(p)
54 49 M B _DPA_TXN2 18
VDD ML_A 2(n)
2009/01/20 DB-2 add DP Cap. 47
ML_A 3(p) M B _DPA_TXP3 18
0.1U_0402_10V7K 1 2 C 924 D P A_TXP0C 3 46
M D A [63..0] 21 D P A_TXP0 ML_IN 0(p) ML_A 3(n) M B _DPA_TXN3 18
A 0.1U_0402_10V7K 1 2 C 925 D P A _TXN0C 4 A
24,25 M D A [63..0] 21 D P A _TXN0 ML_IN 0(n)
0.1U_0402_10V7K 1 2 C 926 D P A_TXP1C 6 25
21 D P A_TXP1 ML_IN 1(p) ML_B 0(p) D PB_TXP0 34
0.1U_0402_10V7K 1 2 C 927 D P A _TXN1C 7 24
21 D P A _TXN1 ML_IN 1(n) ML_B 0(n) D P B_TXN0 34
GPU 0.1U_0402_10V7K 1 2 C 928 D P A_TXP2C 9 22
0.1U_0402_10V7K 1 2 C 929 D P A _TXN2C 10 21
0.1U_0402_10V7K 1 2 C 930 D P A_TXP3C 12 19
Docking
0.1U_0402_10V7K 1 2 C 931 D P A _TXN3C 13 18
2008/12/12 Nvidia 16
ML_B 3(p) D PB_TXP3 34
T139 H P D - G PU 39 15
CAD ML_B 3(n) D P B_TXN3 34
HPD-C 37
20 H P D - C HPD
+ 3VS 100K_0402_5% 1 2 R 1010 30
U8B D P A _LP LP#
29 45 M B _ DPA_AUX 18
P a rt 2 of 5 Priority AUX_A (p)
24,25 M D A [63..0] C M D A [30..0] 2 4,25 43 M B _ DPA_AUX# 18
MD A0 C MD A0 AUX_A (n)
D22 F26
MD A1 E24 FBA_D0 FBA_CMD0 J24 C MD A1 36 28
FBA_D1 FBA_CMD1 21 D P A _ AUX AUX (p) AUX_B (p) D P B _AUX 34
MD A2 E22 F25 C MD A2 35 26
FBA_D2 FBA_CMD2 21 D P A _AUX# AUX (n) AUX_B (n) D P B _AUX# 34
MD A3 D24 M23 C MD A3
MD A4 FBA_D3 FBA_CMD3 C MD A4
D26 N27 41 C A _ D ET 18
MD A5 D27 FBA_D4 FBA_CMD4 M27 C MD A5 CAD_A 40
FBA_D5 FBA_CMD5 HPD_A M B _ D P _HPD 18
MD A6 C27 K26 C MD A6 5
MD A7 FBA_D6 FBA_CMD6 C MD A7 GND
B27 J25 11 33 C A D _ B 34
MD A8 A21 FBA_D7 FBA_CMD7 J27 C MD A8 20 GND CAD_B 32
FBA_D8 FBA_CMD8 GND HPD_B D P B _ H PD 34
MD A9 B21 G23 C MD A9 27
M D A10 C21 FBA_D9 FBA_CMD9 G26 C M D A10 31 GND
M D A11 FBA_D10 FBA_CMD10 C M D A11 GND R 1011
C19 J23 42 1 1 2 6.49K_0402_1%
M D A12 FBA_D11 FBA_CMD11 C M D A12 GND DP(vadj)
C18 M25 44
M D A13 FBA_D12 FBA_CMD12 C M D A13 GND
D18 K27 51 38 + 3VS
M D A14 FBA_D13 FBA_CMD13 C M D A14 GND VDD*1
B18 G25 57
M D A15 FBA_D14 FBA_CMD14 C M D A15 Thermol pad(GND)
C16 L24
M D A16 FBA_D15 FBA_CMD15 C M D A16 S N 7 5 D P128ARTQR_QFN56_8X8
E21 K23
MEMORY INTERFACE
M D A17 FBA_D16 FBA_CMD16 C M D A17

F21 K24
B
M D A18 D20 FBA_D17 FBA_CMD17 G22 C M D A18
B
M D A19 FBA_D18 FBA_CMD18 C M D A19 + 3VS

F20 K25
M D A20 D17 FBA_D19 FBA_CMD19 H22 C M D A20
M D A21 FBA_D20 FBA_CMD20 C M D A21 H P D - G PU R 1205 1 @
F18 M26 2 100K_0402_5% D P A _LP R 1109 1 2 10K_0402_5%
D16 H24
M D A23 FBA_D22 FBA_CMD22 C M D A23 HPD-C R 1206 1
E16 F27 2 100K_0402_5% R 1110 1 @ 2 10K_0402_5%
A22 J26
M D A25 FBA_D24 FBA_CMD24 C M D A25 2009/06/10 SI-2 Ti request
C24 G24
M D A26 D21 FBA_D25 FBA_CMD25 G27 C M D A26
B22 M24
M D A28 C22 FBA_D27 FBA_CMD27 K22 C M D A28
A25 J22
M D A30 B25 FBA_D29 FBA_CMD29 L22 C M D A30
M D A31 FBA_D30 FBA_CMD30
A26 D Q M A[3..0] 24
M D A32 FBA_D31 D Q M A0
U24 C26
M D A33 V24 FBA_D32 FBA_DQM0 B19 D Q M A1
M D A34 FBA_D33 FBA_DQM1 D Q M A2
V23 D19
R24 D23 D Q M A[7..4] 25
T23 T24
R23 AA23
M D A38 P24 FBA_D37 FBA_DQM5 AB27 D Q M A6
P22 T26
M D A40 AC24 FBA_D39 FBA_DQM7
FBA_D40 D Q S A#[3..0] 24
M D A41 AB23 D25 D Q S A#0
M D A42 FBA_D41 FBA_DQS_RN0 D Q S A#1
AB24 A18
W24 E18
AA22 B24 D Q S A#[7..4] 25
W23 R22
W22 Y24
V22 AA27
AA25 R27
M D A49 FBA_D48 FBA_DQS_RN7
W27 D Q S A [3..0] 24
M D A50 W26 FBA_D49 C25 D Q S A0
M D A51 W25 FBA_D50 FBA_DQS_WP0 A19 D Q S A1
M D A52 FBA_D51 FBA_DQS_WP1 D Q S A2
C AB25 E19 C
M D A53 AB26 FBA_D52 FBA_DQS_WP2 A24 D Q S A3
FBA_D53 FBA_DQS_WP3 D Q S A [7..4] 25
M D A54 AD26 T22 D Q S A4
M D A55 AD27 FBA_D54 FBA_DQS_WP4 AA24 D Q S A5
M D A56 V25 FBA_D55 FBA_DQS_WP5 AA26 D Q S A6
M D A57 FBA_D56 FBA_DQS_WP6 D Q S A7
R25 T27
M D A58 FBA_D57 FBA_DQS_WP7
V26
FBA_D58
M D A59 V27
FBA_D59 FB_VREF
A16 FB_ VREF W=15mils
M D A60 R26
M D A61 T25 FBA_D60 F24
FBA_D61 FBA_CLK0 C L KA0 24
M D A62 N25 F23 C L KA0# 24
M D A63 N26 FBA_D62 FBA_CLK0_N
FBA_D63
N24 C L KA1 25
FBA_CLK1 N23 + V D D _MEM
FBA_CLK1_N C L KA1# 25
M22 R 1072 1 2 10K_0402_5%
FBA_DEBUG
N10M-GLM-S-A3_BGA533
+ V D D _MEM
1
2009/02/13 Nvidia DB-2
@ R 4 07 Rt C M D A28 R 1154 1 2 10K_0402_5%

1K_0402_1%
C M D A30 R 1155 1 2 10K_0402_5%
2
FB_ VREF
C MD A7 R 1077 1 2 10K_0402_5%
1
1
C M D A18 R 409 1 2 10K_0402_5%
@ R 4 10 Rb C 361
D D
1K_0402_1% @ 0 .1U_0402_16V4Z 2009/02/06 Nvidia DB-2
2
2
2009/02/06 Nvidia (del termation rsistor)
Close to U8

N10M(3)_VGA RAM Interface
C u s t om L A -4 9 0 1 P 1 .0
1 2 3 4 5
1 2 3 4 5
VGA Pow er sequence: +.3VS->+NVVDD->+VDD_MEM + V D D _MEM U 8E

+NVVDD U 8D B2 P a rt 5 of 5 U2
P a rt 4 of 5 B5 GND GND U5
2009/02/27 Nvidia DB-2 NV care
15.69A GND GND
J9 A13 B8 U11
VDD FBVDDQ GND GND
4.7U_0603_6.3V6K
0 .1U_0402_16V4Z
0.047U_0402_16V7K
0.047U_0402_16V7K
0.047U_0402_16V7K
0.01U_0402_16V7K
0.01U_0402_16V7K
0.01U_0402_16V7K
0.01U_0402_16V7K
0.01U_0402_16V7K
0.01U_0402_16V7K
J10 B13 B11 U12
VDD FBVDDQ GND GND
C 405
C 408
C 381
C 362
C 363
C 364
C 365
C 366
C 367
C 368
C 369
0.01U_0402_16V7K
0.01U_0402_16V7K
0.01U_0402_16V7K
0.047U_0402_16V7K
0.047U_0402_16V7K
0.047U_0402_16V7K
1 U_0402_6.3V4Z
4.7U_0603_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 J12 C13 B14 U13
VDD FBVDDQ GND GND
C 370
C 371
C 372
C 373
C 826
C 827
C 828
C 380
J13 D13 1 1 1 1 1 1 1 1 B17 U14
VDD FBVDDQ GND GND
L9 D14 B20 U15
VDD FBVDDQ GND GND
M9 E13 B23 U16
2 2 2 2 2 2 2 2 2 2 2 VDD FBVDDQ GND GND
M11 F13 B26 U17
VDD FBVDDQ 2 2 2 2 2 2 2 2 GND GND
M17 F14 E2 U23
VDD FBVDDQ GND GND
N9 F15 E5 U26
VDD FBVDDQ GND GND
N11 F16 E8 V9
VDD FBVDDQ GND GND
N12 F17 E11 V19
VDD FBVDDQ GND GND
A N13 F19 E17 W11 A
VDD FBVDDQ 2009/02/27 Nvidia DB-2 NV care GND GND
N14
VDD 2.63A FBVDDQ F22 E20
GND GND
W14
N15 H23 E23 W17
VDD FBVDDQ GND GND
N16 H26 E26 Y2
VDD FBVDDQ GND GND
N17 J15 H2 Y5
GND
VDD FBVDDQ GND GND
N19 J16 H5 Y23
VDD FBVDDQ GND GND
P11 J18 J11 Y26
VDD FBVDDQ GND GND
0.022U_0402_16V7K
0.022U_0402_16V7K
0.022U_0402_16V7K
0.022U_0402_16V7K
0.022U_0402_16V7K
0.022U_0402_16V7K
P12 J19 J14 AC2
VDD FBVDDQ GND GND
C 384
C 385
C 386
C 387
C 388
C 389
1 1 1 1 1 1 P13 L19 J17 AC5
VDD FBVDDQ GND GND
P14 L23 K9 AC6
P15 VDD FBVDDQ L26 K19 GND GND AC8
VDD FBVDDQ GND GND
P16 M19 L2 AC11
2 2 2 2 2 2 P17 VDD FBVDDQ N22 L5 GND GND AC14
VDD FBVDDQ GND GND
R9 U22 L11 AC17
VDD FBVDDQ + 1.05VS GND GND
R11 Y22 L12 AC20
POWER
VDD FBVDDQ GND GND
R12 L13 AC23
VDD GND GND
R13 AG6 L14 AC26
VDD PEX_IOVDDQ GND GND
R14 AF6 L15 AF2
0.1U_0402_10V6K
0.1U_0402_10V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
4.7U_0603_6.3V6K
10U_0805_6.3V6M
22U_0805_6.3V6M
R15 AE6 L16 AF5
C 4 09
C 4 10
C 4 11
C 4 12
C 4 13
C 4 14
C 4 02
R16 AD6 1 1 1 1 1 1 1 L17 AF8
R17 VDD PEX_IOVDDQ AC13 M12 GND GND AF11
T9 AC7 M13 AF14
10U_0805_6.3V6M
1 U_0402_6.3V4Z
1 U_0402_6.3V4Z
T11 2A AB17 M14 AF17
VDD PEX_IOVDDQ 2 2 2 2 2 2 2 GND GND
C 404
C 406
C 407
1 1 1 T17 AB16 M15 AF20
U9 AB13 M16 AF23
U19 VDD PEX_IOVDDQ AB9 P2 GND GND AF26
W9 AB8 P5 T16
2 2 2 W10 VDD PEX_IOVDDQ AB7 + 1.05VS P9 GND GND T15
VDD PEX_IOVDDQ Layout Note:Please GND GND
W12 600 mA P19 T14
VDD colse to Ball. GND GND
W13 AG7 P23 F6
VDD PEX_IOVDD GND GND 2009/02/13 Nvidia DB-2
W18 AF7 P26
VDD PEX_IOVDD GND
C 415
0.1U_0402_10V6K
C 416
0.1U_0402_10V6K
C 417
1U_0402_6.3V6K
C 418
1U_0402_6.3V6K
C 419
4.7U_0603_6.3V6K
C 420
10U_0805_6.3V6M
C 403
22U_0805_6.3V6M
+ 3VS W19 AE7 T12 A15 R 1058 1 2 40.2_0402_1%
VDD PEX_IOVDD 1 1 1 1 1 1 1 GND FB_CAL_PU_GND
AD8 T13
PEX_IOVDD GND R 1059 1 2 60.4_0402_1%
120mA AD7 B16
R 7 92 1 PEX_IOVDD FB_CAL_TERM_GND
2 0_0603_5% V D D 33 A12 AC9
B
B12 VDD33 PEX_IOVDD 2 2 2 2 2 2 2 0_0402_5% 1 2 R 4 13 W16 F11 R 383 1 2 40.2K_0402_1%
B
VDD33 GND_SENSE MULTI_STRAP_REF1_GND
4.7U_0603_6.3V6K
1 U_0402_6.3V4Z
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
C12 AF9 P E X _ PLLDVDD

VDD33 PEX_PLLVDD
C 421
C 422
C 423
C 959
C 960
1 1 1 1 1 D12 0_0402_5% 1 2 R 4 14 E14 F10 R 384 1 2 40.2K_0402_1%

VDD33 GND_SENSE MULTI_STRAP_REF0_GND
E12 45mA VID_PLLVDD K6
VDD33
F12
VDD33 S P _ P LLVDD G P U _ P LLVDD N10M-GLM-S-A3_BGA533
45mA L6
2 2 2 2 2 SP_PLLVDD
P E X _SVDD_3V3 AG9 60mA PLLVDD K5
PEX_SVDD_3V3 2008/12/20 Nvidia request to splite the power plan for SSC
2009/02/27 Nvidia DB-2 NV care R19 + 3VS
10K_0402_5% 1 FB_PLLAVDD
2 R 1175 IF P A_IOVDD V3 120mA
IFPA_IOVDD R 631 1
AC19 F B _ P L L AVDD P E X _SVDD_3V3 2 0_0402_5%
10K_0402_5% 1 2 R 1176 I F P B _ I OVDD V2 FB_PLLAVDD
IFPB_IOVDD
0.1U_0402_10V6K
1 U_0402_6.3V4Z
4.7U_0603_6.3V6K
T19
FB_DLLAVDD
C 4 57
C 4 58
C 8 52
IF P C_IOVDD J6 1 1 1
IFPC_IOVDD
2009/03/30 Nvidia DB-3 I F P D E _ I O VDD H6 AG2 DACA_VDD
IFPDE_IOVDD DACA_VDD
W5 DACB_VDD R 415 1 2 10K_0402_5% 2 2 2
10K_0402_5% 1
120mA DACB_VDD
2 R 1177 I FPAB_PLLVDD AD5
IFPAB_PLLVDD
IF PC_PLLVDD P6 B15 R 418 1 2 40.2_0402_1% + V D D _MEM
IFPC_PLLVDD FB_CAL_PD_VDDQ
I F P D _ P L LVDD N6 W15 2009/02/27 Nvidia DB-2 NV care
IFPD_PLLVDD VDD_SENSE
I F P E _ P LLVDD D7 E15 R 371 1 2 0_0402_5% + N V V D D _ S ENSE to Pow er Layout Note:Please Layout Note:Please
IFPE_PLLVDD VDD_SENSE + N V V D D _ S ENSE 48 colse to Ball. colse to BGA.
N10M-GLM-S-A3_BGA533 +1.05VS
200mA L18
F B _ P L L AVDD 1 2
B LM18PG181SN1D_0603
4700P_0402_25V7K
1 U_0402_6.3V4Z
4.7U_0603_6.3V6K
1 U_0402_6.3V4Z
C 438
C 439
C 440
C 441
1 1 1 1
C + 3VS + 1.05VS C
L37 220mA L38 285mA
1 2 IF PD_PLLVDD 1 2 IF P DE_IOVDD
P B Y160808T-301Y-N_0603 P B Y 160808T-221Y-N_2P Layout Note:Please 2 2 2 2 Layout Note:Please
1U_0603_10V6K
4.7U_0603_6.3V6K
1U_0402_6.3V6K
0.1U_0402_10V6K
4.7U_0603_6.3V6K
1U_0603_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
colse to Ball. colse to BGA.
C 8 53
C 8 54
C 8 55
C 8 56
C 8 57
C 8 58
C 8 59
C 8 60
1 1 1 1 1 1 1 1
Layout Note:Please
2009/03/30 Nvidia DB-3 colse to BGA.
2 2 2 2 2 2 2 2 +1.05VS
2009/03/30 Nvidia DB-3
105mA L 21
G P U _ P LLVDD 1 2
2009/02/27 Nvidia DB-2 NV care 2009/02/27 Nvidia DB-2 NV care 1 0 0 NH_CLH1608T-R10J-S_5%
4.7U_0603_6.3V6K
0 .1U_0402_16V4Z
1 U_0402_6.3V4Z
0 .1U_0402_16V4Z
C 450
C 451
C 452
C 453
1 1 1 1
Layout Note:Please
colse to Ball. Layout Note:Please
+ 3VS + 3VS colse to BGA.
L 19 L41 2 2 2 2
220mA IF PC_PLLVDD
220mA I FPE_PLLVDD Layout Note:Please
1 2 1 2
P B Y160808T-301Y-N_0603 P B Y160808T-301Y-N_0603 colse to Ball.
+ 1.05VS
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
1U_0402_6.3V6K
0.1U_0402_10V6K
1U_0603_10V6K
4.7U_0603_6.3V6K
1U_0402_6.3V6K
0.1U_0402_10V6K
C 442
C 443
C 444
C 445
C 893
C 894
C 895
C 896
1 1 1 1 1 1 1 1 L47
S P _ P LLVDD 1 2
1 0 0 N H_CLH1608T-R10J-S_5%
+1.05VS
2 2 2 2 2 2 2 2
4.7U_0603_6.3V6K
1U_0402_6.3V6K
120mA L15
C 958
C 941
1 1 PEX_PLLDVDD 1 2
0 . 1 U H_MLF1608DR10KT_10%_1608
0.01U_0402_25V7K
0 .1U_0402_16V4Z
1 U_0402_6.3V4Z
4.7U_0603_6.3V6K
1 U_0402_6.3V4Z
1 U_0402_6.3V4Z
2009/02/23 Nvidia DB-2
C 4 24
C 4 25
C 4 26
C 4 27
C 4 28
C 8 29
2 2 1 1 1 1 1 1
Layout Note:Please
colse to BGA.
+ 3VS + 1.05VS 2 2 2 2 2 2
D D
L22 120mA L20 300mA
1 2 DACA_VDD 1 2 IF P C_IOVDD Layout Note:Please
B LM18PG181SN1D_0603 P B Y160808T-221Y-N_2P colse to Ball.
4.7U_0603_6.3V6K
1 U_0402_6.3V4Z
4700P_0402_25V7K
0.1U_0402_10V6K
4.7U_0603_6.3V6K
1U_0603_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
C 884
C 454
C 455
C 456
C 446
C 447
C 448
C 449
1 1 1 1 1 1 1 1
Layout Note:Please
colse to BGA.
2 2 2 2 2 2 2 2
N10M(4)_Power/GND
Layout Note:Please
C u s t om L A -4 9 0 1 P 1 .0
colse to Ball. MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1 2 3 4 5
1 2 3 4 5
VRAM DDR3 chips (512MB) Hynix : H5TQ1G63BFR-12C-->SA000032400 DATA Bus

Sam sung : K4W1G1646E-HC12-->SA000035700 Address 0..31 32..63
64Mx16 DDR3 800MHz*4==>512MB
CMD0 A4
Low 32 bit FB U 13 VR AM@ U14 VR AM@
CMD1 RAS# RAS#
CMD2 A5
M E M _ V REF0 M9 E4 MD A8 M E M _ V REF1 M9 E4 MD A0
VREFCA DQL0 MD A9 VREFCA DQL0 MD A1
H2
VREFDQ DQL1
F8 H2
VREFDQ DQL1
F8 CMD3 BA1 BA1
D Q S A [7..0] F3 M D A10 F3 MD A2
22,25 D Q S A[7..0] DQL2 DQL2
C M D A19 N4
A0 DQL3
F9 M D A11 C M D A19 N4
A0 DQL3
F9 MD A3 CMD4 A2
A D Q S A#[7..0] C M D A25 P8 H4 M D A12 C M D A25 P8 H4 MD A4 A
22,25 D Q S A#[7..0] A1 DQL4 A1 DQL4
C M D A22 P4
A2 DQL5
H9 M D A13 C M D A22 P4
A2 DQL5
H9 MD A5 CMD5 A4
D Q M A[7..0] C M D A24 N3 G3 M D A14 C M D A24 N3 G3 MD A6
22,25 D Q M A[7..0] A3 DQL6 A3 DQL6
C MD A0 P9 H8 M D A15 C MD A0 P9 H8 MD A7 CMD6 A3
M D A [63..0] C MD A2 A4 DQL7 C MD A2 A4 DQL7
22,25 M D A[63..0] P3 P3
C M D A21 A5 C M D A21 A5
R9
A6
R9
A6 CMD7 CKE
C M D A [30..0] C M D A16 R3 D8 M D A16 2008/12/08 swap data bus for layout C M D A16 R3 D8 M D A24 2008/12/08 swap data bus for layout
22,25 C M D A [30..0] A7 DQU0 A7 DQU0
C M D A23 T9 C4 M D A21 C M D A23 T9 C4 M D A29 CMD8 CS#
C M D A20 A8 DQU1 M D A19 C M D A20 A8 DQU1 M D A26
R4 C9 R4 C9
A9 DQU2 A9 DQU2
C M D A17 L8
A10/AP DQU3
C3 M D A20 C M D A17 L8
A10/AP DQU3
C3 M D A30 CMD9 A11 A11
C MD A9 R8 A8 M D A18 C MD A9 R8 A8 M D A28
A11 DQU4 A11 DQU4
C M D A14 N8
A12 DQU5
A3 M D A22 C M D A14 N8
A12 DQU5
A3 M D A25 CMD10 CAS# CAS#
C M D A26 T4 B9 M D A17 C M D A26 T4 B9 M D A27
A13 DQU6 M D A23 A13 DQU6 M D A31
T8
A14 DQU7
A4 T8
A14 DQU7
A4 CMD11 WE# WE#
M8 M8
A15/BA3 + V D D _MEM A15/BA3 + V D D _MEM
CMD12 BA0 BA0
C M D A12 M3 B3 C M D A12 M3 B3 CMD13 A5
C MD A3 N9 BA0 VDD D10 C MD A3 N9 BA0 VDD D10
BA1 VDD BA1 VDD
C M D A27 M4
BA2 VDD
G8 C M D A27 M4
BA2 VDD
G8 CMD14 A12 A12
K3 K3
VDD VDD
VDD
K9
VDD
K9 CMD15 RST RST
N2 N2
C L KA0 VDD C L KA0 VDD
J8
CK VDD
N10 J8
CK VDD
N10 CMD16 A7 A7
C L KA0# K8 R2 C L KA0# K8 R2
C M D A18 CK VDD C M D A18 CK VDD
K10
CKE/CKE0 VDD
R10
+ V D D _MEM
K10
CKE/CKE0 VDD
R10
+ V D D _MEM
CMD17 A10 A10
CMD18 CKE
C M D A30 K2 A2 C M D A30 K2 A2
ODT/ODT0 VDDQ ODT/ODT0 VDDQ
C M D A29 L3
CS VDDQ
A9 C M D A29 L3
CS VDDQ
A9 CMD19 A0 A0
C MD A1 J4 C2 C MD A1 J4 C2
RAS VDDQ RAS VDDQ
C M D A10 K4
CAS VDDQ
C10 C M D A10 K4
CAS VDDQ
C10 CMD20 A9 A9
C M D A11 L4 D3 C M D A11 L4 D3
WE VDDQ WE VDDQ
310mAVDDQ E10
VDDQ
E10 CMD21 A6 A6
B
D Q S A1 VDDQ
F2
D Q S A0
310mAVDDQ F2 B
F4
DQSL VDDQ
H3 F4
DQSL VDDQ
H3 CMD22 A2
D Q S A2 C8 H10 D Q S A3 C8 H10
DQSU VDDQ DQSU VDDQ
CMD23 A8 A8
D Q M A1 E8
DML VSS
A10 D Q M A0 E8
DML VSS
A10 CMD24 A3
D Q M A2 D4 B4 D Q M A3 D4 B4
DMU VSS DMU VSS
VSS
E2
VSS
E2 CMD25 A1 A1
G9 G9
D Q S A#1 VSS D Q S A#0 VSS
G4
DQSL VSS
J3 G4
DQSL VSS
J3 CMD26 A13 A13
D Q S A#2 B8 J9 D Q S A#3 B8 J9
DQSU VSS DQSU VSS
VSS
M2
VSS
M2 CMD27 BA2 BA2
M10 M10
VSS VSS
VSS
P2
VSS
P2 CMD28 ODT
22,25 C M D A 15 C M D A15 T3 P10 C M D A15 T3 P10
RESET VSS RESET VSS
VSS
T2
VSS
T2 CMD29 CS#
ZQ 0 L9 T10 ZQ 1 L9 T10
ZQ/ZQ0 VSS ZQ/ZQ0 VSS
CMD30 ODT
1
1
10K_0402_5%
243_0402_1%
243_0402_1%
J2 B2 J2 B2 LOW HIGH
NC/ODT1 VSSQ NC/ODT1 VSSQ
R 4 21
R 4 22
R 4 23
L2 B10 L2 B10
J10 NC/CS1 VSSQ D2 J10 NC/CS1 VSSQ D2
NC/CE1 VSSQ NC/CE1 VSSQ
L10 D9 L10 D9
NCZQ1 VSSQ E3 NCZQ1 VSSQ E3
2
2
A1 VSSQ E9 A1 VSSQ E9
NC VSSQ NC VSSQ
A11 F10 A11 F10
NC VSSQ NC VSSQ
T1 G2 T1 G2
NC VSSQ NC VSSQ
T11 G10 T11 G10
NC VSSQ NC VSSQ
100-BALL 100-BALL
S D R A M D DR3 S D R A M D DR3
K 4 B 1 G 1646D-HCF8_FBGA100 K 4 B 1 G 1 646D-HCF8_FBGA100
+ V D D _MEM
C C
1
+ V D D _MEM C L KA0
22 C L K A0
R 424
1
1K_0402_1%
1
R 425
R 4 26 121_0402_1%
2
1K_0402_1%
M E M _ V REF1
2
2
1
1 2 1
M E M _ V REF0 0.01U_0402_16V7K C 459 R 427 C 460
1K_0402_1% 0.01U_0402_16V7K
1
1 2
R 4 28 C 4 61 R 429
2
1K_0402_1% 0.01U_0402_16V7K 121_0402_1%
2
2
C L KA0#
22 C L KA0#
+ V D D _MEM
DDR3 BGA MEMORY
+ V D D _MEM
DDR3 BGA MEMORY
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
C 462
C 463
C 464
C 465
C 466
C 467
C 468
C 469
C 470
C 471
1 1 1 1 1 1 1 1 1 1
1 U_0402_6.3V6K
1 U_0402_6.3V6K
1 U_0402_6.3V6K
1 U_0402_6.3V6K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
C 472
C 473
C 474
C 475
C 476
C 477
C 478
C 479
C 480
C 481
1 1 1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2 2
D 2 2 2 2 2 2 2 2 2 2 D

VRAM DDR3
0.1
LA-4901P
1 2 3 4 5
1 2 3 4 5
VRAM DDR3 chips (512MB) 22,24 D Q S A[7..0]

D Q S A [7..0]
D Q S A#[7..0]
64Mx16 DDR3 800MHz*4==>512MB 22,24 D Q S A#[7..0]
D Q M A[7..0]
22,24 D Q M A[7..0]
High 32 bit FB 22,24 M D A [63..0]
M D A [63..0]
U 15 VR AM@ C M D A [30..0] U 16 VR AM@

22,24 C M D A [30..0]
M E M _ V REF2 M9 E4 M D A32 M E M _ V REF3 M9 E4 M D A45
VREFCA DQL0 M D A33 VREFCA DQL0 M D A41
H2 F8 H2 F8
VREFDQ DQL1 M D A34 VREFDQ DQL1 M D A43
F3 F3
C M D A19 DQL2 M D A35 C M D A19 DQL2 M D A42
N4 F9 N4 F9
C M D A25 A0 DQL3 M D A36 C M D A25 A0 DQL3 M D A44
A P8 H4 P8 H4 A
C MD A4 A1 DQL4 M D A37 C MD A4 A1 DQL4 M D A40
P4 H9 P4 H9
N3 G3 N3 G3
P9 H8 P9 H8
C M D A13 A4 DQL7 C M D A13 A4 DQL7
P3 P3
C M D A21 A5 C M D A21 A5 2008/12/08 swap data bus for layout
R9 R9
C M D A16 A6 M D A60 2008/12/08 swap data bus for layout C M D A16 A6 M D A54
R3 D8 R3 D8
T9 C4 T9 C4
R4 C9 R4 C9
L8 C3 L8 C3
C MD A9 R8 A10/AP DQU3 A8 M D A57 C MD A9 R8 A10/AP DQU3 A8 M D A52
N8 A3 N8 A3
C M D A26 T4 A12 DQU5 B9 M D A63 C M D A26 T4 A12 DQU5 B9 M D A55
A13 DQU6 M D A58 A13 DQU6 M D A49
T8 A4 T8 A4
A14 DQU7 A14 DQU7
M8 M8
A15/BA3 + V D D _MEM A15/BA3 + V D D _MEM
C M D A12 M3 B3 C M D A12 M3 B3
C MD A3 N9 BA0 VDD D10 C MD A3 N9 BA0 VDD D10
C M D A27 BA1 VDD C M D A27 BA1 VDD
M4 G8 M4 G8
BA2 VDD K3 BA2 VDD K3
VDD VDD
K9 K9
VDD N2 VDD N2
C L KA1 J8 VDD N10 C L KA1 J8 VDD N10
C L KA1# CK VDD C L KA1# CK VDD
K8 R2 K8 R2
C MD A7 K10 CK VDD R10 C MD A7 K10 CK VDD R10
22 C MD A7 CKE/CKE0 VDD + V D D _MEM 22 C MD A7 CKE/CKE0 VDD + V D D _MEM
22 C M D A 28 C M D A28 K2 A2 22 C M D A28 C M D A28 K2 A2

C MD A8 ODT/ODT0 VDDQ C MD A8 ODT/ODT0 VDDQ
L3 A9 L3 A9
C MD A1 J4 CS VDDQ C MD A1 CS VDDQ
C2 J4 C2
C M D A10 RAS VDDQ C M D A10 RAS VDDQ
K4 C10 K4 C10
C M D A11 CAS VDDQ C M D A11 CAS VDDQ
L4 D3 L4 D3
WE VDDQ WE VDDQ
310mAVDDQ E10 310mAVDDQ E10
F2 F2
B
D Q S A4 F4 VDDQ H3 D Q S A5 F4 VDDQ H3
B
D Q S A7 DQSL VDDQ D Q S A6 DQSL VDDQ

C8 H10 C8 H10
DQSU VDDQ DQSU VDDQ
D Q M A4 E8 A10 D Q M A5 E8 A10
D Q M A7 DML VSS D Q M A6 DML VSS
D4 B4 D4 B4
DMU VSS DMU VSS
E2 E2
VSS VSS
G9 G9
D Q S A#4 G4 VSS J3 D Q S A#5 G4 VSS J3
D Q S A#7 DQSL VSS D Q S A#6 DQSL VSS
B8 J9 B8 J9
DQSU VSS M2 DQSU VSS M2
VSS VSS
M10 M10
VSS P2 VSS P2
C M D A15 VSS C M D A15 VSS
T3 P10 T3 P10
RESET VSS RESET VSS
T2 T2
ZQ 2 L9 VSS T10 ZQ 3 L9 VSS T10
ZQ/ZQ0 VSS ZQ/ZQ0 VSS
J2 B2 J2 B2
NC/ODT1 VSSQ NC/ODT1 VSSQ
1
1
243_0402_1%
243_0402_1%
L2 B10 L2 B10
NC/CS1 VSSQ NC/CS1 VSSQ
R 432
R 433
J10 D2 J10 D2
NC/CE1 VSSQ NC/CE1 VSSQ
L10 D9 L10 D9
NCZQ1 VSSQ E3 NCZQ1 VSSQ E3
A1 VSSQ E9 A1 VSSQ E9
2
2
NC VSSQ NC VSSQ
A11 F10 A11 F10
NC VSSQ NC VSSQ
T1 G2 T1 G2
NC VSSQ NC VSSQ
T11 G10 T11 G10
NC VSSQ NC VSSQ
100-BALL 100-BALL
S D R A M D DR3 S D R A M D DR3 + V D D _MEM
K 4 B 1 G 1646D-HCF8_FBGA100 C L KA1 K 4 B 1 G 1646D-HCF8_FBGA100
22 C L K A1
1
+ V D D _MEM
R 436
C R 434 1K_0402_1% C
1
121_0402_1%
R 435
2
1K_0402_1%
1 2 M E M _ V REF3
0.01U_0402_16V7K C 482
2
1
1
1
M E M _ V REF2 R 439 C 484
1K_0402_1% 0.01U_0402_16V7K
1
1 R 437
R 438 C 483 121_0402_1% 2
2
1K_0402_1% 0.01U_0402_16V7K
2
C L KA1#
2 22 C L K A1#
2
+ V D D _MEM
DDR3 BGA MEMORY + V D D _MEM
DDR3 BGA MEMORY
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
C 4 85
C 4 86
C 4 87
C 4 88
C 4 89
C 4 90
C 4 91
C 4 92
C 4 93
C 4 94
C 4 95
C 4 96
C 4 97
C 4 98
C 4 99
C 5 00
C 5 01
C 5 02
C 5 03
C 5 04
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
D D

VRAM DDR3
0.1
Cartier DIS
1 2 3 4 5
1 2 3 4 5
From Power
+ 1 .0VM_LAN + 1.05VM_LAN
R 442
0_0603_5%
1 2
10U_0805_6.3V6M
0 .1U_0402_16V4Z
C 5 09
C 5 10
2009/02/19 HP DB-2 1 1
A A
2 2
From Power
+ 3VM + 3 VM_LAN
R 932
0_0603_5%
1 2
0 .1U_0402_16V4Z
1 0U_0805_10V4Z
C 513
C 514
1 1
2 2
2009/05/02 HP SI-1
R 1199 1 2 0_0402_5%
13 C L K _ P C IE_LAN_REQ1#
B B
2009/01/22 HP
U18
R 930 1 @ 2 0_0402_5% C L K _ P C I E_LAN_REQ#_R 48 13

15 C L K _ P C I E_LAN_REQ# CLK_REQ_N MDI_PLUS0 L A N _ MDI0P 27
4,12,15,20,28,31,33 P L T_RST# R 450 1 2 0_0402_5% P L T _RST#_LAN 36 14
PE_RST_N MDI_MINUS0 L A N _ M DI0N 27
15 C L K _ P C IE_LAN 44 17 L A N _ MDI1P 27
45 PE_CLKP MDI_PLUS1 18
15 C L K _ P C IE_LAN#
PCIE
PE_CLKN MDI_MINUS1 L A N _ M DI1N 27
MDI
C 516 1 2 0.1U_0402_10V7K P C I E_PRX_DTX_P6_C 38 20
13 P C I E_PRX_DTX_P6 PETp MDI_PLUS2 L A N _ MDI2P 27
C 518 1 2 0.1U_0402_10V7K P C I E _PRX_DTX_N6_C 39 21
13 P C I E _PRX_DTX_N6 PETn MDI_MINUS2 L A N _ M DI2N 27
13 P C I E _PTX_C_DRX_P6 41 23 L A N _ MDI3P 27
PERp MDI_PLUS3
13 P C I E _ PTX_C_DRX_N6 42 24 L A N _ M DI3N 27
PERn MDI_MINUS3 2009/01/22 HP
R 451 1 2 0_0402_5% L A N _ SM_CLK 28 6
SMBUS
13 S M L 0CLK SMB_CLK VCT T R M _CT 27
R 452 1 2 0_0402_5% L A N _ SM_DAT 31
13 S M L 0DATA SMB_DATA
1 R 453 1 2 3.01K_0402_1% + 3 VM_LAN
RSVD_VCC3P3_1 R 454 1
2 2 3.01K_0402_1%
RSVD_VCC3P3_2
5
R 455 1 2 0_0402_5% L A N _ P H Y P C_R 3 VDD3P3_IN
15,27 L A N _ DIS# LAN_DISABLE_N 4 + 3 . 3VM_LAN_OUT
2009/02/06 HP DB-2 VDD3P3_OUT
1
R 1135 1 @ 2 0_0402_5% 92mAVDD3P3_15 15 + 3 . 3 VM_LAN_OUT_R 1 2
15,27 L E D _ L I NK_LAN#_R
L E D _ LINK_LAN# 26 19 R 4 56 0_0603_5% C 524
27 L E D _ L INK_LAN# LED0 VDD3P3_19
L A N _ACT# 27 29 1 U_0603_10V4Z
27,34 L A N _ ACT#
LED
LED1 VDD3P3_29 2
25
LED2
47 + 1 .0VM_LAN4 1 2
VDD1P0_47 R 4 57 0_0603_5%
46
32 VDD1P0_46 37
T65 JTAG_TDI VDD1P0_37
T66 34
JTAG
R 458 1 @ JTAG_TDO
C + 3 VM_LAN 2 10K_0402_5% L A N _JTAG_TMS 33 43 + 1 .0VM_LAN3 1 2 + 1 .0VM_LAN C
R 460 1 @ 2 10K_0402_5% L A N _ JTAG_TCK 35 JTAG_TMS VDD1P0_43 R 4 59 0_0603_5%
JTAG_TCK + 1 .0VM_LAN2
11 1 2
VDD1P0_11 R 4 61 0_0603_5%
XTAL1_C
328mA
9 40
XTAL2 XTAL_OUT VDD1P0_40
10 22
XTAL_IN VDD1P0_22
16
VDD1P0_16 + 1 .0VM_LAN1
8 1 2
R 463 1 VDD1P0_8
2 1K_0402_5% 30 R 4 62 0_0603_5%
TEST_EN
R 464 1 2 3.01K_0402_1% 12 7 L A N _CTRL_18 T138
RBIAS CTRL_1P0
49
2008/11/17 HP VSS_EPAD
W G 8 2 577LM_QFN48P
2009/02/06 HP DB-2
XTAL1 C 934 1 2 10P_0402_50V8C XTAL1_C
Y5
2 5 M H Z _18PF_X5H025000DI1H-H
1 2 XTAL2
1 1
C 529 C 530
33P_0402_50V8J 33P_0402_50V8J
D 2 2 D
2009/09/11 HP PV

Intel 82566 Nineveh
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS L A - 4901P 1 .0
1 2 3 4 5
1 2 3 4 5
+ 3 VM_LAN
RJ-45 CONN.
1 10K_0402_5%
R 926
JP6
2
+ 3 V M_LAN_LED 13
Yellow LED+
L A N _ACT# R 467 1 2 300_0603_5% 14
26,34 L A N _ACT# Yellow LED-
16
M DO3- SHLD1
8
PR4-
A 1 2 9 A
@ 680P_0402_50V7K C 535 M D O3+ DETECT PIN1
7
PR4+
M DO1- 6
PR2-
M DO2- 5
+ 3 VM_LAN PR3-
M D O2+ 4
PR3+
M D O1+ 3
1
PR2+
10K_0402_5%
R 468
R 1137 1 2 0_0402_5% 1 3 L E D _ LINK_LAN# M DO0- 2
S
15,26 L E D _ L INK_LAN#_R PR1-
Q 73 10
2N7002H_SOT23-3 M D O0+ DETCET PIN2
34 L E D _ L I N K_LAN_DOCK# 1
PR1+
15
G
2
2
SHLD1
+ 3 V M_LAN_LED 11
Green LED+
26 L E D _ L INK_LAN# L E D _ LINK_LAN# R 470 1 2 300_0603_5% 12
Green LED-
L A N _ DIS# 15,26 2009/01/22 HP DB-2 FOX_JM36113-P1123-7F
2
C ONN@
1 2
2009/01/22 HP DB-2 @ 680P_0402_50V7K C 538
2009/02/24 Compal DB-2
D 57 @
P J D LC05H_SOT23-3
2009/02/18 Compal DB-2 EMI
1
B B
+ 3 VM_LAN + 3 V M_LAN_LED
Q17
20 mil SI2301CDS-T1-GE3_SOT23-3 20 mil
D
3 1
G
2
R 4 73
100K_0402_5%
+ 3 VM_LAN
1
D
1
34 DOCK_ID 2 Q23
G 2N7002H_SOT23-3
R 1025 @ S
3
0_0402_5%
2
T1
L A N _ MDI0N 12 13 M DO0-
26 L A N _ MDI0N TD4- MX4- M D O0- 34
Change design. 10/12
L A N _ MDI0P 11 14 M D O0+ R 469

26 L A N _ MDI0P TD4+ 1:1 MX4+ M D O0+ 34
1 2 75_0402_1%
26 T R M _CT
C R 1083 @ 0_0402_5% 1 2 T R M _ CT_R 10 15 M C T0 C 537 1 2 0.01U_0402_50V7K 1 2 C
2009/04/10 HP DB-3 C 5 36 1U_0402_6.3V6K TCT4 MCT4
L A N _ MDI1N 9 16 M DO1-
26 L A N _ MDI1N TD3- MX3- M D O1- 34
2009/01/22 HP
L A N _ MDI1P 8 17 M D O1+ R 471

26 L A N _ MDI1P TD3+ 1:1 MX3+ M D O1+ 34
75_0402_1%
T R M _ CT_R 7 18 M C T1 C 540 1 2 0.01U_0402_50V7K 1 2
TCT3 MCT3
26 L A N _ MDI2N TD2- MX2- M D O2- 34
L A N _ MDI2P 5 20 M D O2+ R 472

26 L A N _ MDI2P TD21+ MX2+ M D O2+ 34
75_0402_1%
1:1
T R M _ CT_R 4 21 M C T2 C 542 1 2 0.01U_0402_50V7K 1 2
TCT2 MCT2
26 L A N _ MDI3N TD1- MX1- M D O3- 34
L A N _ MDI3P 2 23 M D O3+ R 474

26 L A N _ MDI3P TD1+ 1:1 MX1+ M D O3+ 34
75_0402_1%
T R M _ CT_R 1 24 M C T3 C 544 1 2 0.01U_0402_50V7K 1 2 C 545 1 2 1000P_1808_3KV7K
TCT1 MCT1
3 50uH_NS892402P
T R M _ CT_R
D D
0 .1U_0402_16V4Z
0 .1U_0402_16V4Z
0 .1U_0402_16V4Z
0 .1U_0402_16V4Z
C 962
C 963
C 964
C 965
1 1 1 1
2 2 2 2
place 1 capacitor at each pin (1,4,7,10) S ecurity Classification Compal Secret Data Compal Electronics, Inc.
2009/04/24 HP SI-1
Magnetic & RJ45
1 2 3 4 5
1 2 3 4 5
Reserve for port80 card use for FCS in factory side. 10/17
WLAN (Halt mini Card) D E G _ F R AME# R 4 77 1 2 0_0402_5% L P C _ L FRAME# 12,33,35,36
D E B U G _AD3 R 4 78 1 2 0_0402_5% L P C _LAD3
D E B U G _AD2 R 4 79 1 2 0_0402_5% L P C _LAD2
+ 3 V _WLAN + 1.5VS D E B U G _AD1 R 4 80 1 2 0_0402_5% L P C _LAD1
D E B U G _AD0 R 4 81 1 2 0_0402_5% L P C _LAD0
L P C _LAD[0..3] 12,33,35,36
P C I _ RST#_R R 4 82 1 2 0_0402_5%
P C I _RST# 15,30
0.01U_0402_16V7K
0 .1U_0402_16V4Z
4 .7U_0805_10V4Z
0.01U_0402_16V7K
0 .1U_0402_16V4Z
4 .7U_0805_10V4Z
C 546
C 547
C 548
C 549
C 550
C 551
1 1 1 1 1 1
+ 3 V _ WLAN
JP7 C ONN@ 2A
2 2 2 2 2 2 P C I E _ W AKE# 1 2
14,31 P C I E _ W AKE# 1 2
A 3 4 0.5A A
2009/04/10 HP DB-3 3 4
5 6 + 1.5VS
5 6 D E G _ F R AME#
13 C L K R E Q _WLAN# 7 8
7 8 D E B U G _AD3
9 10
9 10
Close to JP7 13 C L K _ P C I E _MCARD# C L K _ P C I E _MCARD# 11
11 12
12 D E B U G _AD2
13 C L K _ P C I E _MCARD C L K _ P C I E _MCARD 13 14 D E B U G _AD1
13 14 D E B U G _AD0
15 16
P C I _ RST#_R 15 16
17 18
C L K _ P C I _DEBUG 17 18 X M I T_D_OFF#
15 C L K _ P C I _DEBUG 19 20
19 20
21 22 P L T_RST# 4,12,15,20,26,31,33
+ 3 VALW R 485 1 21 22
13 P C I E_PRX_DTX_N4 2 0_0402_5% P C I E _ C_RXN4 23 24
R 486 1 23 24
13 P C IE_PRX_DTX_P4 2 0_0402_5% P C I E _C_RXP4 25 26
27 25 26 28
27 28
29 30
29 30
1 10K_0402_5% 1 13 P C I E _PTX_C_DRX_N4 31 32
31 32
R 487
2008/12/12 HP 33 34
13 P C I E_PTX_C_DRX_P4 33 34
C 910 @ 35 36
2009/05/02 HP SI-1 0.1U_0402_10V6K + 3 V _WLAN 35 36 2008/12/12 HP
37 38
@ 2 39 37 38 40
2
39 40
3
S
41 42
1 2
G
2 43 41 42 44 W L _ LED#
35 M C 2 _ D ISABLE + 3 V _WLAN 43 44 W L _ LED# 33
R 488 220K_0402_1% 13 C L _ CLK C L _ CLK R 489 1 2 0_0402_5% C L _ C LK_R 45 46
C L _ DATA R 490 1 2 0_0402_5% C L _ D ATA_R 47 45 46 48
13 C L _ DATA 47 48
Q 24 13 C L _RST# C L _ RST# R 491 1 2 0_0402_5% C L _ RST#_R 49 50
SI2305ADS-T1-GE3_SOT23-3
D 49 50
5W T P C12 T 67 51 52
1
51 52
53 54
GND1 GND2
MOLEX_67910-5700
X M I T_D_OFF# 2 1 W L A N _ T R A N SMIT_OFF# 15
D 15 C H 751H-40PT_SOD323-2
Add to prevent leakage issue.
B B
WWAN (Full mini Card)

+ 3 V _ W WAN + 3 V _ W WAN
2009/05/13 HP SI-1
+ 3 V _ W W AN
C 566
39P_0402_50V8J
C 567
39P_0402_50V8J
C 568
39P_0402_50V8J
C 563
0.01U_0402_16V7K
C 564
0 .1U_0402_16V4Z
C 565
4 .7U_0805_10V4Z
1 1 1 1 1 1
JP9 C ONN@ 2.5A
1 2 2008/12/12 HP
1 2
3 4
3 4 2 2 2 2 2 2
5 6
5 6 U I M_ PWR
7 8
7 8 U I M _ DATA
9 10
2008/12/12 HP 9 10 U I M _ CLK
11 12
11 12 U I M _ RST
13 14
13 14 U I M _ VPP
15
15 16
16 Close to JP9
T68 17 18
19 17 18 20 M _ W X MIT_OFF#
T69 19 20
21 22
21 22
C 23 24 C
25 23 24 26 W W A N _ D E T#
25 26 W W A N _ D E T# 15
27 28
29 27 28 30 2009/04/10 HP DB-3 U20 @
31 29 30 32 1 6
31 32 CH1 CH4
33 34
33 34 + 3 VALW
35 36 U S B 20_N9 15 2 5 + 3 V _ W WAN
35 36 Vn Vp
37 38 U S B20_P9 15
39 37 38 40 3 4
41 39 40 42 W W _ L E D# CH2 CH3
+ 3 V _ W WAN 41 42 W W _ L E D# 33 + 3 V _ W W AN
43 44 S D I O (BR) NUP4301MR6T1 TSOP-6
45 43 44 46
45 46
47 48
1
49 47 48 50 D AN217GT146_SC59-3
49 50 @ R 502 2009/03/08 HP DB-3 J P 10 C ONN@
T70 51 52 3
51 52 10K_0402_5% U I M_ PWR
4 1 1
U I M _ VPP GND VCC U I M _ RST
53 54 5 2 2
GND1 GND2 U I M _ DATA VPP RST U I M _ CLK
6 3
2
F O X C O N N AS0B226-S40N-7F 52P 2009/04/24 HP SI-1 7 I/O CLK D16 @

DET 1
C 569
18P_0402_50V8J
3
S
R 1186 Q 84
SI2305ADS-T1-GE3_SOT23-3
4 .7U_0805_10V4Z
0 .1U_0402_16V4Z
G
35 M C 1 _ D ISABLE 1 2 2 @
2
C 570
C 571
220K_0402_1% 8 1 1
GND
9
1
GND
1
@ R 504
D
1
C 9 50 @ + 3 V _ W W AN + 3VS 47K_0402_5% 2 2
0.1U_0402_10V6K
2
2
T A I T W_PMPAT6-06GLBS7N14N0
+ 3 V ALW 7W 1 @ 2 U I M_ PWR
D17 2.5A R 1172 0_0805_5%
15,33 W W A N _ T R A N S M IT_OFF# 1 2 M _ W X MIT_OFF#
D D
C H 751H-40PT_SOD323-2

WLAN&WWAN
1 2 3 4 5
1 2 3 4 5
SATA HDD CONN. SATA ODD CONN.
P lace caps. near JODD1 C ONN@

P lace caps. near
A HDD CONN. ODD CONN. A
J HDD1 C O NN@ 1
GND S A TA_PTX_C_DRX_P1 0.01U_0402_16V7K 2 C 2 02 S ATA_PTX_DRX_P1
23 1 2 1 S ATA_PTX_DRX_P1 12
PTH GND S A TA_PTX_C_DRX_P0 0.01U_0402_16V7K TX+
24 2 1 2 C 1 86 S ATA_PTX_DRX_P0
S ATA_PTX_DRX_P0 12 3 S A T A_PTX_C_DRX_N1 0.01U_0402_16V7K 1 2 C 2 03 S A TA_PTX_DRX_N1
S A TA_PTX_DRX_N1 12
PTH A+ S A T A_PTX_C_DRX_N0 0.01U_0402_16V7K TX-
3 1 2 C 1 87 S A TA_PTX_DRX_N0
S A TA_PTX_DRX_N0 12 4
A- GND S A T A_PRX_C_DTX_N1 0.01U_0402_16V7K 2 C 2 04 S A TA_PRX_DTX_N1
25 4 5 1 S A TA_PRX_DTX_N1 12
NPTH GND S A T A_PRX_C_DTX_N0 0.01U_0402_16V7K RX+
26 5 1 2 C 1 88 S A TA_PRX_DTX_N0
S A TA_PRX_DTX_N0 12 6 S A TA_PRX_C_DTX_P1 0.01U_0402_16V7K 1 2 C 2 06 S ATA_PRX_DTX_P1
S ATA_PRX_DTX_P1 12
NPTH B- S A TA_PRX_C_DTX_P0 0.01U_0402_16V7K RX-
6 1 2 C 1 89 S ATA_PRX_DTX_P0
S ATA_PRX_DTX_P0 12 7
B+ GND
7
GND
8 R 179 1 @ 2 0_0402_5%
DP O D D _ DET# 15
8 17 9
3.3V 9 16 NPTH V5 10
3.3V NPTH 1.6AV5 + 5VS 1
C 210 @
10 11
3.3V + 5VS MD 0 .1U_0402_16V4Z
11 15 12
GND PTH GND + 5VS
12 14 13
GND
13
Near CONN side. PTH GND 2 Near CONN side.
GND
14
V5
1 0U_0805_10V4Z
1 0U_0805_10V4Z
0 .1U_0402_16V4Z
0 .1U_0402_16V4Z
0 .1U_0402_16V4Z
1.1A V5 15 T Y C O_1735491-3_NR
0 .1U_0402_16V4Z
1 U_0603_10V4Z
1 0U_0805_10V4Z
1 0U_0805_10V4Z
16 + 5 VS
V5
C 912
C 196
C 197
C 198
C 199
C 211
C 212
C 213
C 214
17 1 1 1 1 1 1 1 1 1
GND
18
RSVD 19
GND 20
V12 2 2 2 2 2 2 2 2 2
21
V12 22
V12
S A NTA_192601-1_NR
Placea caps. near HDD CONN.

Placea caps. near ODD CONN.
B B
NAND FLASH E-SATA Redriver + 3VS + 3 VS_1.5VS + 1.5VS
2009/05/12 HP SI-1 R 1216 1 @ 2 0_0603_5% R 1217 1 2 0_0603_5%

2009/06/30 HP SI-2
Change TI to Pericom TI & Pericom select
PI3EQX4951ST_PEND and 1.5V power
rail option 6/30
+ 3 VS_1.5VS
2009/09/10 HP PV
C 2009/04/24 SI-1 2009/04/24 SI-1 C
20
10
16
6
U 66 C984, C985 near JP29
VDD18
VDD18
VDD18
VDD18
12 S ATA_PTX_DRX_P4 0.01U_0402_16V7K 1 2 C 980 S A TA_PTX_DRX_P4_R 1 15 S A T A_PTX_C_DRX_P4_R C 984 1 2 0.01U_0402_16V7K S A TA_PTX_C_DRX_P4
AI+ AO+ S A T A_PTX_C_DRX_P4 32
12 S A TA_PTX_DRX_N4 0.01U_0402_16V7K 1 2 C 981 S A T A_PTX_DRX_N4_R 2 50mA 14 S A T A _PTX_C_DRX_N4_R C 985 1 2 0.01U_0402_16V7K S A T A_PTX_C_DRX_N4

AI- AO- S A T A_PTX_C_DRX_N4 32
S A TA_PRX_C_DTX_P4 0.01U_0402_16V7K 1 2 C 986 S A T A_PRX_C_DTX_P4_R 11 5 S A TA_PRX_DTX_P4_R C 982 1 2 0.01U_0402_16V7K
32 S A TA_PRX_C_DTX_P4 BI+ BO+ S A TA_PRX_DTX_P4 12
S A T A_PRX_C_DTX_N4 0.01U_0402_16V7K 1 2 C 987 S A T A _PRX_C_DTX_N4_R 12 4 S A T A_PRX_DTX_N4_R C 983 1 2 0.01U_0402_16V7K
32 S A T A_PRX_C_DTX_N4 BI- BO- S A TA_PRX_DTX_N4 12
+ 3 VS_1.5VS R 1203 1 2 4.7K_0402_5% 7 C982, C983 near U4

EN
17
MODE
GND / A_EN#
GND / B_EN#
R 1201 1 2 4.7K_0402_5% 8
GND / A_EM
GND / A_EQ
B_EM / B_EQ
HEATGND
R 1202 1 2 4.7K_0402_5% 9
A_EM / B_EM
R 1250 1 @ 2 4.7K_0402_5%
2009/08/30 HP PV
R 1251 1 @ 2 4.7K_0402_5%
13
18
19
21
P I2EQX4951SLZDEX_TQFN20_4X4
+ 3 VS_1.5VS
D Place caps. near U66 D

1 U_0603_10V4Z
C 988
0 .1U_0402_16V4Z
C 989
0.01U_0402_16V7K
C 990
1 1 1
2 2 2

2009/02/26 HP DB-2
NAND/HDD/ODD/E-SATA Redriver
1 2 3 4 5
1 2 3 4 5
+ 3VS
Layout Note: Place close to R5C835 Layout Note: Place close to R5C835
SD,MMC,MS,XD muti-function pin define
and Shield GND for SDCLK_MSCLK and Shield GND for SD_CLK MDIO SD Card MMC Card MS Card XD Card
10U_0805_10V4Z
0.01U_0402_16V7K
0.01U_0402_16V7K
0.01U_0402_16V7K
0.01U_0402_16V7K
U21
15 P C I _ AD[0..31] PIN Name PIN Name PIN Name PIN Name PIN Name
C 591
C 592
C 593
C 594
C 595
P C I _ AD31 121 6 1 1 1 1 1
AD31 VCC_PCI3V
P C I _ AD30 122
AD30 2.5mA VCC_PCI3V
23 MDIO00 SDCD# MMCCD# XDCD0#
P C I _ AD29 123 38
AD29 VCC_PCI3V C 596
P C I _ AD28 124 118 MDIO01 MSCD# XDCD1#
P C I _ AD27
P C I _ AD26
125
126
AD28
AD27 R5C835 VCC_PCI3V
92
2 2 2 2 2
+ 3VS
1 2 R 5C832XI
MDIO02 XDCE#
P C I _ AD25 AD26 49mA VCC_RIN 16P_0402_50V8J
127
1
P C I _ AD24 AD25
1
AD24 VCC_ROUT
11 MDIO03 SDWP# XDR/B#
0.01U_0402_16V7K
0 .1U_0402_16V4Z
0.01U_0402_16V7K
1 0U_0805_10V4Z
P C I _ AD23 4 33 X1
+ 3 VS AD23 VCC_ROUT
0.01U_0402_16V7K
0.01U_0402_16V7K
0.47U_0603_16V4Z
0.47U_0603_16V4Z
P C I _ AD22 5 59 1 1 1 1 24.576MHz_16P_3XG-24576-43E1 MDIO04 SDPWR0 MMCPWR MSPWR XDPWR
C L K_PCI_1394 P C I _ AD21 AD22 VCC_ROUT + 3 VS C 601
7 91 1 1 1 1
2
AD21 VCC_ROUT
P C I _ AD20 9 111 1 2 R 5C832XO MDIO05 SDPWR1 XDWP#
1
AD20 VCC_ROUT
100K_0402_1%
R 514
A P C I _ AD19 10 A
AD19
1 2 2 2 2
0.01U_0402_16V7K
1 0U_0805_10V4Z
P C I _ AD18 12 0.2mA 79 16P_0402_50V8J MDIO06 SDLED# MMCLED# MSLED# XDLED#
AD18 VCC_3V 2 2 2 2
C 597
C 598
C 599
C 600
R 515 @ P C I _ AD17 13 1 1 2009/04/07 DB-3 Compal
AD17
C 602
C 603
C 604
C 605
10_0402_5% P C I _ AD16 14 10mA 54 MDIO07 MSEXTCK
P C I _ AD15 AD16 VCC_MD3V
27
2
P C I _ AD14 AD15 + 3 V _ PHY

28 97 MDIO08 SDCCMD MMCCMD MSBS XDWE#
2
C B S _ GRST# P C I _ AD13 AD14 AVCC_PHY3V 2 2

29
AD13 25.6mA AVCC_PHY3V
104
C 606
C 607
P C I _ AD12 30 108 MDIO09 SDCCLK MMCCLK MSCCLK XDRE#
P C I _ AD11 AD12 AVCC_PHY3V L23 + 3 V _ PHY
1 1 31
C 608 AD11 +SC_PWR M B K 2 0 12601YZF_2P
P C I _ AD10 32
AD10 2mA VCC_SC
90 MDIO10 SDCDAT0 MMCDAT0 MSCDAT0 XDCDAT0
1U_0603_10V6K C 609 @ P C I _ AD9 34 1 2
4.7P_0402_50V8C AD9 + 3VS
2 2
P C I _ AD8 36
AD8 MDIO11 SDCDAT1 MMCDAT1 MSCDAT1 XDCDAT1
0.01U_0402_16V7K
10U_0805_10V4Z
10U_0805_6.3V6M
0.01U_0402_16V7K
1000P_0402_25V8J
P C I _ AD7 39 110 I E EE1394_TPBIAS0
P C I _ AD6 AD7 TPBIAS0
40
AD6 GND 1 1 MDIO12 SDCDAT2 MMCDAT2 MSCDAT2 XDCDAT2
P C I _ AD5 41 107 I E EE1394_TPAP0 1 1 1
AD5 TPAP0 I E EE1394_TPAP0 31
P C I _ AD4 42 106 I E E E1394_TPAN0 MDIO13 SDCDAT3 MMCDAT3 MSCDAT3 XDCDAT3
AD4 TPAN0 I E E E1394_TPAN0 31
P C I _ AD3 43
AD3 GND 2 2
P C I _ AD2 44 103 I E EE1394_TPBP0 MDIO14 MMCDAT4 XDCDAT4
AD2 TPBP0 I E EE1394_TPBP0 31 2 2 2
C 610
C 611
2008/12/12 HP P C I _ AD1 45 102 I E E E1394_TPBN0 GND
AD1 TPBN0 I E E E1394_TPBN0 31
C 6 12
C 6 13
C 6 14
P C I _ AD0 46
AD0 MDIO15 MMCDAT5 XDCDAT5
70 S D _ C A R D _DET#
MDIO00 S D _ C A R D _DET# 31
15 P C I _ CBE3#
P C I _ CBE#3 2 69 M D IO01 T81 MDIO16 MMCDAT6 XDCDAT6
15 P C I _ CBE2#
P C I _ CBE#2 15 C/BE3# MDIO01 63 X D _CE# T82
Layout Note:
P C I _ CBE#1 C/BE2# MDIO02 SD_WP
15 P C I _ CBE1# 26
C/BE1# MDIO03
68 S D _ W P 31 Layout Note: Place these cap close to U21 MDIO17 MMCDAT7 XDCDAT7
15 P C I _ CBE0#
P C I _ CBE#0 37
C/BE0# MDIO04
67 S D P W R 0 _ M S P W R _XDPWR
S D P W R 0 _ M S P W R _XDPWR 31 GND Add GND shield for
66 X D W P# T83 MDIO18 XDCLE
MDIO05 3 I N 1_LED# 1394.and Same length
65 T84
MDIO06
MDIO07
64 as TPA+/-,TPB+/- MDIO19 XDALE
P C I _ P AR 25 62 S D _ M M C _CMD GND
15 P C I _ PAR PAR MDIO08 S D _ M M C _CMD 31
P C I _ F R AME# 16 60 S D C L K _ M MCCLK_R R 1048 1 2 33_0402_5%
15 P C I _ F R AME# FRAME# MDIO09 S D C L K _ MMCCLK 31
P C I _ T R DY# 18 58 S D D A T A 0_MSDATA0
15 P C I _ T R DY#
P C I _ I R D Y# 17
TRDY# MDIO10
57 S D D A T A 1_MSDATA1
S D D A T A 0_MSDATA0 31 GND SD,MMC for Cartier DIS and UMA
15 P C I _ I R D Y# IRDY# MDIO11 S D D A T A 1_MSDATA1 31
P C I _STOP# 21 56 S D D A T A 2_MSDATA2 Layout Note:
15 P C I _STOP# STOP# MDIO12 S D D A T A 2_MSDATA2 31
P C I _ D EVSEL# 19 55 S D D A T A 3_MSDATA3
P C I _ AD22 1 R 516 2
15 P C I _ D EVSEL#
C B S _ I DSEL 3
DEVSEL# MDIO13
53 M M C _D4
S D D A T A 3_MSDATA3 31 Add GND shield for
B IDSEL MDIO14 M M C _D4 31 B
100_0402_5%
15 P C I _ P ERR#
P C I _ P ERR# 22 52 M M C _D5
M M C _D5 31
SDCLK_MMCCLK,
P C I _ S ERR# PERR# MDIO15 M M C _D6
15,33,35 P C I _ S ERR# 24 51 M M C _D6 31 SDPWR0_MSPWR_XDPWR.
SERR# MDIO16 50 M M C _D7
MDIO17 M M C _D7 31
49 X D CLE T85
P C I _ REQ2# MDIO18 X DALE
15 P C I _REQ2# 120 48 T86
P C I _GNT2# REQ# MDIO19
Layout Note: Add GND shield. 15 P C I _GNT2# 119
GNT# S C V C C 5 EN# Layout Note: Shield GND for
83
2008/12/12 HP SCVCC5EN# S C V C C 3 EN#
84 CBS_CCLK_INTERNAL and CBS_CCLK
C L K_PCI_1394 117 SCVCC3EN#
15 C L K_PCI_1394 PCICLK
15,28 P C I _RST# 116
C B S _ GRST# 82 PCIRST# 95 R 5C832XI
R 520 1 @ GBRST# XI
2 10K_0402_5% 114 96 R 5C832XO
R 521 1 2 0_0402_5% 78 CLKRUN# XO
14,33,35,36 P M _ C L K RUN# PME#
R 522 1 2 10K_0402_5% P M E# 100
+ 3 VS REXT
99
Function set pin define
VREF
0.01U_0402_16V7K
S C _ R ST 89 UDIO3 UDIO4 UDIO5 Function
SCRST
1
C 615
10K_0402_1%
R 526
S C _ C LK R 1173 1 2 47_0402_5% S C _ C L K_R 88 76 SIRQ 1
SCCLK UDIO0/SRIRQ# SIRQ 12,33,35,36
2009/03/08 SI-1 Add R for RF S C _ D ATA 87 75 T P _ UDIO1 T87 Pull-down Pull-down Pull-up Disable MS,xD Card,serial ROM
S C _ C D# SCIO UDIO1 T P _ UDIO2
86 74 T88
SCSENSE SCCD# UDIO2 U D I O3
+SC_PWR 1 2 85
SCSENSE UDIO3
73
2
Pull-up Pull-up Pull-down Enable serial EEPROM
R 527 10K_0402_5% 72 U D I O4
2
UDIO4 U D I O5
UDIO5
71 Pull-up Pull-up Pull-up Ensable MS,xD Card,disable serial ROM
15 P C I _ PIRQE# 112 8
INTA# GND + 3VS
15 P C I _ PIRQG# 113
INTB# GND
20 Layout Note:
35 Please them close to U21.
R 530 1 GND
+ 3 VS 2 10K_0402_5% 77 47 U D I O5 R 517 1 2 100K_0402_5%
R 531 1 HWSPND# GND
2 100K_0402_5% 81 61 U D I O3 R 518 1 @ 2 10K_0402_5%
TEST GND U D I O4 R 519 1 @ 2 10K_0402_5%
80
GND 2009/02/24 Compal DB-2 for layout
98 93
AGND GND
101 94
AGND GND R 523 1 @
105 115 2 100K_0402_5%
109 AGND GND 128 R 524 1 2 10K_0402_5%
AGND GND R 525 1 2 10K_0402_5%
C C
R5C835-TQFP128P_TQFP128_14X14
D 69 1 2 1 N 4 1 48WSFL_SOD323-2
D 70 1 2 1 N 4 1 48WSFL_SOD323-2
270P_0402_50V7K
1
C 624
5.1K_0402_1%
R 534
D 71 1 2 1 N 4 1 48WSFL_SOD323-2 1
2009/02/24 Compal DB-2
+SC_PWR R 536 1 2 15K_0402_5% S C _ D ATA C 619 1 2 12P_0402_50V8J 2009/04/16 Compal DB-3 follow KAQ 00
2
2
R 962 1 2 15K_0402_5% S C _ R ST C 622 1 2 12P_0402_50V8J + 5VS + S C _ P WR

A P 2301GN-HF_SOT23-3 A P 2301GN-HF_SOT23-3 A P 2309GN-HF_SOT23-3
R 963 1 2 15K_0402_5% S C _ C LK C 623 1 2 12P_0402_50V8J Q79 Q81 Q82
3 1 1 3 3 1 + 3VS
1
1
56.2_0402_1%
R 5 37
56.2_0402_1%
R 5 38
2009/05/16 HP SI-1 2009/03/08 HP DB-3
0.1U_0402_10V6K
100K_0402_5%
0.1U_0402_10V6K
1
1
C 946
R 1162
C 947
Layout Note: 1 1
C 945 R 1161
Add GND shield for 1394.
2
0.1U_0402_10V6K 10K_0402_5%
2
2
2 2
SMART Card Connector
2
I E E E1394_TPBN0
I E EE1394_TPBP0 R 1163 1 2 0_0402_5%
I E E E1394_TPAN0
1
I E EE1394_TPAP0 D S C V C C 3 EN#
1
J P38 C ONN@ + S C _ P WR S C V C C 3 EN# 2
19 20 +SC_PWR G C 948 @
19 20
17 18 GND S Q 83 0.1U_0402_10V6K
3
1
17 18 2
56.2_0402_1%
R 544
56.2_0402_1%
R 545
15 16 S C _ R ST + 3 VS S S M3K7002F_SC59-3
D 15 16 D
13
13 14
14 GND + 5VS
11 12 S C _ C LK 1 1 R 1164 2
11 12 C 840 100K_0402_5%
9
9 10
10 S C _ D ATA GND
7 8 0 .1U_0402_16V4Z
2
7 8 S C V C C 5 EN#
5 6
5 6 S C _ C D# 2
3 4
1 3 4 2 I E EE1394_TPBIAS0
1 2
0.01U_0402_16V7K
0 .33U_0603_16V4Z
C 631
C 632
E-T_6900-Q10N-00R Layout Note: 1 1

Add GND shield
@
2 2
1394+2 in 1 Card
C u s t om L A -4 9 0 1 P 1 .0
1 2 3 4 5
1 2 3 4 5
AUDIO BOARD CONNECTOR (MALE) INT_KBD CONN. K S O[0..13]

35 K S O [0..13]
JP5 K S I[0..7]
35 K S I [0..7]
U S B 20_N4 1 2 + 3VS
15 U S B 20_N4 1 2
U S B20_P4 3 4
15 U S B20_P4 3 4
15 C P P E# 5 6 L I N E _ I N_SENSE 34
5 6
+ 5 VALW 7 8 D O C K _ HPS# 34
2009/07/21 HP SI-2 7 8
9 10 D O C K _ LINE_IN_L 34
P C I E _ W AKE# 9 10 J P 36 C O NN@ CP2 @ CP1 @
14,28 P C I E _ WAKE# 11 12 D O C K _ L I NE_IN_R 34
C L K REQ_EXP# 11 12 K SO11 K SO11 K S I_D_14
13 C L K REQ_EXP# 13 14 D L I NE_OUT_L 34 1 2 4 5 1 8
C L K _PCIE_EXP# 13 14 K S O0 1 2 K S O0 K S I_D_8 K S O9
A 13 C L K _PCIE_EXP# 15 16 D L I N E _OUT_R 34 3 4 3 6 2 7 A
C L K _ PCIE_EXP 15 16 2009/01/21 COMPAL EMI K S O2 3 4 K S O2 K S I_D_12 K S I7
13 C L K _PCIE_EXP 17 18 5 6 2 7 3 6
P C I E_PRX_DTX_N2 17 18 K S O5 5 6 K S O5 K S I_D_10 K S I_D_6
13 P C I E_PRX_DTX_N2 19 20 H D A _ B I T _ CLK_CODEC 12 7 8 1 8 4 5
P C IE_PRX_DTX_P2 19 20 K S I_D_14 7 8 K S I_D_14
13 P C IE_PRX_DTX_P2 21 22 H D A _ S D O U T _ CODEC 12 9 10
P C I E _PTX_C_DRX_N2 21 22 K S I_D_8 9 10 K S I_D_8 100P_1206_8P4C_50V8K 100P_1206_8P4C_50V8K
13 P C I E _PTX_C_DRX_N2 23 24 H D A _ S D IN0 12 11 12
P C I E_PTX_C_DRX_P2 23 24 K S I_D_12 11 12 K S I_D_12
13 P C I E_PTX_C_DRX_P2 25 26 H D A _ S Y N C _ C O D EC 12 13 14
S LP_S3# 25 26 K S I_D_10 13 14 K S I_D_10 CP3 @ CP4 @
14,35,37,38,40,42,43,44,48 S LP_S3# 27 28 H D A _ R S T # _CODEC 12 15 16
P L T_RST# 27 28 K S I_D_0 15 16 K S I_D_0 K SO11 K S I_D_11
4,12,15,20,26,28,33 P LT_RST# 29 30 H D A _ S P KR 12 17 18 4 5 1 8
29 30 K S I_D_4 17 18 K S I_D_4 K S O0 K S O1
31 32 19 20 3 6 2 7
31 32 K S I_D_2 19 20 K S I_D_2 K S O2 K SO10
+ 1.5VS 33 34 + 3 VALW 21 22 2 7 3 6
2009/05/02 HP SI-1 35 33 34 36 2009/05/02 HP SI-1 K S I_D_1 23 21 22 24 K S I_D_1 K S O5 K S O6
35 A _ SD# M U T E _ LED_CNTL 35 1 8 4 5
35 36 K S I_D_3 23 24 K S I_D_3
30 S D D A T A 0_MSDATA0 37 38 25 26
39 37 38 40 K S O3 27 25 26 28 K S O3 100P_1206_8P4C_50V8K 100P_1206_8P4C_50V8K
30 S D D A T A 1_MSDATA1 39 40 27 28
41 42 H D D _ H A L TLED K S O8 29 30 K S O8
30 S D D A T A 2_MSDATA2 41 42 H D D _ H A L TLED 12 29 30
43 44 S A T A_LED# K S O4 31 32 K S O4 CP5 @ CP6 @
30 S D D A T A 3_MSDATA3 43 44 S A T A_LED# 12,34 31 32
45 46 A M B E R _BATLED# K S O7 33 34 K S O7 K S O8 1 8 K S I_D_1 1 8
30 M M C _D4 45 46 A M B E R _BATLED# 35 33 34
47 48 A Q U A W H I T E_BATLED# K S O6 35 36 K S O6 K S O3 2 7 K S I_D_2 2 7
30 M M C _D5 47 48 A Q U A W H I T E_BATLED# 12,35 35 36
49 50 W L / BT_LED# K SO10 37 38 K SO10 K S I_D_9 3 6 K S I_D_0 3 6
30 M M C _D6 49 50 W L / B T_LED# 33 37 38
51 52 S T B_LED# K S O1 39 40 K S O1 K S I_D_3 4 5 K S I_D_4 4 5
30 M M C _D7 51 52 S T B _LED# 34 39 40
30 S D C L K _ MMCCLK 53 54 +3VL K S I_D_5 41 42 K S I_D_5
55 53 54 56 K S I_D_6 43 41 42 44 K S I_D_6 100P_1206_8P4C_50V8K 100P_1206_8P4C_50V8K
30 S D _ M M C _CMD 55 56 43 44
57 58 K S I7 45 46 K S I7
30 S D _ W P 57 58 I E E E1394_TPBN0 30 45 46
59 60 K S I_D_13 47 48 K S I_D_13 CP7 @
30 S D P W R 0 _ M S P W R _XDPWR 59 60 I E EE1394_TPBP0 30 47 48
61 62 K S I_D_11 49 50 K S I_D_11 K S I_D_5 1 8
30 S D _ C A R D _DET# 61 62 49 50
63 64 K S I_D_9 51 52 K S I_D_9 K S O7 2 7
63 64 I E E E1394_TPAN0 30 51 52
65 66 K S O9 53 54 K S O9 K S I_D_13 3 6
65 66 I E EE1394_TPAP0 30 53 54
+ 5VS 67 68 K SO12 55 56 K SO12 K S O4 4 5
67 68 K SO13 57 55 56 58 K SO13
57 58 100P_1206_8P4C_50V8K
59 60
59 60
69 70
GND GND R 1179 1 2 0_0402_5% 61 63
E&T_1000-F68E-04R GND1 GND3
62 64
C O NN@ GND2 GND4
H I R O S E FH12HP-30S-1SV 55 30P
B B
D24 D 23
2 K S I_D_0 2 K S I_D_3
K S I0 1 K S I3 1
3 K S I_D_8 3 K S I_D_11
D AP202U_SOT323-3 D AP202U_SOT323-3
D26 D 25
Power Button K S I1 1
2 K S I_D_1
K S I4 1
2 K S I_D_4
+3VL 3 K S I_D_9 3 K S I_D_12
D28 D 27
2 K S I_D_2 2 K S I_D_5
1
K S I2 1 K S I5 1
R 6 07 3 K S I_D_10 3 K S I_D_13
100K_0402_5%
S W1 @ + 3 V ALW D 29
2
1BT002-0121L_4P 2 K S I_D_6
3 1 O N / O F F# R 609 1 2 47_0402_5% K S I6 1
O N / O F F B T N _KBC# 35
3 K S I_D_14
4 2 1
R 610 1 @ 2 100K_0402_5% D AP202U_SOT323-3
C 712 2009/07/21 HP SI-2
5
6
1 U_0603_10V4Z D31 @
2 1 2
O N / O F F# 34 O N / O F F B TN# 14
C H 751H-40PT_SOD323-2
C C
R 1228 1 2 0_0402_5% P W R B T N _OUT# 34,35
CAP SWITCH BOARD. +3VL 2009/06/30 HP SI-2
1 2 L I D _ SW#
R 178 100K_0402_5%
+3VL + 3VS + VREG3_51125 2009/08/30 HP PV + VREG3_51125
1000P_0402_50V7K
2 1 C 837 1 2 0 .1U_0603_50V4Z
R 602 5.1K_0402_5%
R 603 5.1K_0402_5%
C 836
2009/01/21 COMPAL EMI
1
MDC 1.5 Conn. 2
J P37
1
2 1
4 3 + 3VS
6 4 3 5 C A P _ R ST_EC
35 C A P _ R ST_EC
2
J P 21 C ONN@ + 3VS 6 5 W L / BT_LED#
33 W L / BT_LED# 8 7
ACES_88020-12101_12P 8 7
10 9
1 2 12 10 9 11 C A P _ CLK
1 2 13,35 C A P _ CLK 12 11
12 H D A _ S D O U T _MDC H D A _ S D O U T_MDC 3 4 14 13 C A P _ DAT
3 4 13,35 C A P _ DAT 14 13
5 6 35 C A P _ INT 16 15 C A P _ INT
H D A_ SYN C _ MD C 7 5 6 8 18 16 15 17
12 H D A _ S Y N C _ M D C 7 8 18 17
1 2 H D A _ S D I N 1_MDC 9 10 20 19 S T B_LED#
12 H D A _ S D I N1 9 10 34 S T B_LED# 20 19
12 H D A _ R S T #_MDC R 605 33_0402_5% 11 12 R 606 1 2 0_0402_5% H D A _ B I T _CLK_MDC 12 O N / O F F# 22 21 O N / O F F#
11 12 22 21
1 10K_0402_5%
R 604
L I D _ SW# 24 23 L I D _ SW#
19,35 L I D _SW# 24 23
1 2
GND
GND
GND
GND
GND
GND
C 706 ACES 85203-12021 12P P1.0

@ 10P_0402_25V8K C ONN@
13
14
15
16
17
18
2
2009/01/21 HP
D + 3 VS D
C 703
1000P_0402_50V7K
C 704
0 .1U_0402_16V4Z
C 705
4 .7U_0805_10V4Z
1 1 1
@
2 2 2 S ecurity Classification Compal Secret Data Compal Electronics, Inc.
MDC/KBD/ON_OFF/CAP
1 2 3 4 5
1 2 3 4 5
USB CONN. ACCELEROMETER BT Connector

+ 3VS
ODM part# HP302DLTR8-MBD J P26
+ 5 V ALW + 5 V ALW U S B _ V C CA 70mA
1 + 3VAUX_BT
+ 3VS + 3 V S_ACL_IO 2
0 .1U_0402_16V4Z
10U_0603_6.3V6M
U S B 20_P8_R R 611 1 2 0_0402_5%
3 U S B 20_P8 15
C 723
C 724
U S B 2 0_N8_R R 612 1 2 0_0402_5%
4 U S B 20_N8 15
1
1 1 R 617
5 B T _LED 33
0_0603_5%
R 613 1 2 ACES_87212-05G0_5P
10K_0402_5% 2009/08/14 Compal DFB PV C ONN@
U29 2 2
2
1 8 W=100mils J P27
GND OUT
A 2 7 1 A
IN OUT 1
1 5 0U_B2_6.3VM_R35M
3 6 U S B 2 0_N0_R 2
IN OUT 2 + 3 V ALW + 3VAUX_BT
1000P_0402_50V7K
38 S L P_S4 S LP_S4 4 5 U S B 20_P0_R 3
EN# OC# 3
0 .1U_0402_16V4Z
1 1 4
4
C 7 15
C 7 16
G 5 4 7F2P81U_MSOP8 C 714 1 1 5 Q 33 SI2301CDS-T1-GE3_SOT23-3
C 7 13 + GND U31
6
GND
S
4 .7U_0805_10V4Z (2A,100mils ,Via NO.=4)
D
7 LIS302DL 3 1
2 @ GND
8
2 2 2 GND
C 717
C 718
+ 3 VS_ACL_IO 0.4mA 1
VDD_IO
1
C O N N @ S U Y I N 0 20133MR004S536ZL 4P 6 2
G
+ 3VS
2
1
VDD GND 4
GND R 614 R 1245
15 A C C E L _INT# 8 5 1 1
U S B _ V C CA U S B _ V C CB 9 INT 1 GND 10 10K_0402_5% 470_0402_5%
J4 INT 2 GND
2
1 2 12
2
U S B 2 0_N0_R U S B 20_P0_R SDO 2 2
4,9,10,11,13 S M B _DATA_S3 13
SDA / SDI / SDO
0 .1U_0402_16V4Z
1 0U_0805_10V4Z
P A D - S H O RT 2x2m R 1230 1 2 0_0402_5% 14
4,9,10,11,13 S M B _CLK_S3
1
SCL / SPC R 6 15 Q 93 D
3 + 3VS
R 6 19 2 1 10K_0402_5% 7 RSVD 11 1 2 2
+ 3VS CS RSVD 15 B T _ O FF
220K_0402_1% G
1 L52 @ 2 U S B 20_P0_R H P302DLTR8_LGA14_3X5 S S M 3K7002FU_SC70-3 S
3
15 U S B 20_P0 1 2 D33 @ Must be placed in the center of the system.
P J D L C05H_SOT23-3 L 2009/09/03 Compal PV
4 3 U S B 2 0_N0_R 2009/02/18 Compal DB-2 EMI
15 U S B 2 0_N0 4 3
WCM-2012-900T_4P
2009/07/21 Compal SI-2 EMI
1
1 2
R 1231 0_0402_5%
+ 5 V ALW + 5 V ALW U S B _ V C CB + 5 V ALW + 5 V ALW USB_VCCD
B B
2
1
R 616 R 1012
10K_0402_5% 10K_0402_5%
2009/08/14 Compal DFB PV
U 30 @ U 62 2009/08/14 Compal DFB PV
1
2
1 8 W=100mils J P 28 1 8 W=100mils J P39
GND OUT GND OUT
2 7 1 2 7 1
IN OUT 1 IN OUT 1
1 5 0U_B2_6.3VM_R35M
1 5 0U_B2_6.3VM_R35M
3 6 U S B 2 0_N1_R 2 3 6 U S B 2 0_N3_R 2
IN OUT 2 IN OUT 2
0 .1U_0402_16V4Z
1000P_0402_50V7K
0 .1U_0402_16V4Z
1000P_0402_50V7K
S LP_S4 4 5 U S B 20_P1_R 3 S LP_S4 4 5 U S B 20_P3_R 3
EN# OC# 4 3 EN# OC# 4 3
1 1 4 1 1 4
C 721
C 722
C 879
C 880
G 5 4 7F2P81U_MSOP8 C 720 1 1 5 G 5 4 7F2P81U_MSOP8 C 878 1 1 5
C 7 19 + 6 GND C 877 + 6 GND
4 .7U_0805_10V4Z GND 4 .7U_0805_10V4Z GND
2
(2A,100mils ,Via NO.=4) 7
GND 2
(2A,100mils ,Via NO.=4) 7
GND
8 8
2 2 2 GND 2 2 2 GND
C O N N @ S U Y I N 020133MR004S536ZL 4P C O N N @ S U Y I N 0 20133MR004S536ZL 4P
R 1232 1 2 0_0402_5%
R 1233 1 2 0_0402_5% U S B 2 0_N3_R U S B 20_P3_R
U S B 2 0_N1_R U S B 20_P1_R
3
2
3
1 L53 @ 2 U S B 20_P3_R
15 U S B20_P3 1 2
1 L54 @ 2 U S B 20_P1_R
15 U S B 20_P1 1 2
4 3 U S B 2 0_N3_R D 68 @
15 U S B 20_N3 4 3
4 3 U S B 2 0_N1_R D34 @ WCM-2012-900T_4P P J D LC05H_SOT23-3
15 U S B 20_N1 4 3
WCM-2012-900T_4P P J D LC05H_SOT23-3 2009/07/21 Compal SI-2 EMI 2009/02/18 Compal DB-2 EMI
2009/02/18 Compal DB-2 EMI
2009/07/21 Compal SI-2 EMI 1 2
1
1 2 R 1234 0_0402_5%
R 1235 0_0402_5% 1
C C
USB and E-SATA Combo CONN. + 5 VALW + 5 V ALW U S B _ V C CC

1
R 618
10K_0402_5%
2009/05/12 HP SI-1
U32
2
1 8 W=100mils J P 29
2 GND OUT 7 1 USB
IN OUT VBUS
1 5 0U_B2_6.3VM_R35M
3 6 U S B 2 0_N2_R 2
IN OUT D-
0 .1U_0402_16V4Z
1000P_0402_50V7K
S LP_S4 4 5 U S B 20_P2_R 3
EN# OC# 4 D+
1 1 GND
C 727
C 728
G 5 4 7F2P81U_MSOP8 1 1
C 725 + 5
4 .7U_0805_10V4Z S A TA_PTX_C_DRX_P4 GND
2
(2A,100mils ,Via NO.=4) 29 S A TA_PTX_C_DRX_P4 6
A+ ESATA
C 726 29 S A T A_PTX_C_DRX_N4 S A T A_PTX_C_DRX_N4 7
2 2 2 8 A-
S A T A_PRX_C_DTX_N4 GND
29 S A T A_PRX_C_DTX_N4 9
S A TA_PRX_C_DTX_P4 10 B-
29 S A TA_PRX_C_DTX_P4 B+
11
R 1236 1 GND
2 0_0402_5%
12
U S B 2 0_N2_R U S B 20_P2_R GND
13 16
GND Boss
14 17
2
1 L55 @ 2 U S B 20_P2_R 15 GND Boss

D 15 U S B20_P2 1 2 GND D
T A I W I _EU016-117CRL-TW
4 3 U S B 2 0_N2_R C ONN@
15 U S B 20_N2 4 3
WCM-2012-900T_4P D 36 @
P J D LC05H_SOT23-3
2009/07/21 Compal SI-2 EMI 20009/02/18 Compal DB-2 EMI
1 2
R 1237 0_0402_5%
1

USB/BT/E-SATA Conn/Acclerometer
1 2 3 4 5
1 2 3 4 5
LPC Debug Port TrackPoint CONN. T/P CONN.

+3VL
8 0 5 1 _RECOVER# R 6 32 1 2 100K_0402_5%
J P 24
B + _ D EBUG 1 2 + 5 VS + 5VS 2009/06/02 Compal SI-2 for DFB + 5 VS
+ 5VS 1 2
3 4 S P _ DATA 35
J P13 C ONN@ 3 4 J P 25
35 S P _ CLK 5 6 1 1
5 6 C 709 C 710
1 7 8 8 7
Ground 7 8 8 7 0 .1U_0402_16V4Z
15 C L K _ P CI_DB 2 9 10 35 T P _DATA 6 5
LPC_PCI_CLK 9 10 0 .1U_0402_16V4Z 6 5
3 11 12 35 T P _CLK 4 3
Ground 11 12 2 4 3 2
A
12,28,35,36 L P C _ L FRAME# 4 2 1 A
SIRQ LPC_FRAME# ACES_87153-08011 2 1
12,30,35,36 SIRQ 5
3
+V3S C O NN@ ACES_85203-04021
4,12,15,20,26,28,31 P L T_RST# 6
LPC_RESET# C ONN@
15,30,35 P C I _ S E RR# 7
+V3S
12,28,35,36 L P C _LAD0 8
LPC_AD0
12,28,35,36 L P C _LAD1 9
LPC_AD1 D32 @
12,28,35,36 L P C _LAD2 10
LPC_AD2 P J D LC05H_SOT23-3
12,28,35,36 L P C _LAD3 11
LPC_AD3 2009/02/18 Compal DB-2 EMI
12
VCC_3VA
35 8051TX 13
14 PWR_LED#
35 8051RX
1
8 0 5 1 _RECOVER# CAPS_LED#
35 8 0 5 1 _RECOVER# 15
16 NUM_LED#
42 D E B U G _ K B CRST VCC1_PWRGD
S P I _ CLK_JP 17
S P I _ CS0#_JP SPI_CLK
18
S P I _SI_JP SPI_CS#
19
S P I _SO_JP SPI_SI
20
S P I _HOLD#_0 SPI_SO + 3VS
21
35 S P I _CS1# 22
23
SPI_HOLD#
Reserved WLAN/WWAN/BT LED
24 Reserved
Reserved
1
R 9 53
ACES_87216-2404_24P 47K_0402_5%
2009/04/24 HP SI-1
2
2009/08/30 HP SI-2b
W L _ LED# R 1191 1 2 0_0402_5% W L / BT_LED#

28 W L _ LED# W L / B T_LED# 31
Finger Printer
3
Q 60B
2 N 7 002DWH_SOT363-6
+ 3 VALW 5
B 15,28 W W A N _ T R A N S M IT_OFF# B
FPR : Validity
6
Q 34 SI2301CDS-T1-GE3_SOT23-3 19mA 2009/06/02 Compal SI-2 for DFB W W _ L E D# R 1192 1 2 0_0402_5%
28 W W _ L E D#
J P 30
S
3 1 U S B 2 0 _ N1_PWR 2 1 Q 60A
D
2 1 2 N 7 002DWH_SOT363-6
15 U S B 20_N10 4 3 32 B T _LED 2
4 3
C 735
C 736
15 U S B20_P10 6 5
8 6 5 7
G
1 1
2
1
8 7
1
2009/06/30 HP SI-2 ACES_85203-04021 2008/12/17 Compal ME

0 .1U_0402_16V4Z
1 0U_0805_10V4Z
R 623 C O NN@
10K_0402_5% 2 2 + 5 VALW
D 37 B T _LED R 954 1 2 100K_0402_5%
4 2 U S B20_P10
2
VIN IO1
R 628 U S B 20_N10 3 1 W L _ LED R 955 1 @ 2 100K_0402_5%
220K_0402_1% IO2 GND
15 F PR_ O FF 1 2 CM1293A-02SR_SOT143-4
+ 3VS + 3 V ALW
TPM1.2 on board
C 7 30
0 .1U_0402_16V4Z
C 7 31
0 .1U_0402_16V4Z
C 7 32
0 .1U_0402_16V4Z
C 7 33
0 .1U_0402_16V4Z
BIOS ROM(16MB) C 729
1 2
22P_0402_50V8J
TPM_XTALI 1 1 1 1
+ 3VL
8MB SPI ROM Y6
1
C SPI ROM 2 2 2 2 C
1 8 Pin SPI ROM SCKET 2 1 R 620
20mils &U1 NC IN 10M_0402_5%
C 738 25mA U52 C O NN@ 3 4
0 .1U_0402_16V4Z 8 4 NC OUT
2
2 VCC VSS 3 2 .768KHZ_12.5PF_QTFM28-32768K1
S P I _ WP# 3
24
19
10
W
5
1 2 TPM_XTALO U33
20mils R 633 1 2 3.3K_0402_5%S P I _HOLD#_1 7 4 5@ W25Q64BVSSIG SOP 8P C 734 22P_0402_50V8J
VDD
VDD
VDD
VSB
+3VL HOLD L P C _LAD0 26
12,28,35,36 L P C _LAD0 LAD0
35 S P I _CS0# S P I _CS0# 1 L P C _LAD1 23 5mA 25mA
S 12,28,35,36 L P C _LAD1 LAD1
L P C _LAD2 20
12,28,35,36 L P C _LAD2 LAD2 + 3 VS
35 S P I _CLK S P I _CLK R 1246 1 2 15_0402_5% S P I _ CLK_ROM 6 L P C _LAD3 17 6 T P M_GPIO T89
C 12,28,35,36 L P C _LAD3 LAD3 GPIO
L P C _ L FRAME# 22 2 T P M_GPIO2 T90
12,28,35,36 L P C _ L FRAME# LFRAME# GPIO2
35 S P I _SI S P I_SI R 1247 1 2 15_0402_5% S P I _ SI_ROM 5 S P I _SO_R 2 1 2 P L T_RST# 16 Base I/O Address
D Q S P I _SO 35 4,12,15,20,26,28,31 P LT_RST# LRESET#
1
R 634 22_0402_5% 2008/12/12 HP 2009/08/30 HP PV L P C P D#_TPM 28 0 = 02Eh
6 4 M MX25L6405DZNI-12G WSON 8P 2009/02/20 HP DB-2 SIRQ LPCPD#
R1246, R1247 near U52 12,30,35,36 S I R Q 27
SERIRQ
1 =* 04Eh
S P I _CLK 15 C L K _ PCI_TPM 21 R 6 22
2009/09/17 HP SI-2b LCLK R 6 25 4.7K_0402_5%
1 2 1 @ 2 SL B 9635 T T 1.2 0_0402_5%
2
1
+ 3VS 10P_0402_50V8K @ C 737 R 624 10_0402_5% 15 8 1 2 1 2

R 1111 @ CLKRUN# TEST1 9 R 626 @
10_0402_5% TESTB1/BADD 4.7K_0402_5%
14,30,35,36 P M _ C L K RUN#
1
7
PP
2
R 627 @ 3
4.7K_0402_5% TPM_XTALO 14 NC 12
XTALO NC
1 1
2
TPM_XTALI 13 NC
C 913 @ XTALI/32K IN
1
10P_0402_50V8J 2009/06/02 Compal SI-2 for UMA
GND
GND
GND
GND
2
R 6 29 @
0_0402_5% + 3VS SLB 9635 TT 1.2_TSSOP28
25
18
11
4
2009/06/30 SI-2
2
D D
2008/12/18 Compal EMI 4.7K_0402_5% 1 2 R 1238 L P C P D#_TPM
2009/08/30 HP PV
S P I _HOLD#_0 1 2 S P I _HOLD#_1
R 637 0_0402_5% + 3VL 1 @ 2 S P I _CS0#
S P I _ CLK_JP 1 2 S P I _CLK R 1180 100K_0402_5%
R 638 15_0402_5% 2009/04/10 HP DB-3
S P I _SI_JP
R 639
1 2
15_0402_5%
S P I_SI S ecurity Classification Compal Secret Data Compal Electronics, Inc.
S P I _ CS0#_JP 1 2 S P I _CS0# 20mils 1 2 S P I _ WP# 1 2
R 640 0_0402_5%
+ 3VL
R 6 35 3.3K_0402_5% R 636 @ 0_0402_5%
FPR/BIOS/LPC DEBUG/LED/TPM/TP
S P I _SO_JP 1 2 S P I_SO Size D o c u m ent Number Rev
R 641 22_0402_5% 2009/09/17 HP SI-2b
1 2 3 4 5
1 2 3 4 5
VA
DOCK CONN. 184PIN DOCKING CONNECT 2009/02/06 Follow Dior
V A _ ON#
+ 3 V ALW
1
C 740
C 741
(1) PCI Express x1 channels 1
(2) PS/2 Inte rfaces D O C K _ ID R 645 1 2 10K_0402_5%
(2) USB 2.channels 1 1 + 5 VS R 644 C 739
(2) SATA Channels
(2) Display Port Channels VIN VA 1K_0402_5%
2
0 .1U_0402_16V4Z
2
(1) Serial Port L34
2 2
C 742
C 743
C 744
C 745
(1) Paralle l Port HCB2012KF-121T50_0805
0 .1U_0603_50V4Z
0 .1U_0603_50V4Z
10U_0805_10V4Z
0 .1U_0402_16V4Z
0 .1U_0402_16V4Z
0 .1U_0402_16V4Z
(1) Lin e In 1 2 O N / O F F # _ DOCK R 1241 1 2 0_0402_5% O N / O F F#
(1) Line Out O N / O F F# 31
(1) RJ45 (10/100/1000) 1 1 1 1
5A R 1242 1 @ 2 0_0402_5% P W R B T N _OUT#
(1) VGA P W R B T N _OUT# 31,35
A L51 A
(1) 2 LAN indicator LED's HCB2012KF-121T50_0805 2009/09/03 Compal
(1) Power Button
1 2 2 2 2 2
(1) I2C interface J P 32B
143 46 D CAD2
22 C A D _ B 143 46
DP_CEC DP_CEC 142 47 D P _ C E C2
142 47 D P _ C E C2
DPB_HPD 141 48 DPE_HPD
VA 22 D P B _ H P D 141 48 D P E _ H P D 20
J P 32A 14 S LP_S5# R 646 1 2 1K_0402_5% 140 49 O N / O F F # _ DOCK
A D P _ S IGNAL 140 49 V A _ ON# 2009/09/03 Compal 2008/12/06 follow UMA
A D P _ S IGNAL 139 50
2008/12/06 follow UMA 139 50
12A 190
P1 G1
189 D P B _ C T RLCLK 138
138 51
51 D P C _ C T R LCLK
D P B _ C T RLDATA 137 52 D P C _ C T R LDATA
136 137 52 53
D P B _AUX R 1207 136 53
1 2 0_0402_5% 135 54 0_0402_5% 1 2 R 1208 D P E _AUX
R 1209 135 54
188 1 D P B _AUX# 1 2 0_0402_5% 134 55 0_0402_5% 1 2 R 1210 D P E _AUX#
188 1 2009/06/30 SI-2 134 55 2009/06/30 SI-2
27 M D O3+ 187 2 M D O1+ 27 133 56
187 2 133 56
27 M D O3- 186 3 M D O1- 27 132 57
186 3 L PTSTB# 132 57 D _ D D C D A TA
185 4 36 L PTSTB# 131 58 D _ D D C D A TA 18
184 185 4 5 L P T A FD# 130 131 58 59 D_DDCCLK
27 M D O2+ 184 5 M D O0+ 27 36 L P T A FD# 130 59 D _ D D C C L K 18
183 6 36 L P T ERR# L P T ERR# 129 60
27 M D O2- 183 6 M D O0- 27 129 60 D _ V S Y N C 18
182 7 36 L P T ACK# L P T ACK# 128 61
182 7 128 61 D _ H S Y N C 18
36 L P T B U SY L P T B U SY 127 62
L P TPE 126 127 62 63 R _ D O C K _ RED R 947 1 2 0_0402_5% D O C K _ R ED
36 L P TPE 126 63
D E T E CT 181 8 36 L P TSLCT L P TSLCT 125 64
181 8 L E D _ L I N K_LAN_DOCK# 27 125 64
180 9 L P D7 124 65 R _ D O C K _ GRN R 948 1 2 0_0402_5% D O C K _ G RN
180 9 L A N _ACT# 26,27 36 L P D7 124 65
+ 5VS 179 10 + 5 VS L P D6 123 66 R _ D O C K _BLU R 949 1 2 0_0402_5% D O C K _ BLU
179 10 2009/01/22 HP DB-2 36 L P D6 123 66
178 11 L P D5 122 67
178 11 36 L P D5 122 67
2009/02/06 HP DB-2 177 12 2009/02/06 HP DB-2 L P D4 121 68 DCD#1
177 12 36 L P D4 121 68 D C D # 1 36
176 13 L P D3 120 69 R I #1
176 13 36 L P D3 120 69 R I #1 36
175 14 L P D2 119 70 D T R#1
175 14 36 L P D2 119 70 D T R #1 36
174 15 L P D1 118 71 C T S#1
174 15 36 L P D1 118 71 C T S#1 36
173 16 L P D0 117 72 R T S#1
173 16 36 L P D0 117 72 R T S#1 36
172 17 L P T SLCTIN# 116 73 D S R #1
172 17 36 L P T SLCTIN# 116 73 D S R #1 36
171 18 L P TINIT# 115 74 TXD1
171 18 36 L P TINIT# 115 74 T XD1 36
170 19 S T B _LED#_R 114 75 R X D1
B 170 19 U S B 20_N11 15 114 75 R X D1 36 B
169 20 113 76 SER_SHD
169 20 U S B20_P11 15 12,31 S A T A_LED# 113 76 S E R _ S H D 36
168 21 D O C K _ ID 112 77
168 21 27 D O C K _ ID 112 77 D O C K _ ID0 15
167 22 I S O _ PREP# 111 78
167 22 15 I S O _ PREP# 111 78 D O C K _ ID1 15
166 23 110 79
166 23 110 79 2009/01/20 follow Dior DIS
165 24 12 S ATA_PTX_DRX_P5 109 80
165 24 109 80 K B D _ D ATA
164 25 12 S A TA_PTX_DRX_N5 108 81 K B D _ D ATA 35
164 25 108 81 K B D _ CLK
163 26 107 82 K B D _ CLK 35
163 26 107 82 P S 2 _DATA
162 27 12 S ATA_PRX_DTX_P5 106 83 P S 2 _DATA 35
161 162 27 28 105 106 83 84 P S 2 _CLK
161 28 2009/02/06 HP DB-2 12 S A TA_PRX_DTX_N5 105 84 P S 2 _CLK 35
160 29 104 85 L I N E _ I N _SENSE 31
159 160 29 30 103 104 85 86 D O C K _ HPS#
2009/01/22 HP DB-2 159 30 2009/01/22 HP DB-2 15 U S B 20_N13 103 86 D O C K _ H PS# 31
22 D P B_TXP0 158 31 D P E_TXP0 21 15 U S B20_P13 102 87
157 158 31 32 101 102 87 88
22 D P B _TXN0 157 32 D P E_TXN0 21 101 88 D O C K _ L INE_IN_L 31
156 33 12 S ATA_PTX_DRX_P2 100 89 D O C K _ L I NE_IN_R 31
156 33 100 89
22 D P B_TXP1 155 34 D P E_TXP1 21 12 S A TA_PTX_DRX_N2 99 90
154 155 34 35 98 99 90 91 D L I N E_OUT_L
22 D P B _TXN1 154 35 D P E_TXN1 21 98 91 D L I N E_OUT_L 31
153 36 97 92 D L I N E _OUT_R
Quick SW 152
153 36
37
GPU 12 S ATA_PRX_DTX_P2
96
97 92
93
D L I N E _ OUT_R 31
22 D P B_TXP2 152 37 D P E_TXP2 21 12 S A TA_PRX_DTX_N2 96 93
22 D P B _TXN2 151 38 2009/02/06 HP DB-2 95 94 D E T E CT
151 38 D P E_TXN2 21 95 94
150 39
149 150 39 40
22 D P B_TXP3 149 40 D P E_TXP3 21
22 D P B _TXN3 148 41 D P E_TXN3 21
147 148 41 42
D P B _AUX 146 147 42 43 D P E _AUX 192 191
22 D P B _ AUX 146 43 D P E _AUX 21 G2 G1
D P B _AUX# 145 44 D P E _AUX# 194 193
22 D P B _AUX# 145 44 D P E _AUX# 21 G4 G3
144 45 196 195
144 45 G6 G5
198 197
2008/12/11 nVidia 2008/12/11 nVidia G8 G7
200 199
FOX_QL0094L-D26601-8H G10 G9
FOX_QL0094L-D26601-8H
C 2008/12/18 nVidia + 3 VS C
D P E _AUX# R 651 1 @ 2 100K_0402_5% D O C K _ R ED R 950 1 2 150_0402_1%

D P E _AUX R 652 1 @ 2 100K_0402_5% + 5 VALW D O C K _ G RN R 951 1 2 150_0402_1%
D P B _AUX# R 653 1 @ 2 100K_0402_5% D O C K _ BLU R 952 1 2 150_0402_1%
D P B _AUX R 654 1 @ 2 100K_0402_5%
1
ADD by HP 2008/10/17
R 1145
10K_0402_5%
2
2009/09/03 reserve for auto power on/off when dock 2009/02/06 Follow Dior D O C K _ R ED C 766 1 2 @ 0 .1U_0402_16V4Z
S T B _LED#_R D O C K _ G RN C 767 1 2 @ 0 .1U_0402_16V4Z
+ 3 V ALW D O C K _ BLU C 768 1 2 @ 0 .1U_0402_16V4Z
1
D
O N / O F F# 31 S T B _LED# S T B_LED# 2 Q75
1
G 2N7002H_SOT23-3
@ R 1240 S
3
10K_0402_5%
3
@
2
Q 94B DPB_HPD R 1211 1 2 100K_0402_5%

5 D M N 6 6D0LDW-7_SOT363-6 DPE_HPD R 1212 1 2 100K_0402_5%
1 2009/06/30 SI-2
4
@ C 694 O N / O F F # _ DOCK
0.1U_0402_10V6K U 35 U36 U37
6
2
1 6 D O C K _ ID 1 6 D O C K _ ID 1 6 D O C K _ ID
18 V G A _ R ED NO IN + 3VS 18 V G A _ GRN NO IN + 3 VS 18 V G A _BLU NO IN + 3 VS
C 769 C 770 C 7 71
I S O _ PREP# 2
@ Q 94A 2 5 2 1 2 5 2 1 2 5 2 1
D M N 66D0LDW-7_SOT363-6 GND VCC GND VCC GND VCC
1
0 .1U_0402_16V4Z 0 .1U_0402_16V4Z 0 .1U_0402_16V4Z

D D
D O C K _ R ED 3 4 D O C K _ G RN 3 4 D O C K _ BLU 3 4
NC COM R E D _ R 18 NC COM G R E E N _R 18 NC COM B L U E _R 18
2009/09/03 Compal
TS5A3157_SC70-6 TS5A3157_SC70-6 TS5A3157_SC70-6
IN NC<-->COM NO<-->COM S ecurity Classification Compal Secret Data Compal Electronics, Inc.
L ON OFF
DOCK CONN
H OFF ON DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
C u s t om L A -4 9 0 1 P 1 .0
1 2 3 4 5
1 2 3 4 5
+ 3VL System Board ID Detect Q 12A

+ 3VL
2 N 7002DWH_SOT363-6
+3VL + 3 V S_EC 6 1
1
R P 16 2009/02/20 Compal DB-2 layout R 669 1 @ 2 0_0402_5% @
8 1 K S I1 1 2 + 3VS R 670 1 @ 2 0_0402_5% R 1200 @
7 2 K S I0 R 6 71 0_0402_5% 10K_0402_5%
2
0 .1U_0402_16V4Z
0 .1U_0402_16V4Z
0 .1U_0402_16V4Z
0 .1U_0402_16V4Z
4 .7U_0805_10V4Z
0 .1U_0402_16V4Z
6 3 K S I3
C 773
C 774
C 775
C 776
C 777
C 778
5 4 K S I2 1 1 1 1 1 1 R 672 1 @ 2 0_0402_5%
2
R 673 1 @ 2 0_0402_5%
6
1 0K_0804_8P4R_5%
K S I3 2009/02/06 HP DB-2 3 4
R P 18 2 2 2 2 2 2 K S I2 2009/08/30 HP PV @
1 8 K S I7 K S I1 Q 12B @ 2 A D P _ EN
2 7 K S I6 K S I0 2 N 7002DWH_SOT363-6 Q 85A
5
3 6 K S I5 2 N 7 002DWH_SOT363-6
1
3
A 4 5 K S I4 A
1
106
119
1 0K_0804_8P4R_5% 2009/02/06 HP DB-2 @ Q 85B
39
58
84
14
49
U39 @ R 990 2 N 7 002DWH_SOT363-6 5 A Q U A W H I T E_BATLED#
128 15 C 779 1 2 4 .7U_0805_10V4Z 47K_0402_5%
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC2
+ 5 VS 33 S P I_SI FLDATAOUT CAP
127
4
12 K B C _ S PI_SI_R HSTDATAOUT/GPIO45
1 2 S P I _ CS0#_EC 97 93
33 S P I _CS0# FLCS0# GPIO28 P M _SLP_M# 14,37,38
12 K B C _ S PI_CS0#_R R 1032 0_0402_5% 96 100mA 2mA 98 Q12B Q12A
HSTCS0#/GPIO44 GPIO29 S U S _ P W R _ ACK 14
R P 26 33 S P I_SO 95 99
FLDATAIN GPIO30 A C _ P R E SENT 14,20
1 8 T P _CLK 1 2 K B C _ S PI_SO_R 94 100 R 677 1 2 0_0402_5% BUILD PHASE R673 R672 R670 R669
12 K B C _ SPI_SO HSTDATAIN/GPIO43 GPIO31 M U T E _ LED_CNTL 31
2 7 T P _ DATA R 1033 22_0402_5% 126 2009/05/02 HP SI-1
GPIO32 P C I _ S E RR# 15,30,33
3 6 K B D _ CLK
31 K S O[0..13] FCS/MV
4 5 K B D _ D ATA K S O0 21 124 K B C _ P W R _ON to Pow er
KSO0 OUT0/(SCI) K B C _ P W R _ON 42
K S O1 20 125 A Q U A W H I T E_BATLED# DB1 X
KSO1 OUT1/IRQ8# A Q U A W H I T E_BATLED# 12,31
1 0K_0804_8P4R_5% K S O2 19 2008/04/14 EC R 1034 1 @ 2 0_0402_5%
KSO2 B A T SELB_A#
K S O3 18 123 R 1035 1 2 0_0402_5% 2008/12/12 HP DB2 X X
KSO3 CFETA/OUT7/nSMI F E T _A 41
General Purpose I/O Interface

K S O4 17 122 K B R ST# D40 1 2 C H 751H-40PT_SOD323-2
KSO4 OUT8/KBRST K B _ RST# 15
SMSC_1098-NU_TQFP-128P
Keyboard/Mouse Interface
R P 19 K S O5 16 121 FAN_ PWM DBx X X
KSO5 OUT9/PWM2 FAN_ PWM 4
1 8 S P _ CLK K S O6 13 120 to Pow er
KSO6 OUT10/PWM0 B A T _ P WM_OUT 40
2 7 S P _ DATA K S O7 12 118 C H G C T R L 40 to Pow er SI1 X
3 6 P S 2 _CLK K S O8 10 KSO7 PWM_CHRGCTL
KSO8
4 5 P S 2 _DATA K S O9 9 107 T H M _TRAVEL#
T H M _ TRAVEL# 39 SI2 X X
K SO10 8 KSO9 GPIO01 79
KSO10 GPIO02 O N / O F F B T N _KBC# 31
1 0K_0804_8P4R_5% K SO11 7 80 T118 SIx X X
K SO12 KSO11 GPIO03 2009/01/22 HP DB-2
6 81 S LP_S3# 14,31,37,38,40,42,43,44,48
K SO13 KSO12/GPIO00/KBRST GPIO04/KSO14
5
KSO13/GPIO18 GPIO05/KSO15
83 8 0 5 1 _ RECOVER# 33 PV X
31 K S I[0..7] 85 P M _ R SMRST# PVx X

GPIO07/PWM3 P M _ R SMRST# 14
K S I0 29 86 C R A C K _ BGA
KSI0 GPIO08/RXD C R A C K _ BGA 8,17
K S I1 28 87 G P IO9 T119
K S I0 K S I2 KSI1 GPIO09/TXD 2009/02/06 HP DB-2 X --> means installed
T143 27
KSI2 A B 2 A_DATA R 682 1
T144 K S I1 K S I3 26 88 2 0_0402_5% C A P _ DAT 13,31
K S I4 KSI3 GPIO11/AB2A_DATA A B 2 A_CLK R 683 1
25 89 2 0_0402_5% C A P _ CLK 13,31
K S I5 KSI4 GPIO12/AB2A_CLK R 684 1 2 0_0402_5%
24 90 C E L LS 40 to Pow er
KSI5 GPIO13/AB2B_DATA R 685 1
K S I6 23 91 2 0_0402_5% A _ S D# 31
B
K S I7 22 KSI6 GPIO14/AB2B_CLK 92 R 1101 1 2 0_0402_5% A D P _ DET# 2009/05/02 HP SI-1 B
KSI7 GPIO15/FAN_TACH1 2009/01/22 HP DB-2 A D P _ DET# 47
GPIO16/FAN_TACH2
101 T H M _ MAIN# 39 to Pow er
102 G A TEA20 15
T P _CLK GPIO17/A20M
33 T P _CLK 35
T P _ DATA IMCLK
33 T P _DATA 36 103 K B D _ CLK 34
S P _ CLK IMDAT GPIO20/PS2CLK
33 S P _ CLK 61 105 K B D _ D ATA 34
S P _ DATA KCLK GPIO21/PS2DAT P W R B T N _OUT# +3VL
33 S P _ DATA 62 4 P W R B T N _OUT# 31,34
P S 2 _CLK KDAT GPIO24/KSO16
34 P S 2_CLK 66 74 2009/07/22 HP SI-2 A D P _ P R ES 38,40,47 to Pow er
P S 2 _DATA 67 EMCLK ADP_PRES[CKT#2]/GPIO27/WK_SE05 2009/01/22 HP DB-2
34 P S 2 _DATA EMDAT
2009/05/02 HP SI-1
C L K _ P C I_KBC A B 1 A_DATA 2009/02/06 HP DB-2
AB1A_DATA
111
A B 1 A_CLK
A B 1 A _DATA 39 to Pow er K B R ST# R 1143 1 @
112 A B 1 A_CLK 39 to Pow er 2 10K_0402_5%
AB1A_CLK
Access Bus Interface
1
55 109 A B 1 B_DATA V C C 1 _ P W R GD R 965 1 2 10K_0402_5%

14,30,33,36 P M _ C L K RUN# CLKRUN# AB1B_DATA A B 1 B _DATA 39
57 110 A B 1 B_CLK
12,30,33,36 SIRQ SER_IRQ AB1B_CLK A B 1 B_CLK 39
R 966 C L K _ P C I_KBC 54
@ 10_0402_5%
15 C L K _ P C I_KBC
R U N S C I _ EC# 76 PCI_CLK Power Mgmt/SIRQ 73 R 687 1 2 0_0402_5%
15 R U N S C I _ EC# EC_SCI# GPIO25 C A P _ INT 31
2
108 EA# R 688 1 @ 2 1K_0402_5% +3VL

GPIO26/KSO17 R 691 1
12,28,33,36 L P C _LAD3 51 59 2 0_0402_5% A D P _ E N 47
C R A C K _ BGA R 697 1 2 100K_0402_5%
LAD[3] NC_CLOCKI 3 2 K_CLK
1 12,28,33,36 L P C _LAD2 50
LAD[2] 32KHZ_OUT/GPIO22/WK_SE01
75 P G D _ IN to Pow er
48 60 P G D _ IN R 692 1 2 220_0402_5% 2009/02/16 HP DB-2
12,28,33,36 L P C _LAD1 LAD[1] RESET_OUT#/GPIO06 P M _ P W R OK 46
Miscellaneous
C 849 46 LPC 78 PWR_GD 2009/02/16 HP DB-2 P G D _ IN R 711 1 @ 2 10K_0402_5%
12,28,33,36 L P C _LAD0 LAD[0] PWRGD P W R _ G D 12,37
@ 4.7P_0402_50V8C 77 2008/12/12 HP 2009/05/02 HP SI-1
2 52
Bus VCC1_RST#
38 R 1036 1 2 0_0402_5%
V C C 1 _ P W R GD 42,47
P M _ R SMRST# R 712 1 2 100K_0402_5%
12,28,33,36 L P C _ L FRAME# LFRAME# ADC_TO_PWM_OUT/GPIO19 2008/12/12 HP O CP 47 to Pow er
15,36 N P C I _ RST# 53
LRESET# T EST R 698 1
69 2 1K_0402_5% K B C _ P W R _ON R 701 1 2 10K_0402_5%
TEST PIN
L A T CH R 968 1 2 10K_0402_5%
C R Y1 70 116 R 1037 1 2 0_0402_5% 2008/04/14 EC
XTAL1 CFETB/GPIO10 F E T _B 41
C R Y2 71 113 F E T _A R 969 1 2 10K_0402_5%
XTAL2 BAT_LED# A M B E R _BATLED# 31
115 8051TX 33
PWR_LED#/8051TX F E T _B R 970 1
+VCC0 68 114 8051RX 33 2 10K_0402_5%
VCC0 FDD_LED#/8051RX R 702 1
C 2009/02/06 HP DB-2 2 100K_0402_5% +3VL C
41 B A T _ ALARM 1 G P IO9 R 1140 1 2 10K_0402_5%
Alarm [CKT#2]/GPIO36
3 2 .768KHZ_12.5PF_QTFM28-32768K1
12 K B C _ S P I_CLK_R 2 41 A C _ A D P _ PRES 40
HSTCLK/GPIO41 AC[CKT#2]/GPIO23 R 1194 1
33 S P I _CLK 3 42 2 300_0402_5% A D P _ A _ID 47
2009/02/06 HP DB-2
30 FLCLK ADC2/GPIO40 65
28 M C 2 _ D ISABLE GPIO39 Q/GPIO33 L A T CH 41
1
31 64 2008/12/12 HP
12 K B C _ S P I_CS1#_R HSTCS1#/GPIO42 GPIO34 L I D _ SW# 19,31
22P_0402_50V8J
22P_0402_50V8J
Y7 1 2 S P I _ CS1#_EC 32 63 R 706 1 2 0_0402_5% +3VL

IN
OUT
33 S P I _CS1# FLCS1# GPIO35 C A P _ R S T_EC 31

C 781
C 782
R 1039 0_0402_5% 33 40 +3VL R P 20

28 M C 1 _ D ISABLE GPIO38 AVCC
1 1 34 A B 1 A_DATA 1 8
14,38,45 P M _ SLP_LAN# GPIO37
AGND
AVSS
40 P M C 1 2 43 A B 1 A_CLK 2 7
VSS
VSS
VSS
VSS
VSS
VSS
VSS
R 1195 1 ADC1/GPIO46
2 300_0402_5%
NC
NC
47 O C P _ A_IN 44 A B 1 B_CLK 3 6
R 1196 300_0402_5% ADC_TO_PWM_IN A B 1 B_DATA 4 5
2 2 K B C1098-NU_VTQFP128_14X14
2
72
11
37
47
56
104
82
117
45
4 .7K_0804_8P4R_5%
2009/02/16 HP DB-2 2009/05/16 HP SI-1

2009/05/02 HP SI-1
+ R T C V CC
C 966 1 2 2200P_0402_50V7K AVSS C 967 1 2 2200P_0402_50V7K

P G D _ IN R 1204 1 2 1K_0402_5% V G ATE 14,46
1
C 968 1 2 2200P_0402_50V7K
2009/05/16 HP SI-1
R 7 22
0_0402_5%
2
+ V C C0
1
C 784
1 U_0603_10V4Z
C 785
0 .1U_0402_16V4Z
R 1197
1 1 0_0402_5%
R 729 @
2
D D
0_0402_5%
2
2 2

KBC1098
1 2 3 4 5
1 2 3 4 5
Parallel Port + 5VS
2
TO LPC47N217N
D43
C H 751H-40PT_SOD323-2
+ 3VS
1
DCD#1 R 1079 1 2 4.7K_0402_5%
+ 5 V S _PRN
R I #1 R 1080 1 2 4.7K_0402_5%
A L P T ERR# 1 R 7 32 2 C T S#1 R 1081 1 2 4.7K_0402_5% A
4.7K_0402_5% D S R #1 R 1082 1 2 4.7K_0402_5%
R X D1 R 7 36 1 2 1K_0402_5%
R P 22
L P T ACK# 1 8 U65
L P T B U SY 2 7 9 L P C _AD0
LAD0 L P C _LAD0 12,28,33,35
L P TPE 3 6 11 L P C _AD1
LAD1 L P C _LAD1 12,28,33,35
L P TSLCT 4 5 34 R X D1 R X D1 54 12 L P C _AD2
RXD1 LAD2 L P C _LAD2 12,28,33,35
TXD1 55 13 L P C _AD3
SERIAL I/F
34 TXD1 TXD1 LAD3 L P C _LAD3 12,28,33,35
4.7K_0804_8P4R_5% D S R #1 56
34 D S R #1 DSR1#
R P 23 R T S#1 1 14 L P C _ F RAME#
34 R T S#1 RTS1# LFRAME# L P C _ L FRAME# 12,28,33,35
L P D3 1 8 C T S#1 2 15 L P C _ DRQ#0
34 C T S#1 CTS1# LDRQ# L P C _ LDRQ#0 12
L P D2 2 7 D T R#1 3
LPC I/F
34 D T R #1 DTR1#
L P D1 3 6 34 R I #1 R I #1 4 16 N P C I _ RST#
RI1# PCI_RESET# N P C I _ RST# 15,35
L P D0 4 5 34 DCD#1 DCD#1 5 17 L P C P D#_SIO 2008/12/12 HP
DCD1# LPCPD# 2009/08/30 HP PV
4.7K_0804_8P4R_5% 18 P M _ C L K RUN# + 3 VS
CLKRUN# P M _ C L K RUN# 14,30,33,35
R P 24 19 C L K _ PCI_SIO
PCI_CLK C L K _ P CI_SIO 15
L P D7 1 8 34 L P TINIT# L P TINIT# 35 20 SIRQ
INIT# SER_IRQ SIRQ 12,30,33,35
L P D6 2 7 34 L P T SLCTIN# L P T SLCTIN# 36 6 S I O_PME# 1 2 + 3 VS L P C P D#_SIO R 1239 1 2 4.7K_0402_5%
L P D5 L P D0 SLCTIN# IO_PME# R 735 10K_0402_5%
3 6 34 L P D0 37
L P D4 4 5 L P D1 39 PD0 8 C L K_14M_SIO 2009/08/30 HP PV
34 L P D1 PD1 C L K_14M_SIO 13
34 L P D2 L P D2 40
PD2
CLOCK CLK14
4.7K_0804_8P4R_5% 34 L P D3 L P D3 41
PD3
PARALLEL I/F
R P 25 34 L P D4 L P D4 42 21 S I O_GPIO41
L P TINIT# L P D5 PD4 GPIO41 S I O_GPIO42
1 8 34 L P D5 43 22
L PTSTB# 2 7 L P D6 44 PD5 GPIO42 24 S I O_GPIO43
34 L P D6 PD6 GPIO43
L P T A FD# 3 6 34 L P D7 L P D7 45 25 S I O_GPIO44
GPIO
L P T SLCTIN# L P TSLCT PD7 GPIO44 S I O_GPIO45
4 5 34 L P TSLCT 47 26
L P TPE SLCT GPIO45 S I O_GPIO46
34 L P TPE 48 27
4.7K_0804_8P4R_5% L P T B U SY PE GPIO46 S E R _ S H D_GPIO47 @ SER_SHD
34 L P T B U SY 49 28 1 2 S E R _ S H D 34
L P T ACK# BUSY GPIO47 S I O_GPIO10 R 1189 0_0402_5%
34 L P T ACK# 50 29
L P T ERR# ACK# GPIO10 S Y S O PT
34 L P T ERR# 51 30
ERROR# GPIO11/SYSOPT
1
34 L P T A FD# L P T A FD# 52 31 S I O_GPIO12
B
L PTSTB# 53 ALF# GPIO12/IO_SMI# 32 S I O _IRQ
B
34 L PTSTB# STROBE# GPIO13/IRQIN1
33 R 1190
GPIO14/IRQIN2 34 S I O_GPIO23 10K_0402_5%
2009/06/30 SI-2 GPIO23
2
+ 3VS 7
R P 57 VTR 2009/04/24 SI-1
10
S I O_GPIO46 + 3 VS VCC
8 1 23
VCC
POWER EPAD
57
7 2 S I O_GPIO45 38
6 3 S I O_GPIO44 46 VCC
S I O_GPIO43 VCC
5 4
C 790
C 787
C 786
C 789
L P C 4 7 N 217N-ABZJ_QFN56_8X8
1 0K_0804_8P4R_5% 1 1 1 1
R P 58
0 .1U_0402_16V4Z
0 .1U_0402_16V4Z
0 .1U_0402_16V4Z
4 .7U_0805_10V4Z
8 1 S I O _IRQ
7 2 S I O_GPIO12 2 2 2 2
6 3
5 4 S I O_GPIO10
1 0K_0804_8P4R_5%
+ 3VS
R 1130 1 2 10K_0402_5% S I O_GPIO23
R 1131 1 2 10K_0402_5% S I O_GPIO41

C C
R 1132 1 2 10K_0402_5% S I O_GPIO42
R 1174 1 2 10K_0402_5% S Y S O PT
Base I/O Address 2009/03/23 Compal DB-3

0 = 02Eh
1 = 04Eh
C L K _ PCI_SIO C L K_14M_SIO
1
R 7 42 @ R 7 43 @
10_0402_5% 10_0402_5%
2
1 1
C 7 91 @ C 7 92 @
18P_0402_50V8J 10P_0402_25V8K
2 2
D D

SUPER I/O LPC47N217N-ABZJ
1 2 3 4 5
1 2 3 4 5
+ 3VS
R 744 1 2 1M_0402_5%
1
R 7 46
2008/12/12 HP + 5 V ALW 10K_0402_5%
R 7 47 1 2 3.3K_0402_5%
45 1 .5V_POK
2
8
+ 3 V ALW
R 7 48 1 2 76.8K_0402_1% R 749 1 2 10K_0402_5% 3 J2
P
+ 5VS +
1 1 2 2009/07/02 HP SI-1b
O V C C P _ EN 43
2 V R EF_51125 1 2 2 V R EF_393 2
-
G
+ 0.75VS R 7 51 1 2 11.5K_0402_1% R 750 34.8K_0402_1% U 4 1A S H O R T PADS
A L M 393DR_SO8 A
5
D 44 R 7 52 1 2 49.9K_0402_1%
1 2 1 2
VCC
14 M _ P W ROK + 3 VALW
R 7 53 3.3K_0402_5% 1
C H 751H-40PT_SOD323-2 IN1
1 4 V C C P _ 1 . 5 V SPWRGD 4
D45 C 793 2008/12/12 HP S LP_S3# OUT
2
GND
1000P_0402_50V7K IN2 U67
14,31,35,38,40,42,43,44,48 S LP_S3# 1 2 1 2
5
R 7 54 3.3K_0402_5% M C 7 4 V HC1G08DFT2G_SC70-5
C H 751H-40PT_SOD323-2 2
VCC
3
1 1
IN1 4
OUT P W R _ G D 12,35
C 794 2
GND
43 V C C P _ POK IN2
3300P_0402_25V7K
1
2
U 42 R 7 55
3
R 756 M C 7 4 V HC1G08DFT2G_SC70-5 4.99K_0402_1%
1 2
1M_0402_5% 1
2
2009/02/25 HP DB-2 @ C 999
0.1U_0402_25V4K
+ 5 V ALW V T T P W R GOOD 4
R 7 58 1 2 3.3K_0402_5%
48 N V V D D _ POK 2
1
2009/09/15 Compal ESD PV
R 7 61 1 2 49.9K_0402_1% R 7 59 1 2 10K_0402_5% 5 R 7 60
P
+ 3VS +
7 2.49K_0402_1%
2 V R EF_393 6 O
-
G
+ 1.05VS R 7 62 1 2 16.2K_0402_1% U 4 1B
2
L M 393DR_SO8
4
1
2008/12/12 HP 1
R 7 63 C 795
56.2K_0402_1% 3300P_0402_25V7K
2
2
B B
R 1041
R 1040 1 2 3.3K_0402_1% 1 2
44 1 . 8VS_POK
1M_0402_5%
R 1042 1 2 10.7K_0402_1% + 5 V ALW

+ 1.5VS
8
2009/02/25 HP DB-2 R 1043 1 2 10K_0402_5% 3 MDC STANDOFF Mini PCIE STANDOFF SATA STANDOFF
P
2009/07/21 HP SI-2 + 1
2 V R E F_393_R 2 O
G
1
2009/07/21 HP SI-2 - H13 H 21 H22 H 23 H24 H7

1
R 1044 C 897 U 3A H O L EA H O L EA H O L EA H O L EA H O L EA H O L EA
4
165K_0402_1% 3300P_0402_25V7K L M 3 93DR_SO8
2
2
1
H 15 H1 H2 H3 H4 H5 H 26
H O L EA H O L EA H O L EA H O L EA H O L EA H O L EA H O L EA
C C
1
H8 H9 H 10 H11
H O L EA H O L EA H O L EA H O L EA
2 V R EF_51125 2 V REF_51125 R 9 86 1 2 41.2K_0402_1%
1
1
R 987 C 863
71.5K_0402_1% 1000P_0402_25V8J + 3 VALW
2
2
H17 H 18 H19 H 20 H25

H O L EA H O L EA H O L EA H O L EA H O L EA
R 935 1 2 1M_0402_5%
1
+ 5 V ALW R 936
2008/12/12 HP 3.3K_0402_5%
Z Z Z1
2
8
U3B
R 9 37 1 2 3.3K_0402_5% R 938 1 2 10K_0402_5% 5
P
45 1 . 0 5VM_LAN_POK +
7 M _ P W R OK 14
R 9 39 1 O
+ 3VM 2 46.4K_0402_1% 2 V R E F_393_R 6
-
G
FM1 FM2 F M3 FM4

1
+1.05VM R 9 40 1 2 14.7K_0402_1% L M 393DR_SO8 1 1 1 1 PCB-MB

4
R 988
D 66 1K_0402_5%
R 9 41 1 2 3.3K_0402_5% 1 2
14,35,38 P M _SLP_M#
2
1 N 4 1 48WSFL_SOD323-2 D67
2 1 R 989 1 2 1M_0402_5%
D D
2009/02/06 HP DB-2
C H 751H-40PT_SOD323-2
1
C 864 1 2 0.068U_0402_10V6K
1
R 942 C 8 39
86.6K_0402_1% 3300P_0402_50V7K 2009/07/09 HP SI-1b
2
2

POK CKT
1 2 3 4 5
A B C D E
+1.05VM to +1.05VS Transfer +3VALW to +3VM Transfer Discharge circuit-2 for V-M
+ 3 V ALW Q 40 + 3VM
SI2301CDS-T1-GE3_SOT23-3
+ 1.05VM_LAN + 1.05VS
1.5A + 1.05VM + 3VM
D
3 1
Q57
0 .1U_0402_16V4Z
AO4430L_SO8 6A
1
C 8 00
0 .1U_0402_16V4Z
C 7 98
8 1
G
1 1
2
7 2 1 R 7 73 C 7 99
6 3 2009/05/07 HP SI-1 47K_0402_5% 1 0U_0805_10V4Z R 7 71 R 772
5 470_0402_5% 470_0402_5%
2 2
C 801
1 0U_0805_10V4Z
C 802
0 .1U_0402_16V4Z
C 804
1 0U_0805_10V4Z
C 978
3 3 0U_B2_2VM_R15M
1
2
2
1 1 1
4
1 + R 7 74 2009/04/13 Compal DB-3 1
3
1 2 L A N _EN#
@ 4.7K_0402_5%
2 2 R U NON 1 R 1178 2 2 2 Q 41B
0_0402_5% P M _SLP_M 2 L A N _EN# 5 2 N 7 002DWH_SOT363-6
1
2009/04/13 Compal DB-3 D Q 41A
14,35,45 P M _ SLP_LAN# 2 Q 43 2 N 7002DWH_SOT363-6
4
G 2N7002H_SOT23-3
S 2008/12/12 follow UMA
3
+3VALW to +3VS Transfer
B+ + 3 V ALW + 3VS
U 45
SI7326DN-T1-GE3_PAK1212-8-5 6.5A
+1.05VM_LAN to +1.05VM Transfer +1.5V to +1.5VS Transfer +1.5V to +VDD_MEM Transfer
1
1
2 + 1 .05VM_LAN +1.05VM
0 .1U_0402_16V4Z
10U_0603_6.3V6M
1 3
C 806
C 807
R 776 5 U55 B+ + 1.5V + V D D _MEM

1 1
330K_0402_5% C 805 SI7326DN-T1-GE3_PAK1212-8-5
10U_0603_6.3V6M 1 2.5A Q 77 3A
2
2 2 + 1.5V + 1.5VS AO4430L_SO8

2 2 3 8 1
R U NON 5 Q62 7 2
1
C 815
10U_0805_10V4Z
C 979
3 30U_B2_2VM_R15M
1 AO4430L_SO8 6 3
1
C 812
1 0U_0805_10V4Z
C 813
0 .1U_0402_16V4Z
C 935
10U_0805_10V6K
C 936
0.1U_0402_10V6K
C 937
0.1U_0402_10V6K
C 938
10U_0805_10V6K
1 8 1 1.5A 5
4
J3 + 7 2 R 1243
1 1 1 1 1 1
S H O R T P ADS R 777 R 778 6 3 330K_0402_5%
6 2
4
820K_0402_5% 470_0402_5% @ 5
2
2 2
2
2 2 2 2 2 2
C 843
10U_0805_10V6K
C 844
0.1U_0402_10V6K
C 845
0.1U_0402_10V6K
C 846
10U_0805_10V6K
1 2009/05/07 HP SI-1
4
C 808 1 1 1 1
2 2
S LP_S3 2 0.01U_0402_16V7K
Q 45A Q 58A
2 N 7002DWH_SOT363-6 2 2 N 7 002DWH_SOT363-6
1
6
R 943 1 2 6 1 2 2 R U NON 2 2
B+
1
330K_0402_5% 2009/02/18 Compal DB-2
Q 45B 2009/09/08 Compal PV
5 2 N 7 002DWH_SOT363-6 S LP_S3 2 R 1156 R 1170
2
35,40,47 A D P _ P RES
1
P M _SLP_M Q 95A 820K_0402_5% 10K_0402_5%
R 1047 2 N 7002DWH_SOT363-6
4
2
820K_0402_5%
3
3 2
1
Q 95B C 9 39
A D P _ P RES 5 2 N 7 002DWH_SOT363-6 0 .22U_0402_10V4Z
Q 58B
+5VALW to +5VS Transfer A D P _ P RES 5 2 N 7 002DWH_SOT363-6 2
4
4
+ 5 V ALW + 5VS
10/17 HP correct it
U 46 +3VL + 3VL + 3VL
SI7326DN-T1-GE3_PAK1212-8-5
4.5A
1
0 .1U_0402_16V4Z
1
3
C 809
5 1 1 R 957 R 779 R 780

1 C 810 100K_0402_5% 100K_0402_5% 100K_0402_5%
1 0U_0805_10V4Z
4
C 811
2
1 0U_0805_10V4Z 2 2
2 P M _SLP_M S LP_S4 S LP_S3
32 S L P_S4 7 S LP_S3
3 3
1
R U NON D D D
R U NON 7
14,35,37 P M _SLP_M# 2 14,45 S LP_S4# 2 14,31,35,37,40,42,43,44,48 S LP_S3# 2
G G G
S S S
3
1
1
Q47 Q 48 Q49
S S M 3K7002FU_SC70-3 S S M 3K7002FU_SC70-3 S S M 3 K7002FU_SC70-3
R 1013 R 1014 R 1015
100K_0402_5% 100K_0402_5% 100K_0402_5%
2
Discharge circuit-1
+ 3VS + 1 .5VS +1.5V + 5VS + 1 .8VS + 0.75VS
+ 1.05VS
1
1
1
1
R 783 R 786
R 781 R 782 470_0402_5% 470_0402_5% R 784 R 785 R 7 87
470_0402_5% 220_0402_5% 470_0402_5% 470_0402_5% 10_0402_5%
2
2
2
2
2009/06/30 SI-2
6
3
1
1
D D D D D
S LP_S3 2 Q 50 S LP_S3 2 Q 51 Q 52B S LP_S3 2 Q 53 S LP_S3 2 S LP_S3 2
G 2N7002H_SOT23-3 G 2N7002H_SOT23-3 S LP_S3 2 S LP_S4 5 2 N 7 002DWH_SOT363-6 G 2 N7002H_SOT23-3 G Q 54 G Q56
S S Q 52A S S S S M 3K7002FU_SC70-3 S S S M 3 K7002FU_SC70-3
3
3
4 4
2 N 7 002DWH_SOT363-6
1

DC/DC Circuits
A B C D E
1 2 3 4
ADP_SIGNAL
PJP1
3 5
GND1 SINGAL
4
GND2 VIN
6 PL1
GND_1 SMB3025500YA_2P
A
1 A
PWR1 AD P IN
7 1 2
GND_2
3
8
GND_3
100P_0402_50V8J
1000P_0402_50V7K
1
9 2 P C3
GND_4 PWR2
1
P C1
P C4
100P_0402_50V8J PR1
FOX_JPD113E-LB103-7F @15K_0402_5%
@ P D1 P C2
2
@PJSOT 24C_SOT23 1000P_0402_50V7K
2
VMB_A BATT_A
PJP2 PL2
1 SMB3025500YA_2P
1
2 1 2
2
3
3
4
4
1
5 2 1
5 P R2 1M_0402_1%
6
6 P C5 P C6
7
2
7 1000P_0402_50V7K 0.01U_0402_50V4Z
8
8
@SUYIN_200046GR008G102ZR_8P-T
100_0402_5%
100P_0402_50V8J
100P_0402_50V8J
1
1
1K_0402_5%
100_0402_5%
B B
1
1
P R6
P R3
P C7
P R5
P C8
P C9
100P_0402_50V8J
2
2
+3VL VL P R88
2
2
69.8K_0402_1%
1 2
1
PR4
100K_0402_5%
PR89 AB1A_DAT A 35
PQ29 100K_0402_1%
2
E
MMBT3906_SOT23-3 PD15
2
35 T HM_MAIN# B
2 BAV99WT 1G_SC70-3 AB1A_CLK 35
1
D C
PD16 PD17
1
2 BAV99WT 1G_SC70-3 BAV99WT 1G_SC70-3

G
1
S
3
PQ30
SSM3K7002FU_SC70-3 P R91 PR90 VL
220K_0402_5% 150K_0402_1% +3VL
2
PH1 under CPU botten side :

2
CPU thermal protection at 90 +-3 degree C

PR92
294K_0402_1%
(Need to be checked)
47 O C P_ADJ 1 2
C C
VMB_B BATT_B 2VREF_51125

P C N1 PL3
SMB3025500YA_2P
1 1 2 P R8
BATT+
470K_0402_1%
1
2 P R7 1 2 VL
SMD
1
3 1K_0402_5% P H1
SMC 100K_0603_1%_T SM1A104F4361RZ
B/I
4 1 2 Close to CPU
5 PC11 PC10
2
TS 1000P_0402_50V7K 0.01U_0402_50V4Z PR12 P R10
2
6 53.6K_0603_1% 100K_0402_5%
GND
1 2 EN0 42
8
100P_0402_50V8J
SUYIN_20163S-06G1-K
1
100_0402_5%
P
+
2
1
100_0402_5%
100P_0402_50V8J
1
O
1
1
PR16 D
PR14
PC28
PR15
P C12 6
-
G
PR11 PC29 19.1K_0402_1% 2 PQ1
0.1U_0603_25V7K
2
2
1K_0402_5% 100P_0402_50V8J 1 2 PU15B G SSM3K7002FU_SC70-3

2
4
1
PC27
2VREF_51125 PR13 LM393DG_SO8 S

1
3
+3VL
75K_0402_1%
1
2
1
2
PJSOT24C_SOT23
P D2 P D3 P R17 P C13
1
PR9 150K_0402_1% 1000P_0402_50V7K
2
PJSOT24C_SOT23
210K_0402_1%
2
AB1B_DATA 35
1
AB1B_CLK 35
35 T HM_T RAVEL#
D D
PD19
1
BAV99WT 1G_SC70-3
0.1
PD18
BAV99WT 1G_SC70-3
PD20
BAV99WT 1G_SC70-3+3VL
Security Classification
2008/09/15
Compal Secret Data
2009/09/15 Title
Compal Electronics, Inc.
2
DC-IN/ BATTERY CONN
Size D o cument Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C u s tom L A - 4 902P
D ate: T uesday, December 15, 2009 Sheet 39 of 54
1 2 3 4
A B C D
B+ PL103
VIN P2 P4 1.2UH_1127AS-1R2N_2.4A_30% P4
1 2
PQ101 PQ102 PQ103
AO4407L_SO8 AO4407A_SO8 PR102 PL101 AO4407A_SO8
1 8 8 1 0.01_2512_1% @HCB2012KF-121T50_0805 1 8
2 7 7 2 1 4 1 2 CHG_B+ 2 7
3 6 6 3 3 6
5 5 2 3 5
4.7U_0805_25V6M
4.7U_0805_25V6M
4.7U_0805_25V6M
1
4
ACN
4
1
1
A CP
ACDET + PC132
+3VL
PC102
PC103
PC104
1
1 2 1 2 PR104 PC105 47U_25V_M 1
0.1U_0603_50V7K
PR103 1 2 1U_0603_6.3V6M
2
1
2
PC101 47K_0402_5% 1 2 2
56K_0402_1%
0.1U_0603_25V7K
1
1 2 PR105 PR106
PC108
PR101 15K_0402_5% 0_0402_5%
1
200K_0402_5% PC107 +3VL PC106
1 2
1
PR111 0.01U_0402_16V7K @0.1U_0603_25V7K
D C H GEN# P2
150K_0402_5%
2
G CHG_B+
2
1
S PQ104
3
ADP_EN# VL SSM3K7002FU_SC70-3 PR110
LPREF
ACSET
ACDET
LPMD
ACP
ACN
CHGEN
29 10_0805_5%
PR109 TP
PR138 1 2
1 2 0_0402_5%
5
6
7
8
100K_0402_5% 1 2 8 28 1 2
BATT P2 14,31,35,37,38,42,43,44,48 SLP_S3# IADSLP PVCC
PC109 PC110
D
D
D
D
PR139 1U_0805_25V6K 0.1U_0402_10V7K
1 2 9 27 BST _CHG 1 2 1 2
PR135 1M_0402_5% AGND BTST PR121 PQ106
8
G
S
S
S
100K_0402_1% BQ24740VREF PU101 0_0402_5% AO4466_SO8
1 2 3 1 2 10 BQ24740RHDR_QFN28_5X5 26 D H _ CHG 1 2 BATT
P
4
3
2
1
+ PC111 VREF HIDRV PR145 PL102 PR112
1
O 1U_0603_6.3V6M +3VL 0_0402_5% 10U_LF919AS-100M-P3_4.5A_20% 0.01_1206_1%
1 2 2
-
G
PR136 P U10A 11 25 LX_CHG 1 2 1 2

VDAC PH
23.7K_0402_1%
100K_0402_1% LMV393DR2G_SO8
4
1
5
6
7
8
PC128 4.7U_0805_25V6M
PD102
PC114 4.7U_0805_25V6M
PR113 VAD J 12 24 R E GN 2 1
VADJ REGN
PR140
PC115 4.7U_0805_25V6M
2 PR141 2
453K_0402_1%
4.7U_0805_25V6M
4.7U_0805_25V6M
LLS4148_LL34-2 4.7_1206_5%
1
PR137 13 23 D L _CHG
2
2
EXTPWR LODRV
1
24.3K_0603_1% 35 BAT _PWM_OUT 1 2 4
1 1
PC112
PC113
1 2 PR114
2
422K_0402_1% 1 14 22 PQ107
2
ISYNSET PGND
1
PR115 AO4468L_SO8 PC126
DPMDET
PC116 1M_0402_1% PC118 680P_0603_50V8J 1 2
IADAPT
SRSET
3
2
1
2
CELLS
1
1U_0603_6.3V6M 1U_0603_10V6K PC117
SRN
2
SRP
BAT
PR116 CELLS 35 0.1U_0402_10V7K
2
43.2K_0402_1%
2
2
15
16
17
18
19
20
21
PR117
100K_0402_5%
BATT
I ADAPT
1
P2 PR118 +3VL 47 IADAPT
1 2
1
255K_0402_1%
PC119
AC Detector
1
100P_0402_50V8J
2
PR119
PR120
High 11.85
200K_0402_1% SRSET 47
22K_0402_5% Low 10.55
8
2
1
5 2 1 CHGCT RL 35
P
+ PR122
7
O
1
1
6 ADP_PRES 35,38,47 210K_0402_1% PC120 PC121
2
-
G
1
PU103B PR124 0.1U_0603_50V7K @0.1U_0603_25V7K
PR123
41.2K_0402_1% LMV393DR2G_SO8 147K_0402_1%
4
3 PC122 3
2
1U_0603_6.3V6M
2
2VREF_51125
+3VL
100K_0402_5%
+3VL
1
PR126
PR142
Charge Detector 11K_0402_5% + 5VALW
High 17.588 I ADAPT 1 2 1
+IN
3
E
1 2 PQ108
1 2
1
PR125 Low 17.292 2
B
V+
5
604K_0402_1% MMBT3906_SOT23-3 2
C
PC127 V-
2
V IN P2 VL PR133
220K_0402_5% 1U_0603_10V6K 4
+3VL
1 2 ACDET 3
OUTPUT PMC 35
PR129 -IN
2
1
1
PD103 C H GEN# 47K_0402_5%
1
PR128 PR127 PR151 PR130 PR132 PU104

1
1K_0402_5% 1SS355_SOD323-2 D
76.8K_0402_1% @76.8K_0402_1% 22K_0402_5% 300K_0402_5% L M V 3 2 1 M 5 X - N O P B _SOT23-5
PC124 C HGCT RL1 2 2 1 2 PQ109
2
0.1U_0402_10V7K G BSS138_SOT23-3
2
2
8
S 1 2
3
3
P
+
1
1
1 AC _ADP_PRES PR143
O
1
2 AC_ADP_PRES 35 PC123 PR144 39.2K_0402_1%

-
G
PU103A 0.047U_0402_16V7K PR134 49.9K_0402_1%

2
PR131
LMV393DR2G_SO8 Note: X7R type
4
4
10K_0603_0.1% 470K_0402_5% 4
2
2
2
2VREF_51125
2008/09/15
Compal Secret Data
2009/09/15 Title
Charger
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS L A - 4 902P 0.1
A B C D
A B C D
B++ PR1101 51125_PWR

0_0402_5%
1 2 2 1 1 2
1
PR1100 Vin PD1102
1M_0402_5% PD1101 PD1103
2VREF_51125 2 1 1SS355_SOD323-2
VL +3VL
BATT GLZ27D_LL34-2
2
1SS355_SOD323-2
1
1
BATT_A
1
PR1103 PD1100
1
10K_0402_5% PR1104 RB715F_SOT323-3 PR1106

PC1100 100K_0402_5% BATT_B 2 100_0805_5%
2
2
8
PR1105 0.1U_0603_50V4Z 1 1 2
2
1
93.1K_0603_1% 5 3
1
P
+
7
2
O
6
-
G
PU10B B+_DEBUG
1
1
LMV393DR2G_SO8
PR1109 4 PC1102
20K_0402_1% 0.1U_0603_50V4Z
BAT_ALARM 3 5
2
2
1
PR1110 D
8.06K_0402_1% 2 CFET_B CFET_B
G
S PQ1100
2
SSM3K7002FU_SC70-3
PQ1102 PR1112
0_0402_5%
S
3 1 1 2BATT_IN
D
35 L ATCH
BSS84LT1G_SOT23-3
G
2
BATT
2 2
3
PR1114
470K_0402_5% PQ1113B
2
2N7002KDW-2N_SOT363-6
BATT_IN5
1
PR1115
2 470K_0402_5%
4
PQ1105
1
1
PMBT2222A_SOT23-3
3
PR1117
10K_0402_5% PQ1113A
6
2N7002KDW-2N_SOT363-6
1
47 CFET_A 1 2
6 2
CFET_A PR1118
PD1106 PD1107 2 4.7K_0402_5%
PR1119 1SS355_SOD323-2 SX34-40_SMA
10K_0402_5% 1 2
2
BATT_A_P
1 2 2
PQ1106A
2N7002KDW-2N_SOT363-6
1
3
1
PQ1106B 5 5
2N7002KDW-2N_SOT363-6 3 6 6 3 PR1120
BATT_IN 5 2 7 7 2 470K_0402_5%
1 8 8 1
BATT BATT_A
2
PQ1107 PQ1108
AO4407A_SO8 AO4407A_SO8
3
FET_A 35 3
PQ1109 PQ1110
AO4407A_SO8 AO4407A_SO8 BATT_B
1
1 8 8 1
PMBT2222A_SOT23-3
2 7 7 2 PR1121
470K_0402_5%
3 6 6 3 470K_0402_5%
PR1122 5 5
2
470K_0402_5%
2
BATT_B_P
4
4
PR1124
2
1
PQ1111
2
1
1 2
PR1125
3
1
PD1108 4.7K_0402_5%
FET_B 35 PR1126 SX34-40_SMA
10K_0402_5% 1 2
2
PD1109
3 2
3
1SS355_SOD323-2
PQ1114B
PQ1112B 2N7002KDW-2N_SOT363-6
2N7002KDW-2N_SOT363-6 5
1 2 5
PR1127
4
10K_0402_5%
4
CFET_B
CFET_B
6
6
PQ1114A
PQ1112A 2N7002KDW-2N_SOT363-6
4 2N7002KDW-2N_SOT363-6 BATT_IN2 4
BATT_IN 2
1
1
Security Classification Compal Secret Data Compal Electronics, Inc.

Battery selector
Size Do c ument Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Cu s tom L A -4902P
Da te: Tuesday, December 15, 2009 Sheet 41 of 54
A B C D
A B C D E
2VREF_51125
1
PC302
1U_0603_16V7
2
1 1
PR301 PR302
13.7K_0402_1% 30.9K_0402_1%
+3VALWP 1 2 1 2 +5VALWP
PR303 PR304
B+ B++
20K_0402_1% 20K_0402_1%
B++
PL301 1 2 1 2
HCB2012KF-121T50_0805
1 2 +3VLP
ENTRIP2
ENTRIP1
0.1U_0402_25V6
4.7U_0805_25V6-K
1 PR305 PR306
0.1U_0402_25V6
1000P_0402_50V7K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
107K_0402_1% 95.3K +-1% 0402
1
+ PC316 1 2 1 2
1
PC318
PC304
PC305
PC306
@100U_25V_M
PC303
PC301
2
PC3172
2 1000P_0402_50V7K S IS412DN
2
5
5
1
PQ301 PC307 PQ302
ENTRIP2
VFB2
TONSEL
VREF
VFB1
ENTRIP1
2.2U_0805_10V6K 25 S IS412DN
P PAD
2
4U G1_3V 7 24 4
VO2 VO1
2 8 23 PR308 PC309 2
VREG3 PGOOD 2.2_0402_5% 0.1U_0402_10V7K
PR307
PR309 1 2 1 2 BST_3V 9 22 BST_5V 1 2 1 2 PR310
1
2
3
3
2
1
0_0402_5% VBST2 VBST1 0_0402_5%
PC308 2.2_0402_5%
PL302 1 2 0.1U_0402_10V7K U G_3V 10 21 U G_5V 1 2 PL303
4.7UH_SIQB74B-4R7PF_4A_20% DRVH2 DRVH1 4.7UH_PCMC063T -4R7MN_5.5A_20%
2 1 LX_3V 11 20 LX_5V 1 2 +5VALWP
+3VALWP LL2 LL1
5
5
LG_3V 12 19 LG_5V
DRVL2 DRVL1
1
PQ304
1
SKIPSEL
PR312
VREG5
PR311 4.7_1206_5%
VCLK
1 +3VL 1
GND
EN0
VIN
4.7_1206_5%
+ 4 4 +
2
PU301
2
13
14
15
16
17
18
1
PC310 T PS51125RGER_QFN24_4X4 S T R AON7702L 1N DFN PC311
1
150U_B_6.3VM_R45M 2 2 150U_B_6.3VM_R45M
+5VLP
1
AON7406L_DFN8-5 PR314 PQ303

1
2
3
3
2
1
PC312 @100K_0402_5% PC313
2
1000P_0603_50V8J 2 1 1000P_0603_50V8J
2
2
14,31,35,37,38,40,43,44,48 SLP_S3#
R PGOOD 14
PD302 51125_PWR
@1SS355_SOD323-2
1
1 2 B++
1
PR319
PR315 2VREF_51125 @0_0402_5%
6 ENTRIP1
3 ENTRIP2
@620K_0402_5% +3VEXTLP
2
PC314
2
0.1U_0603_25V7K +5VLP
3 3
1
PU303
1
PC315 1 PC320
PQ305A PQ305B 22U_0805_6.3V6M VIN PR322
1
220K_0402_5%
2N7002KDW-2N_SOT363-6 2N7002KDW-2N_SOT363-6 PC319 5 64.9K_0402_1% 2.2U_0603_6.3V6K
2
PJP301 10U_0805_10V6K VOUT
2 5 2
2
GND
PR325
1 2 +5VALW (4.5A,180mils ,Via NO.= 9)
2
+ 5VALWP
4
1
FB
3
2
P AD -OPEN 4x4m EN
1
PJP303 DEBUG_KBCRST
1
PR316 1 2 +3VALW (3A,120mils ,Via NO.= 6) P2 APL5317 PR323
100K_0402_5% +3VALWP 20K_0402_1%
1 2 +5VLP PR326
VL
2
P AD -OPEN 4x4m
1
470K_0402_5%
1
PR317 PU302
2
330K_0402_5% PJP302 PR320 1 PR324
255K_0402_1% +IN 16.5K_0402_1%
2 1 2 1
KBC_PWR_ON 35 +3VLP +VREG3_51125 5
2
V+
2
P AD -OPEN 2x2m 2
2
V- PR327
PR318
1
100K_0402_5% PJP304 PC321 4 1 2 2 1
OUT
11.5K_0402_1%
2 1 3 PD304
+5VLP VL -IN
1
PR321
1U_0603_10V6K 1SS355_SOD323-2
1
2
P AD -OPEN 2x2m 680K_0402_5%
2
G L M V 3 2 1 A S 5 X _ S O T 23-5
2
S 2 1
DEBUG_KBCRST 33
3
PQ307 PD305 PJP305

SSM3K7002FU_SC70-3 1SS355_SOD323-2 2 1
4
2 1
+3VEXTLP +3VL 4
PD301 VCC1_PWRGD 35,47 P AD -OPEN 2x2m

1SS355_SOD323-2
EN0 39 Security Classification

2008/09/15
Compal Secret Data
2009/09/15 Title
3.3VALWP/5VALWP
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C u s tom L A - 4 902P 0.1
A B C D E
A B C D
1 1
B+ PL401
HCB2012KF-121T50_0805
1 2 VCCP_B+
0.1U_0402_25V6
1000P_0402_50V7K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
+3VS + VCCP
1
1
PC416
PC401 1 2
PC402
PC403
PC404
PR427 PR401 PR417
2
2
10K_0402_5% @10K_0402_5% 1 2 1 2 0_0603_5%
PR402
BST_VCCP
2.2_0603_5% PC405
D H _ VCCP
2
LX_VCCP
0.22U_0603_16V7K
+ 5VALW
37 VCCP_POK
D H _VCCP1
1
5
6
7
8
PR403
0_0402_5% PR404 PQ401
17
16
15
14
13
PU401 2.2_0603_5% S T R T PC8037-H 1N SO8
1 2
GND
PGOOD
PHASE
UG
BOOT
+6269_VCC
2
4
1 12 1 2 PC406
VIN PVCC
+6269_VCC 2.2U_0603_6.3V6K
3
2
1
2 11 D L _VCCP PL402
VCC LG 0.33UH_PCMC063T -R33MN_20A_20%
1
PC407 PR405 1 2
2
2.2U_0603_6.3V6K 0_0402_5%
+VCCP 2
PC409
1 2 3 10
2
FCCM PGND
330U_X_2VM_R6M
330U_X_2VM_R6M
1 1 1
PC408
PC410
PR408 + + +
330U_X_2VM_R6M
1 2 4 9 S E_VCCP 1 2 4.7_1206_5%
14,31,35,37,38,40,42,44,48 SLP_S3# EN ISEN PR407
PR406
COMP
7.87K_0402_1% 2 2 2
FSET
2
@0_0402_5%
VO
4
FB
1
2
1 2 ISL6269ACRZ-T _QFN16
37 VCCP_EN
5
8
PR428 PC412
PC411 PQ402
2
3
2
1
1
0_0402_5% AON6718L
@0.1U_0402_25V4K + VCCP 1000P_0603_50V7K
F B_VCCP
19.1K_0402_1%
0.01U_0402_16V7K
1
1
PR409
49.9K_0402_1%
PR410
PC413
2
1
6800P_0603_50V7K
2
PC414
22P_0402_50V8J
2
(18A,720mils ,Via NO.= 36)

PC415
2
3 3
1 2 1 2 1 2+ VCCP
7 H_VTTVID1 PR416 PR411 PR413
35.7K_0402_1% 1.58K_0402_1% 10_0402_5%
1
H_VTTVID1= Low, 1.1V PR412 1 2

1.96K_0402_1% PR414 VTT_SENSE 7
H_VTTVID1= High, 1.05V 0_0402_5%
2
PC125
@0.1U_0402_10V7K
1
1 2
PR415 VSS_SENSE_VTT 7
0_0402_5%
4 4
2008/09/15
Compal Secret Data
2009/09/15 Title
1.05V_VCCP
A B C D
A B C D
+1.5V
PU601
1 6
VIN VCNTL +5VALW
10U_0805_6.3V6M
10U_0805_10V4Z
2 5
GND NC
1
1
3 7 1
VREF NC
1
PC601
PC602
+5VALW PR601 4 8 PC603
2
1K_0402_1% VOUT NC 1U_0603_10V6K
2
9
2
TP
1
PR604
47K_0402_1% PR602 G2992F1U_SO8
1 2
14,31,35,37,38,40,42,43,48 SLP_S3#
6
10K_0402_5%
0.1U_0402_10V7K
PQ601A
+0.75VSP
2
PD601
1
2N7002KDW-2N_SOT363-6
1 2 2 PR603
3
1K_0402_1%
1
PQ601B
1
1SS355_SOD323-2 PC605
2N7002KDW-2N_SOT363-6
PC604
5 10U_0805_6.3V6M
2
1
4
PC606
2
0.47U_0402_6.3V6K
PJP601
+0.75VSP 1 2 +0.75VS (2A,80mils ,Via NO.= 4)

P AD -OPEN 3x3m
2 2
PR605
0_0402_5%
1 2
SLP_S3# 14,31,35,37,38,40,42,43,48
2
1
316K_0402_1% PC607
PR607 @0.1U_0402_16V7K
2
PR608
402K_0402_1% PU602
1
+1.8VSP 2 1 1 10
FB EN/SYNC
PC608 2 9 PL602
0.1U_0402_16V7K GND GND 1.2UH_1127AS-1R2N_2.4A_30%
PL601
1 2 3 8 1 2 +1.8VSP
HCB1608KF-121T30_0603 SW SW
+ 5VALW
1 2 4 7
IN IN
22U_0805_6.3V6M
22U_0805_6.3V6M
<BOM Structure>
<BOM Structure>
0.1U_0402_25V6
10U_0805_10V6K
10U_0805_10V6K
1 2 5 6
BS POK 1.8VS_POK 37
@B340A_SMA2
PR609 PR606
1
1
PC611
PC610
PC609
PD602
PC613
PC614
3 0_0402_5% 11 4.7_1206_5% 3
TP
2
MP2121DQ-LF-Z_QFN10_3X3
2
2
2
1
PC612
680P_0603_50V7K
PJP602
+1.8VSP 1 2 +1.8VS (1.5A,60mils ,Via NO.= 3)
4
P AD -OPEN 3x3m 4
2008/09/15
Compal Secret Data
2009/09/15 Title
0.75VSP/PCIE/1.8VSP
A B C D
A B C D
PR516 PL501
2 1 1.05VS_B+
14,35,38 PM_SLP_LAN# HCB1608KF-121T30_0603
0_0402_5% PC519 1 2 B+
1000P_0402_50V7K
0.1U_0402_25V6
@1000P_0402_50V7K
4.7U_0805_25V6M
4.7U_0805_25V6M
2
1
PC504
PC505
PC506
PC507
1 1
PR511 PC511
2
5
2.2_0402_5% 0.1U_0402_10V7K
BST _1.05V1 2 1 2 PQ502
S IS412DN
15
14
1
PU501 4
PR514 PR509
EN_PSV
TP
VBST
255K_0402_1% 0_0402_5% +1.05VMP_LAN
+1.05VMP_LAN 1 2 2 13 UG_1.05V 1 2 UG1_1.05V PL503
TON DRVH 2.2UH_PCMC063T -2R2MN_8A_20%
3
2
1
1 2 3 12 LX_1.05V 1 2
PR519 0_0402_5% VOUT LL
PR517
+ 5VALW + 5VALW1 2 4 11 1 2 15.4K_0402_1%
V5FILT TRIP
5
6
7
8
1
PR518 +1.05VMP_LAN PR503
1 2 5 10 + 5VALW PQ504
316_0402_1% VFB V5DRV PR513
4.12K_0402_1% 1
1
1
6 9 LG_1.05V 4.7_1206_5%
PGOOD DRVL
1
PGND
PC520 PC521 +
GND
2
1U_0603_10V6K 1 2 4.7U_0805_10V6K 4
2
2
PC526 PC514 PC515
2
1
@10P_0402_50V8J T PS51117RGYR_QFN14_3.5x3.5 4.7U_0805_6.3V6K 2 330U_B2_2.5VM_R15M
8
1
PC517
PR504 S T R AO4712L 1N SO8 1000P_0603_50V8J
3
2
1
2
10K_0402_1%
2
2 2
1.05VM_LAN_POK 37
PJP501
+1.05VMP_LAN 1 2 +1.05VM_LAN (8A,320mils ,Via NO.= 16)

P AD -OPEN 4x4m
PR521 PL504
2 1 1.5V_B+
14,38 SLP_S4# HCB1608KF-121T30_0603
0_0402_5% PC524 1 2 B+
1
1000P_0402_50V7K
0.1U_0402_25V6
@1000P_0402_50V7K
4.7U_0805_25V6M
4.7U_0805_25V6M
2
1
PC501
PC502
PC508
PC509
5
PR510 PC510
2
2.2_0402_5% 0.1U_0402_10V7K PQ501
BST _1.5V 1 2 1 2
S IS412DN
4
15
14
1
3 PU502 3
PR523 PR508
EN_PSV
TP
VBST
255K_0402_1% 0_0402_5% +1.5VP

1 2 2 13 U G_1.5V 1 2 UG1_1.5V PL502
3
2
1
TON DRVH 2.2UH_PCMC063T -2R2MN_8A_20%
+1.5VP 1 2 3 12 LX_1.5V 1 2
PR520 0_0402_5% VOUT LL
PR515
+ 5VALW + 5VALW1 2 4 11 1 2 7.87K_0402_1%
V5FILT TRIP
5
6
7
8
1
PR522 PR501
+1.5VP 1 2 5 10 + 5VALW
316_0402_1% VFB V5DRV PR512
10.2K_0603_0.1% 1
1
6 9 LG_1.5V 4.7_1206_5%
PGOOD DRVL
1
PGND
PC522 PC523 +
GND
2
1U_0603_10V6K 4.7U_0805_10V6K 4 PC513
2
4.7U_0805_6.3V6K PC512
2
1
T PS51117RGYR_QFN14_3.5x3.5 2 330U_2.5V_B2_R15M
7
8
1
PC516
PR502 1000P_0603_50V8J
3
2
1
2
10K_0603_0.1%
2
PQ503
ST S14N3LLH5 1N SO8
1.5V_POK 37
PJP502
+1.5VP 1 2 +1.5V (8A,320mils ,Via NO.= 16)

4 4
P AD -OPEN 4x4m
2008/09/15
Compal Secret Data
2009/09/15 Title
1.5VP/1.05VMP
A B C D
8 7 6 5 4 3 2 1
+VCCP
H _ VID0 2 1 PR2 66 @1 K_0402_5% H _ VID0 2 1 PR280 1K_0402_5%

H _ VID1 2 1 PR2 67 @1 K_0402_5% H _ VID1 2 1 PR281 1K_0402_5%
C PU_B+ PL201
H _ VID2 2 1 PR2 68 1K_0402_5% H _ VID2 2 1 PR282 @1 K_0402_5% SMB3 0 2 5500YA_2P
2 1 B+
H H _ VID3 2 1 PR2 69 1K_0402_5% H _ VID3 2 1 PR275 @1 K_0402_5% H
@1 0 0 U_25V_M
2 2 0 0 P_0402_50V7K
4 .7 U_ 0805_25V6-K
4 .7 U_ 0805_25V6-K
1 0 0 0 P_0402_50V7K
0 .1 U_0402_25V6
H _ VID4 2 1 PR2 70 @1 K_0402_5% H _ VID4 2 1 PR276 1K_0402_5%
4 .7 U_ 0805_25V6-K
4 .7 U_ 0805_25V6-K
@1 0 0 0P_0603_50V7K
1
PC206
7 H_ VID0 H _ VID0 H _ VID5 2 1 PR2 71 1K_0402_5% H _ VID5 2 1 PR277 @1 K_0402_5%
1
+
PC201
PC203
PC204
PC220
PC249
1
1
PC202
PC207
PC208
7 H_ VID1 H _ VID1 H _ VID6 2 1 PR2 72 @1 K_0402_5% H _ VID6 2 1 PR278 1K_0402_5%
2
2
2
H _ VID2 PRO C_ DPRSL PVR 2 1 PR2 73 1K_0402_5% PRO C_ DPRSL PVR 2 1 PR279 @1 K_0402_5% 2
7 H_ VID2
2
5
6
7
8
7 H_ VID3 H _ VID3
H _ VID4 PQ201
7 H_ VID4
7 H_ VID5 H _ VID5 PR208 PC209 UG AT E1 _ CPU2 4 S T R T PC8 0 3 7 -H 1N SO8

2 .2 _0603_5% 0 .2 2 U_ 0603_10V7K
7 H_ VID6 H _ VID6 BO O ST _ CPU2 2 1 1 2 PR2 49
0_0603_5%
35 PM_ PWROK 1 2 PR2 09 0_0402_5% UG AT E_ CPU2 2 1 PL202
3
2
1
G 0 .3 6 UH_ PCMC1 0 4 T - R36MN1R17_30A_20% G
7 PRO C_ DPRSL PVR PRO C_ DPRSL PVR P HASE_ CPU2 1 4 +CPU_ CO RE

LF2 2 3 V 2N
5
11 CL K_ EN#
3 .6 5 K_0603_1%
1 0 K_0402_1%
1
1
+3 VALW
4.7_1206_5%
PQ202
1
TPCA8036
PR211
PR2 15
PR213
PR214
47K_0402_5% PR216
1 2 CL K_ EN# 1_0402_5%
L G AT E_ CPU2 4
2
VSUM-
1 0 0 0P_0603_50V7K
1
PR219
3
2
1
PC2 10
0_0402_5%
1 2
2
14,35 VGATE IS EN2
VSUM+
+VCCP 1 2 PR221 @1 K_0402_5%
F F
PSI# CPU_B+
7 PSI#
2 1 PR283 1 K_ 0402_5%
1 2
2 2 0 0P_0402_50V7K
1 0 0 0P_0402_50V7K
0 .1 U_0402_25V6
PR223 1 4 7 K_0402_1%
5
6
7
8
+5 VALW
4 .7 U_0805_25V6-K
4 .7 U_0805_25V6-K
4 .7 U_0805_25V6-K
4 .7 U_0805_25V6-K
PC211
1 2 1 U_ 0 6 03_10V6K
40
39
38
37
36
35
34
33
32
31
+VCCP
1
PC2 12
PC2 51
PR224 PU2 01 1 2
1 U_ 0 603_10V6K
PC2 13
PC2 14
PC2 15
PC2 16
PC2 17
68_0402_5%
DPRSLPVR
VR_ON
CLK_EN#
VID6
VID5
VID4
VID3
VID2
VID1
VID0
1 2 PR226
2
1
4 H_ PRO CHO T#
PC218
PR225 30 2 .2 _0603_5% PC2 19 UG AT E1 _ CPU3 4
0_0402_5% BOOT2 PU2 0 2 0 .2 2 U_ 0603_10V7K
29
UGATE2 BO O ST _1CPU3 PR2 64
1 28 5 1 2 1 2
2
PGOOD PHASE2 VCC BOOT 0_0603_5% PQ203
2 27
PSI# VSSP2 UG AT E_ CPU3
3 26 6 8 1 2
3
2
1
RBIAS LGATE2 FCCM UGATE S T R T PC8 0 3 7 -H 1N SO8
4 25 +5 VALW
VR_TT# VCCP P HASE_ CPU3 PL203
E 5 24 2 7 E
NTC PWM3 PWM PHASE 0 .3 6 UH_ PCMC1 0 4 T - R36MN1R17_30A_20%
6 23
VW LGATE1 L G AT E_ CPU3
7 22 3 4 1 4 +CPU_ CO RE
COMP VSSP1 GND LGATE
8 21
FB PHASE1 PR228 ISL 6 2 0 8 CRZ-T_QFN8 LF3 V 3N
1 2 9 2 3
ISEN3
1
4 .7 _1206_5%
1 0 K_0402_1%
UGATE1
10 @0_0402_5%
BOOT1
ISEN2
1
ISUM+
@2 4 9K_0402_1%
8 .0 6 K_0402_1%
1 0 0 0 P_0402_50V7K
3 .6 5 K_0603_1%
PR2 29
ISEN1
ISUM-
PC221 PQ204
VSEN
1 2
IMON
VDD
RTN
PR2 31
PR2 32
TPCA8036
VIN
@2 2 P_ 0 402_50V8J 41 PR233
AGND
1
PC222
1_0402_5%
1
PR234
PR235
ISL 6 2 8 8 3 HRZ- T_QFN40_5X5

11
12
13
14
15
16
17
18
19
20
2
4
2
2
3 9 0 P_0402_50V7K PC2 23
2
1 2 1 2 1 U_ 0 6 03_10V6K VSUM-
2
1 0 0 0P_0603_50V7K
PR236
562_0402_1% PC2 24
3
2
1
1
PR239 0_0402_5%
PC2 26
1 2 1 2 1 2
PC2 25 IS EN3
2
3 3 P_ 0402_50V8J PR238 PR2 42 0_0402_5% IMVP_ IMO N 7 VSUM+
D 2 .3 7 K_0402_1% 1 2 CPU_B+ PR2 40 @4 0 2K_0402_1% D
1 2 1 2 1 2 +1 .05VS
PC227 PR241
1 5 0 P_ 0402_50V8J 3 2 4 K_0402_1% PR2 44 1_0402_5%
CPU_B+
0 .0 6 8 U_0603_16V7K
1 2 +5 VALW
IS EN3
1
1
1 U_ 0 603_10V6K
0 .2 2 U_0603_25V7K
PC228
PC229
PC230
IS EN2
0 .2 2 U_0402_10V6K
0 .2 2 U_0402_10V6K
0 .2 2 U_0402_10V6K
PR2 46
2
2 2 0 0P_0402_50V7K
1 0 0 0P_0402_50V7K
4 .7 U_0805_25V6-K
4 .7 U_0805_25V6-K
0 .1 U_0402_25V6
IS EN1 6 .8 1 K_0402_1%
5
6
7
8
4 .7 U_0805_25V6-K
4 .7 U_0805_25V6-K
2
1
PC2 31
PC2 52
VSSSENSE
BO O ST_ CPU1
PC2 32
PC2 33
PC2 34
PC2 38
PC2 39
PR274
1
1
PC235
PC236
PC237
0_0603_5%
2
UG AT E_ CPU1 2 1 UG AT E1 _ CPU1 4
2
PR2 48 PC240
C 2 .2 _0603_5% 0 .2 2 U_ 0603_10V7K C
3
2
1
VSUM+ 2 1 1 2 PQ205
S T R T PC8 0 3 7 -H 1N SO8
PL204
82.5_0402_1%
0 .3 6 UH_ PCMC1 0 4 T - R36MN1R17_30A_20%

P HASE_ CPU1 1 4 +CPU_ CO RE
1
0 .0 4 7 U_0402_16V7K
2 .6 1K_0402_1%
1
0 .3 3 U_0603_10V7K
4 .7 _1206_5%
PR252
LF1 2 3 V 1N
5
PR250
0 .0 2 2 U_0402_25V7K
PR2 53
1
1
0 .0 1 U_0402_25V7K
PC2 41
7 V C CSENSE 1 2 PQ206
1
3 .6 5K_0603_1%
<BO M Structure>
TPCA8036
10K_0402_1%
2
PR255
PR2 51 0_0402_5% PR2 57
2
PC2 42 2
PC2 43 2
2
1
PR256
1_0402_5%
1
PC244 L G AT E_ CPU1 4
PC2 45
3 3 0 P_0402_50V7K
2
2
1 0 0 0P_0603_50V7K
2
1
VSUM-
PC246
3
2
1
3 3 0 P_0402_50V7K
2
1
B B
1 1 K_0402_1%
PR260
1
PC248
PR262
PC247 768_0402_1% PH2 0 1

1 0 0 0P_0402_50V7K 1 2
PR2 63 0_0402_5% 1 0 KB_ 0 6 0 3 _ 5 %_ERTJ1VR103J IS EN1
2
1 2 VSUM+
7 VSSSENSE
2
VSUM-
0 .1 U_ 0402_16V7K
1
PC2 50
2
A A
2008/09/15
Compal Secret Data
2009/09/15 Title
CPU_CORE
Size Do cu me n t Number Rev
L A-4891 0.1
Da te: T u e sd a y, De ce mber 15, 2009 Sheet 46 of 54
8 7 6 5 4 3 2 1
5 4 3 2 1
BQ24740VREF
1
PR1000
165K_0402_1%
PC1000
2
0.22U_0603_10V7K
1 2
+5VS
0.01U_0402_16V7K
1 2 1
40 IADAPT PR1013 +IN
D D
10K_0402_1% 5
V+
41 CFET _A 1 2 2
V-
PC1001
PR1014
150K_0402_5% 4
OUTPUT
3
2
-IN
2
G
PQ1000
1
BSS138_SOT23-3 +3VS
1 3 3 1 PU1000
1
L M V 3 2 1 M 5 X - N O P B _SOT23-5 PR1017
D
D
S
1
D PQ1001 2K_0402_5%
2
2 BSS138_SOT23-3 PR1018
2
8,40 ADP_PRES
G O C P_ADJ 39 100K_0402_1%
S PQ1002 PR1019
3
2
SSM3K7002FU_SC70-3 10K_0402_5%
1
PD1001
1SS355_SOD323-2 1 2 O CP# 15
PD1000 PR1020
1
AD P _SIGNAL 1SS355_SOD323-2 0_0402_5%
1
D
D
1 2 3 1 2 1
3.9K_0402_5%
PR1022 PQ1003 1 2 2
1
100_0402_5% NDS0610_NL_SOT23-3 35 O CP PR1015 G
1
PR1025
3900P_0402_50V7K
@0_0402_1%
G
S
3
PQ1004
SSM3K7002FU_SC70-3
2
PC1003
2
1
C PR1023 +3VS C
SRSET 40
27.4_0402_1% 1 2
2
C PR1016
1 2 2 PQ1005 200K_0402_1% PR1027
2
PR1028 B MMBT 3904W_SOT323-3 10K_0402_1%
100K_0402_5% E
3
VIN P U1 +5VS
1
1 2 1
IN+
1 2O C P _A_IN O C P _A_IN 35 PR1021 5
VCC+
1
1
PR1032 100K_0402_1% 2
100_0402_5% GND
PR1030 4
PD1003 OUT
68K_0402_5% 3
IN-
0.01U_0402_16V7K
GLZ4.7B_LL34-2 LMV331IDCKRG4_SC70-5
2
PC1002
1
2
PR1040
33K_0402_5%
+3VS
ADP_EN# 40
1
1 2
2
PR1042 PR1026
8.06K_0402_1% 100K_0402_1%
2
4.7K_0402_5%
PR1024
2
1
100K_0402_1%
3
PR1045
+3VL PQ1007B
1
1
2N7002KDW-2N_SOT363-6
3
B B
8.66K_0402_1%
E
5
2
VC C 1_PWRGD 35,42
PR1046
B
2
4
C
PQ1006
2
MMBT3906_SOT23-3
2 1 AD P _ A_ID
PD1004
1
1SS355_SOD323-2
PR1059
45.3K_0402_1%
6
PQ1007A
2
2N7002KDW-2N_SOT363-6
2 ADP_EN 35
2VREF_51125 1 2
1
PR1062
1M_0402_5% +3VL
1
VL
PR1063
130K_0402_1% PR1064
22K_0402_5%
8
2
3
P
+
A 1 ADP_DET# 35 A
O
1
2
-
G
PR1065
P U15A
10K_0402_1%
4
LM393DG_SO8
2
1 2AD P _ A_ID AD P _ A_ID 35

2008/09/15
Compal Secret Data
2009/09/15 Title
PR1066
10K_0402_5%
ADP_OCP
5 4 3 2 1
5 4 3 2 1
GPU_VID0 GPU_VID1 GPU_VID2 +NVVDD

0 0 0 0.75V
1 0 0 0.8V
1 1 0 0.85V
PR701
200K_0402_5%
D
1 2
1 1 1 1V D
7,38,40,42,43,44 SLP_S3#
1
PL701
PC701
0.22U_0402_10V6K HCB1608KF-121T30_0603
2
VGA_B+ 1 2 B+
@0.1U_0402_25V6
4.7U_0805_25V6-K
4.7U_0805_25V6-K
2200P_0402_50V7K
1
@1000P_0603_50V7K
PC708
PC703
PC704
PC710
@1000P_0603_50V7K
1
PC719
2
PC718
5
6
7
8
+ 5VALW
2
1+5VALW
PQ701
BST _VGA 1 2 1 2 T PC8037_SO8
PR704 PC706
0_0402_5% 0.1U_0402_10V7K 4
PR702
15
14
1
316_0402_1% PU701
PR705
EN_PSV
TP
VBST
255K_0402_1%
2
3
2
1
1 2 2 13 D H _ VGA 1 2 D H _VGA_1 PL702
TON DRVH PR707 0.68UH_PCMC063T -R68MN_15.5A_20%
C +VGA_COREP 3 12 LX_VGA 0_0402_5% 1 2 C
VOUT LL +VGA_COREP
330U_D2E_2.5VM_R9M
4 11 1 2
V5FILT TRIP
330U_D2E_2.5VM_R9M
PR706 1 1
5 10 + 5VALW 12.4K_0402_1%
VFB V5DRV
5
6
7
8
PC709
PC711
PR720 + +
1
1
6 9 PC707 PQ702 4.7_1206_5%
PGOOD DRVL
PGND
PC702 4.7U_0805_10V6K
GND
2
1U_0603_10V6K 2 2
37 NVVDD_POK
2
1
D L _VGA 4
8
PC716
S IC RT 8209BGQW WQFN 14P PWM 1000P_0603_50V7K
2
AO4714_SO8
3
2
1
@10P_0402_50V8J
PC713
1 2 +VGA_COREP
2 1 PR717
PR709 10_0402_5%
PR708
90.9K_0402_1%
2 1 2 1 +VGA_COREP1 1 2 + NVVDD_SENSE
+NVVDD_SENSE 23
1K_0402_1% PR718
1
0_0402_5%
PR740
1
17.8K_0402_1%
2N7002KDW-2N_SOT363-6
PR734
2
B B
4.42K_0402_1%
PR737
1
PQ710B
2
2 1 GPU_VID0 20
2
PQ711 PR739
1
D SSM3K7002FU_SC70-3 15K_0402_1% 15K_0402_1% PR738

5
2 @10K_0402_5%
6 2
G
4
S PC717
3
0.022U_0402_16V7K
1
PQ710A
1
2 1 GPU_VID1 20
2
2N7002KDW-2N_SOT363-6
2
2.61K_0402_1% PR733
PR732 @10K_0402_5%
PC726
1
0.022U_0402_16V7K PJP701
1
+VGA_COREP 1 2 + N VVDD (10A,400mils ,Via NO.= 20)

P AD -OPEN 4x4m
PJP702
1 2
P AD -OPEN 4x4m
A 2 1 GPU_VID2 20 A
2
PR735 PR736
2
5.1K_0402_1% @10K_0402_5%
PC727
0.022U_0402_16V7K
1
2008/09/15
Compal Secret Data
2009/09/15 Title
VCCGFX
5 4 3 2 1
5 4 3 2 1
Version change list (P.I.R. List) Power section Page 1 of 1
Item Reason for change PG# Modify List Date Phase
D D
3
4
C C
B B
A A
Security Classification Compal Secret Data Compal Electronics, Inc.

Changed-List History
Size D o c u m e nt Num ber Rev
A N D TR A D E SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
LA-4 902P 0.1
D E P A R TMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
D a te: T u e sd a y , D ecem ber 15, 2009 Sheet 49 of 54
5 4 3 2 1
Version Change List ( P. I. R. List ) for HW Circuit DB-1>> DB-2
A B C D E
Request
Item Page# Date Owner Solution Description Rev.
1 01 2 009/02/06 HP Del R4, R6, R8 for XDP. 0.2
1
2 01 2 009/02/06 HP Del R40 for Thermal sensor. 0.2 1
3 01 2 009/02/06 HP Del R34, R36, R46, R49, R37 for XDP. XD P. 0.2
4 01 2 009/02/24 HP Change R31 24.9K ohm to 1.5K ohm and R33 12.4K ohm to 750 ohm for intel WOW. 0.2
5 01 2 009/02/25 HP Debug port design guide changed XDP debug ports to CFG4 - pin 28, CFG5 - pin 30, CFG10 - pin 22, and CFG11 pin 24. 0.2
6 02 2 009/02/19 HP No install R60, R61.
R 61. 0.2
7 12 2 009/02/25 Compal Install
In stall C193, C194 for WLAN nosie 0.2
8 12 2 009/02/06 HP Change R1026, R181, R185, R1027 from 15 ohm to 0 ohm.
oh m. 0.2
9 12 2 009/02/06 HP Del C205, C207, C208, C209 for docking. 0.2
10 12 2 009/02/06 HP Change D1pin 2 form +3VL to +VREG3_51125
+VREG3_511 25 0.2
11 12 2 009/02/06 HP D el JP15 pin 51, 53 trace (SMB_DATA_S3, SMB_CLK_S3) and add test point. 0.2
12 12 2 009/02/11 HP Add R1144 1K ohmohm 0.2
13 12 2 009/02/11 HP A dd Test point for SATA bus. 0.2
14 12 0.2
2 2
2 009/02/18 HP Add NAND Flash dect pin (BRAID_DET)

15 13 2 009/02/06 HP Install R354 0.2
16 13 2 009/02/06 HP Add R1138 10K ohm 0.2
17 13 2 009/02/20 HP Change
Cha nge R1092, R1093 power sourece form +3VS to +3VS. 0.2
18 13 2 009/02/20 HP Del R208, R210
R210 0.2
19 13 2 009/02/22 HP Add Q76A and Q76B for CBB C BB 0.2
20 13 2 009/02/22 HP Reserve
Rese rve R1146 and R1147 for external VGA thermal 0.2
21 14 2 009/01/22 HP Del R238, because double pull down. 0.2
22 14 2 009/02/19 HP Del R288 0.2
23 14 2 009/02/06 HP S tuff R296 0.2
24 14 2 009/02/06 HP Add R1142 10K ohm 0.2
3
25 14 2 009/02/25 Compal Add C949 for RF 0.2 3
26 16 2 009/01/22 HP Del L1, C228, C229 and add test point.po int. 0.2
27 16 2 009/01/22 HP Del L2, C241 and add test point.
poi nt. 0.2
28 16 2 009/01/22 HP Del C847 and add test point.
poi nt. 0.2
poi nt. 0.2
30 16 2 009/01/22 HP Del L3, C263, C262 and add test point.
poi nt. 0.2
31 16 2 009/02/03 HP Change R299, R300 form 10 ohm to 100ohm. 0.2
32 16 2 009/02/03 HP C hange C278 form 0.1uF to 1uF. 0.2
33 16 2 009/02/05 HP Change C243, C244 form 10uF to 22uF. 0.2
34 18 2 009/02/18 Compal A dd L48, L49, L50, C944, C943, C942 for EMI 0.2
35 18 2 009/02/24 Nvidia Change R321, R320, R319, R318 form 2.2K ohm to 4.7K ohm. 0.2
36 18 2 009/02/18 Compal Reserve
Res erve D5, D6, D7, D8, D9 for ESD 0.2
37 18 0.2
4 4
2 009/02/12 Nvidia Del R1066

38 19 2 009/01/22 HP Add
Ad d Q71, Q72, R1134 for Keyboard light 0.2
THIS S HE E T OF E NGINE E RING DRA W ING IS THE P ROP RIE TA RY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Hardware revision (0.1 to 0.2)
A ND TRA DE S E CRE T INFORMA TION. THIS S HE E T MA Y NOT B E TRA NS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DE P A RTME NT E XCE P T A S A UTHORIZE D B Y COMP A L E LE CTRONICS , INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
C u s t om L A -4 9 0 1 P 1 .0
MA Y B E US E D B Y OR DIS CLOS E D TO A NY THIRD P A RTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A B C D E
A B C D E
Request
39 19 2 009/02/06 Nvidia A dd C914, C915, C916, C917 for eDP. 0.2
1
40 19 2 009/02/06 HP Change R341 pin 1 power plan form +5VS to +3VALW. 0.2 1
41 20 2 009/02/12 Nvidia Reserve

Re serve R1150 0.2
42 20 2 009/02/24 HP Change R355, R356 from 2K ohm to 10K ohm. oh m. 0.2
43 20 2 009/02/25 HP Add
Ad d Q78, R1158, R1157 for thermal trip. 0.2
44 21 2 009/01/20 HP Del LVDS function 0.2
45 21 2 009/02/26 Nvidia Del
De l C346, because no SPDIF. 0.2
46 22 2 009/01/20 Nvidia A dd C924 ~ C931 for DP function 0.2
47 22 2 009/02/06 Nvidia Del RP28, 31, 34, 40, 49, 52, 55, 29, 43, 35, 39, 44, 48, 53, 56, 30, 33, 36, 38, 45, 46, 42 for VRAM 0.2
48 22 2 009/02/06 Nvidia Del C904, 899, 900, 901, 902, 903 for VRAM 0.2
49 23 2 009/02/23 Nvidia Add L47, C941 for SP_PLLVDD 0.2
50 26 2 009/02/19 HP Del C505, C509, C507, C508, C905, Q18, R440, R1062, R441 R441 0.2
51 26 2 009/02/06 HP Add C934 0.2
52 27 0.2
2 2
2 009/02/18 HP ReserveD57
Rese rveD57 for ESD
53 28 2 009/02/06 HP R ecover Q25, R503, R483 0.2
54 29 2 009/02/26 HP A dd R1159 for NAND Flash detect 0.2
55 30 2 009/02/24 Compal Del R529, R528, R535, C618, U22U 22 0.2
56 30 2 009/02/24 Compal Add Q79 ~ Q83, R1163, R1162, R1164, C945, C946, C947, C948 C948 0.2
57 31 2 009/02/22 Compal Del D30, U28, C711, R608 0.2
58 32 2 009/02/18 HP Reserve
Rese rve D33, D34, D36, D68 for ESD 0.2
Res erve D32 for ESD 0.2
60 34 2 009/02/06 HP Add JP32 of pin 179, 178, 11, 10 to +5VS 0.2
61 34 2 009/01/22 HP Del C746 ~ C761
C761 0.2
62 34 2 009/02/06 HP A dd Q75, R1145. 0.2
3
63 34 2 009/02/06 HP Del R647~ R650 0.2 3
64 35 2 009/02/06 HP Reserve
Re serve R711 0.2
65 35 2 009/02/06 HP Add R1140 0.2
66 35 2 009/02/16 HP Change R692 from 10K ohm to 220 ohm o hm 0.2
poi nt. 0.2
68 36 2 009/02/18 Compal change
cha nge Super IO from ITE to SMSC 0.2
69 37 2 009/02/25 HP Del R758 0.2
70 37 2 009/02/06 HP C hange R941 pin from PM_SLP_LAN# to PM_SLP_M# 0.2
71 37 2 009/02/25 HP change
ch ange R1044 from 49.9K ohm to 78.7K ohm. 0.2
72 38 2 009/02/18 Compal Add Q77, R1170, C939, R1156, C935 ~ C938 C9 38 0.2
73 0.2
74 0.2
75 0.2
4 4
76 0.2
C u s t om L A -4 9 0 1 P 1 .0
A B C D E
A B C D E
Request
01 15 2 009/03/23 Compal Add RP59 0.3
1
Re serve C956 ~ C951 for RF 0.3 1
03 30 2 009/03/08 Compal Add R1173 for RF 0.3

04 36 2 009/03/23 Compal Add R1174 10K ohm 0.3
05 36 2 009/03/23 Nvidia Change R1059 from 40.2 ohm to 60.4 ohm 0.3
06 36 2 009/03/23 Nvidia Change R418 from 60.4 ohm to 40.2 ohm 0.3
07 36 2 009/04/09 Compal Install R706 for SMSC CBB
C BB 0.3
08 23 2 009/04/09 Nvidia Del L16, C429 ~ C432 for no use LVDS function 0.3
09 23 2 009/04/09 Nvidia Del L17, C433 ~ C435, C436, C437, C883 for no use LVDS function
function 0.3
10 23 2 009/04/09 Nvidia A dd R1175 ~ R1177 for no use LVDS function 0.3
11 18 2 009/04/09 HP Add
Ad d C957 for DP issue 0.3
12 01 2 009/04/13 Compal D el R12 for follow UMA 0.3
13 38 2 009/04/13 Compal Del
Del Q70, R1094 for follow UMA 0.3
14 35 0.3
2 2
2 009/04/13 Compal Reserve

Re serve R1140
15 31 2 009/04/13 Compal Add
Ad d R1179 for follow UMA 0.3
16 16 2 009/04/13 Compal D el R290, R291 for follow UMA 0.3
17 15 2 009/04/13 Compal Change C956 ~ C951 from 47P to 22P for RF 0.3
18 04 2 009/04/10 HP Install R51 0.3
19 27 2 009/04/10 HP No install R1083
R1083 0.3
20 33 2 009/04/10 HP Reserve
Re serve R1180 0.3
21 15 2 009/04/10 HP LAN_DIS# should pull up to +3VM_LAN instead of 3VALW 0.3
22 04 2 009/04/10 HP Change R14/R15 to 1.1K1%/3K1% per DG1.52
DG1. 52 0.3
23 20 2 009/04/10 HP Install R1085 and R1086 for SM communication to GPU
G PU 0.3
24 15 2 009/04/10 HP Reserve
Re serve R1181 0.3
3
25 19 2 009/04/10 HP Reserve
Re serve R331 0.3 3
26 19 2 009/04/10 HP Del R484 0.3

27 09 2 009/04/10 HP D el M2 0.3
28 10 2 009/04/10 HP D el M2 0.3
29 38 2 009/04/13 Compal Add R1178 0.3
30 13 2 009/04/10 HP XTAL_IN (ohm to GND if not used)For discrete:NO INSTALL: R215, Y4, C226, INSTALL 0ohm resistor in C227 0.3
31 35 2 009/04/14 Compal Install R1035, R1036, R1037; no install R1034.
R1 034. 0.3
0.3
4 4

C u s t om L A -4 9 0 1 P 1 .0
A B C D E
Version Change List ( P. I. R. List ) for HW Circuit DB-3>> SI-1
A B C D E
Request
01 16 2 009/04/24 HP Del R294 0.4
1
02 13 2 009/04/24 HP Del CLRP2
CLRP2 0.4 1
03 14 2 009/04/24 HP Del C147, C148 location

locat ion 0.4
04 14 2 009/04/24 HP Add C961 0.4
05 14 2 009/04/24 HP A dd R1188, R1187 for intel spec 0.4
06 27 2 009/04/24 HP Add C962 ~ C965 0.4
07 36 2 009/04/24 HP Add R1190, R1189 0.4
08 29 2 009/04/24 HP D el C574~C577 and C579~C582. 0.4
09 33 2 009/04/24 HP Add R1191, R1192 0.4
10 26 2 009/05/02 HP Add R1198, R1199 0.4
11 04 2 009/05/02 HP Install R1060 0.4
12 35 2 009/05/02 HP Add R1197, C967, C966, C968, R1195, R1196
R11 96 0.4
2
13 38 2 009/05/02 HP Add C978, C979 0.4 2
Version Change List ( P. I. R. List ) for HW Circuit SI-1>> SI-1b

Request
01 04 2 009/07/21 HP Add C997, R1219, Q87, R1218 for CPU S3 power savings issue 0.5
02 04 2 009/07/02 HP Add R1226 for CPU S3 power savings issue 0.5
03 05 2 009/07/21 HP Add Q88,
Q8 8, Q89 and reserve R1220, R1222 for CPU S3 power savings issue 0.5
04 07 2 009/07/02 HP A dd Q91, R1224, C994, C995, C991, C992, C993, C996, Q92, R1223 for CPU S3 power savings issue 0.5
05 19 2 009/06/30 HP A dd R1213, D72 for Lid SW issue 0.5
06 37 2 009/07/09 HP Change
Ch ange C864 from 0.047uF to 0.068uF. 0.5
3 0.5 3
4 4

C u s t om L A -4 9 0 1 P 1 .0
A B C D E
Version Change List ( P. I. R. List ) for HW Circuit SI-1b>> SI-2
A B C D E
Request
01 07 2 009/07/22 HP Change C72 ~ C75 from 10uF to 20uF
20 uF 0.6
1
Res erve R1215 for CLK gen change 0.6 1
03 15 2 009/07/23 Compal Add C949 ~ C951 for Compal RF team.

te am. 0.6
04 12 2 009/09/03 Compal C hange JBAT1 Connector. 0.6
Re serve Q 0.6
06 0.6
07 0.6
08 0.6
09 0.6
10 0.6
11 0.6
12 0.6
13 0.6
14
2 2
15
16
17
18
19
20
21
22
23
24
3
25 3
26
27
28
29
30
31
4 4

C u s t om L A -4 9 0 1 P 1 .0
A B C D E

Compal Confidential: Cartier DIS LA-4901P

Uploaded by

Copyright:

Available Formats

Compal Confidential: Cartier DIS LA-4901P

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Compal Confidential: Cartier DIS LA-4901P

Uploaded by

Copyright:

Available Formats

1 2 3 4 5

with IBEX PEAK-M core logic

S ecurity Classification Compal Secret Data Compal Electronics, Inc.

The rmal Sensor Fan C ontrol DP to Docking

Page 4 Page 36 Page 34

Socke t-rPGA989 Dual Channel

Page 4,5,6,7,8 Clo ck Generator

PCIE X1 + USB X1 PCIE X1 USB2.0 Finger Printer VFM451 daughte r board

Audi o CKT TPA6047A

2.5" SATA HDD Connector

Track Point CONN.

( O MEANS ON X MEANS OFF )

SMBUS Control Table

S ecurity Classification Compal Secret Data Compal Electronics, Inc.

Layout rule ： 10mil width tr ace +VCCP +VCCP +VCCP

length < 0.5", spacing 20mil PM_EXTTS#0 R1 1 2 10K_0402_5%

JTAG & BPM

31 OBSDATA_B1 OBSDATA_D1 32 2008/12/12 HP DB-1 R23

P M _ P W R B TN#_R PWRGOOD/HOOK0 ITPCLK/HOOK4 C L K _ C PU_XDP#

Processor Pullups Thermal Sensor EMC2113-2 with CPU PWM FAN

EMC2103 (default) EMC2113

REMOTE Thermal sensor Install R1060 R794,R1061

Don't Install R794,R1061 R1060

Layout rule ： tra ce

JCPU1A C O NN@ JCPU1E C ONN@

PCI EXPRESS -- GRAPHICS

CFG Straps for PROCESSOR I C , A U B _ C F D_rPGA,R1P0

C FG 0 R67 1 @ 2 3.01K_0402_1% C FG 7 R68 1 @ 2 3.01K_0402_1%

CFG3-PCI Express Static Lane Reversal

CFG4-Display Port Presence

S ecurity Classification Compal Secret Data Compal Electronics, Inc.

DDR SYSTEM MEMORY - B

S ecurity Classification Compal Secret Data Compal Electronics, Inc.

AD35 D12 AK21 AJ1 2009/07/02 HP SI-2

PEG & DMI

VCC62 VTT1_58 VCCPLL2 + 1.8VS

V28 AL33 H _ V ID4

V26 AM35 H _ V ID6

R28 AJ34 VCCSENSE

38 S LP_S3 S LP_S3 2 Q92

S ecurity Classification Compal Secret Data Compal Electronics, Inc.

S ecurity Classification Compal Secret Data Compal Electronics, Inc.

+ V R E F _ D Q_DIMMA +1.5V + 1.5V

D D R _ A _MA9 A12/BC# A11 D D R _ A _MA7

201 202 S M B _CLK_S3 +1.5V

1 1 203 204 + 0.75VS

205 206 0 . 6 5 A @0.75V

TOP SLOT S M B _DATA_S3

6 D D R _ C K E 2 _DIMMB D D R _ C K E 2 _DIMMB 73 74 D D R _ C K E 3 _DIMMB

201 202 S M B _CLK_S3

+ 3 VS_CK505 + 1.05VS_CK505 + 3 VS_CK505 + 1 .05VS_CK505

+ 1.05VS + 1 .05VS_CK505 + 3VS_CK505 + 3 VS + 3 VS_CK505 R 1214 1 @ 2 0_0603_5%

S ecurity Classification Compal Secret Data Compal Electronics, Inc.

T127 P C H _ R T C RST# W=20mils 3 1 2

C 1 90 C 191 C 215 D A N 2 02U_SC70 1K_0402_5%

Y3 1 P C H _ RTCX1 B13 D33 L P C _LAD0 28,33,35,36

RTCX2 FWH1 / LAD1 L P C _LAD1 28,33,35,36

R 1027 1 2 15_0402_5% P C H _ S PI_SI AY1 Y9 S A TA_DET#0 H D D _ H A L TLED

GND6 GND7 2009/02/16 HP DB-2