Power Supply Design Seminar

Exposing the Inner Behavior of a

Quasi-Resonant Flyback Converter

Reproduced from
2012 Texas Instruments Power Supply Design Seminar
SEM2000, Topic 3
TI Literature Number: SLUP302

© 2012, 2013 Texas Instruments Incorporated

Power Seminar topics and online power-

training modules are available at:
ti.com/psds
 Exposing the Inner Behavior of a
Quasi-Resonant Flyback Converter
Lisa Dinwoodie

Abstract

Deciding that a flyback converter is the best choice for a given application is just the beginning of a long
list of decisions you need to make when designing a power converter to meet specific requirements. Each
choice in the design process will affect the performance and overall efficiency of the final product. But as
each specified requirement rises to the top of your must-have list, the inevitable compromises will impact
other requirements. In this paper, I’ll present a simple and practical discussion about the decisions you
must make during the design flow, and how to live with your choices.

Topic 3
I. Introduction
The overwhelming majority of isolated power required for discontinuous current is smaller than
supplies less than 50 Watts (W) are flybacks. that required for continuous current. DCM
Flyback converters are ideal for set-top boxes flybacks are also easier to compensate because
(typically 10 W to 35 W), chargers and auxiliary their right half-plane zero is beyond the half-
bias supplies (3 W to 5 W). They’re also common switching frequency of the converter – something
in notebook computers, which can require as much that can’t be said for CCM flybacks.
as 120 W of power. Lest you get the impression that flybacks are
Flyback converters offer many advantages perfect and should be used everywhere, you will
over other topologies that compete for this low- to have to make compromises if you choose this
mid-power range. The single magnetic component topology. That single magnetic that heretofore has
used in a flyback converter – although commonly been so good at providing multiple outputs,
referred to as a transformer – behaves as a coupled ensuring isolation and reducing overall parts
inductor, combining the functions of energy count? It is actually poorly utilized and fairly
storage, energy transfer and isolation. Eliminating bulky when compared to other converters at the
the need for a separate LC filter on each output same power level because it provides energy
greatly reduces the overall cost of multiple output storage as well as energy transfer. Cross-regulation
designs. of the outputs is dependent upon the coupled
Cost alone makes flyback converters a inductance and output load. Lightly loaded slave
preferred topology in today’s mass-market windings will tend to have higher output voltages
production world. But its advantages don’t stop when the main output is heavily loaded. Because
with the bill of materials. This superhero of of this, a post-regulator is often used when tight
converter topologies can accommodate a wide- voltage regulation is required on each output.
input voltage range and have outputs higher or DCM flybacks, although easy to compensate,
lower than the input voltage; the number of outputs have very high peak currents and sharp switching
is limited only by the number of available pins on edges that require large input filters in order to
the transformer bobbin. meet electromagnetic interference (EMI)
Discontinuous current-mode (DCM) flybacks standards. These high peak currents also reduce
offer better line and load transient response when the practical power limitation of flybacks. A
compared to continuous current-mode (CCM) 500-W flyback may be theoretically possible, but
flybacks, primarily because the inductance problems will arise when trying to find space for

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 that bank of output capacitors that you will need to
meet the resultant huge output current ripple.
Applicable power is also limited because the
primary inductance value is inversely proportional
to the required power. High power will require a
relatively tiny inductance, but it is just not sensible
to use an inductance so small that the circuit
parasitics will completely dominate. That would
lead to an unreliable design that would never be
robust enough to be practical in a mass-market
production lot.
Even when considering the drawbacks, power
supplies that are within the appropriate power
range, are cost-conscious, have a nominal number
of outputs and require isolation are ideal candidates
for flybacks. But once you’ve selected the flyback,
Topic 3

the decisions made while winding down the design

path should exploit its advantages and mitigate its
less-than-ideal aspects so that a reliable, cost-
effective and efficient converter is the result.

A. Quasi-What? Figure 1 – Power waveforms of a typical resonant

There have been many papers already written converter.
about flybacks. For the 2010-2011 Power Supply
Design Seminar, Jean Picard’s “Under the Hood of A quasi-resonant converter is sort of like a
Flyback SMPS Designs” detailed the influence of resonant converter, but not quite. The power
parasitics on flyback behavior; most switched- waveforms in a quasi converter aren’t sinusoidal
mode power supply design textbooks cover like in a true resonant converter; a QR flyback still
flyback converter basics extensively. (See the retains the distinct, familiar flyback waveform
references section at the end of this paper.) But this shapes. The difference between a QR flyback and
particular discussion is about quasi-resonant (QR) a traditional flyback is simply that the irritating
flyback converters. ringing caused by the circuit parasitics is put to
What exactly is a QR flyback? Start with the actual use. The resonance referred to as “quasi” is
adjective quasi, which means “having some not contained in the power portion of the switching
resemblance usually by possession of certain cycle, but after the core has demagnetized, in the
attributes” or “resembling in some degree.” In dead time; this resonant ringing is used as an
“Resonant Mode Converter Topologies,” from the indicator for the controller to initiate the next
1988 Power Supply Design Seminar, Bob switching cycle.
Mammano described a resonant converter as a Because there is no dead time in CCM
power-conditioning system that uses a resonant flybacks, QR flybacks are forced to operate in
LC circuit as part of the conversion process. A DCM or on the edge of DCM/CCM operation,
resonant converter is a converter whose switching referred to as transition mode (TM) or critical
occurs when the sinusoidal-shaped voltage and/or conduction mode. Figure 2 shows the difference
current goes through zero, resulting in an almost between the drain-to-source waveform of a DCM
lossless transition. The power waveforms of flyback that does not switch on the resonant valley
resonant converters are sinusoidal. Figure 1 shows and a TM flyback that does switch on the resonant
an example in the waveform shape of the drain valley.
current, ID.

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Figure 2 – Comparison of drain-to-source voltage waveforms of DCM and TM flybacks.

B. The Quasi-Resonant Advantage

A quasi-resonant converter is actually a soft- Another advantage to soft switching is that
switcher; utilizing an available resonant LC, the there will be less generated conducted and radiated

Topic 3
switching occurs at the valley of the resonant ring EMI. Voltage ripple on the input capacitor results
generated by the primary inductance and the in slight variations in the switching frequency
parasitic capacitance of the circuit. Thus, its initial because the valley is a moving target. The dithering
advantage could be its resourcefulness; there’s no that results from hunting for and switching on an
need to add Ls and Cs because this circuit uses available valley spreads the radio frequency
what is already there. Quasi-resonant describes the spectrum and reduces EMI. The required EMI
soft switching action of the metal-oxide filter may be a bit more challenging to design,
semiconductor field-effect transistor (MOSFET). however, because there isn’t just one switching
Soft switching has many advantages, most frequency to filter but a range of switching
notably the reduction of switching losses. Turning frequencies. Despite this challenge, the filter will
on the MOSFET switch at the valley of the still be smaller, saving on overall cost and size.
resonant ring – where the drain-to-source voltage Table 1 summarizes the differences between a
is lowest – results in lower losses associated with hard-switching traditional flyback and a soft-
the output capacitance of the MOSFET. switching QR flyback.

Flyback Feature Comparison

Operating Advantage Disadvantages
Quasi-Resonant • Lower Switching Losses • Poor Transformer Utilization
• Smaller EMI Filter • Poor Cross-Regulation
• Low Parts Count = Low Cost • Limited to DCM or TM
• Isolated • Challenging EMI Filter Design
• Multiple Outputs • Limited to Low to Medium Power Levels
• Operates Over a Wide Input Range
• Better Transient Response (DCM)
• Easier to Compensate (DCM)
Traditional • Low Parts Count = Low Cost • Poor Transformer Utilization
• Isolated • Poor Cross-Regulation
• Multiple Outputs • CCM Challenging to Compensate
• Operates Over a Wide Input Range • Large EMI Filter
• DCM, CCM or TM • Limited to Low to Medium Power Levels
Table 1 – Comparison between traditional and QR flyback converter features.

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 VBULK DOUT
VAC – +
LP IOUT
ISEC VOUT
CIN NP NS COUT
IPRI
NB

Q D

G CPARASITIC
S
Topic 3

Figure 3 – QR flyback power stage.

II. The QR Flyback Power Stage

Figure 3 shows the power stage of a QR provide bias to the primary-side controller. This
flyback. Looking closely, it doesn’t seem any bias winding also gives an accurate, scaled-down,
different from a traditional flyback; all of the basic offset view of the primary-side switching
building blocks are there, with no major circuit waveform.
changes or additions. The power stage has an QR flybacks must operate in DCM or TM, but
input capacitor, CIN, that determines the minimum the only way to do this is to have some way of
bulk voltage, VBULK(min), due to input voltage detecting when the flyback coupled inductor, or
ripple. Equation 1 shows that VBULK is equal to transformer, has completely reset. The bias
the rectified and filtered input AC voltage: winding creates an ideal signal to indicate when
the core has completely demagnetized. A
VBULK = 2 × VAC (1) specialized controller that senses this transformer
reset status is required in order to take advantage
The coupled inductor fulfills the energy- of this information. Texas Instruments’ UCC28600,
storage and energy-transfer functions and provides UCC28610, TPS92070, TPS92210 and TPS92010
input-to-output isolation. The MOSFET switch, controllers are all designed to detect the end of the
Q, allows the primary-side current, IPRI, to flow. demagnetization time of the flyback power stage.
The turns ratio of the primary winding, NP, to the The parasitic capacitance depicted in Figure 3
secondary winding, NS, sets the output voltage, represents the sum of the output capacitance,
VOUT. The rectifying diode, DOUT, feeds the COSS, of Q, the reflected junction capacitance of
secondary side current, ISEC, to the output DOUT, the winding capacitance of the flyback
capacitor, COUT, and to the load. inductor, the capacitance of Q’s package, and the
The turns ratio of the secondary winding, NS, capacitance of the heatsink that Q may be mounted
to the bias winding, NB, sets the voltage that will to:
CPARASITIC = COSS + CDIODEreflected + C WINDING + CQpackage + CHEATSINK (2)

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 Note that most of the components of The on-time is complete when the primary current
CPARASITIC in Equation 2 are unknown and has ramped up to its designed peak threshold.
difficult to characterize. This parasitic capacitance, Figure 5 highlights the significant current and
along with the primary inductance, LP, is the cause voltage waveforms during the on-time of Q.
of the resonant ring that is represented on the bias
winding and used by the controller to mark the
point at which the core is demagnetized. As I will
show in the example, an initial assumption for the tON
tSW
tDEMAG tRES
period of this resonance is required at the onset of
the design process. GATE
DRIVE

A. Flyback Fundamentals IPRI

The following brief discussion provides a
basic description of a typical switching cycle of a
ISEC
peak-current-mode-controlled DCM flyback
converter. Starting the cycle when the switch, Q, is

Topic 3
turned on, the current on the primary side ramps
up at a slope that is a function of the input bulk VDS VBULK
voltage and the primary inductance according to
Equation 3.
dIPRIramp V (3)
VOUT

= BULK
dt Lp
VSEC

As noted earlier, the transformer behaves like

a coupled inductor; current does not flow through
the primary and any of the secondary windings at Figure 5 – Current and voltage waveforms
the same time. During the on-time of Q, current is highlighting the on-time of Q.
flowing in the primary winding but not the
secondary windings. As a result, energy will be Once the primary current has ramped up to its
stored in the inductance of the primary (more peak value, the switch, Q, is turned off. A
specifically, in the gap) because it can’t go representation of the converter with Q off is shown
anywhere else. Referring to Figure 4, the dot ends in Figure 6. Figure 7 highlights the current and
of the transformer are more negative than the voltage waveforms during the demagnetizing
undotted ends. The output diode, DOUT, is reverse- portion of the switching cycle.
biased and in blocking mode.
Because no current is actually flowing through VBULK DOUT
the secondary windings, all of the output load VAC – +
LP ISEC IOUT V
current must be supplied by the output capacitor. CIN NP NS COUT
OUT

IPRI
D
VBULK DOUT
VAC – + Q CPARASITIC
LP
ISEC IOUT V S
CIN NP NS OUT
COUT

IPRI
D
Figure 6 – The switch, Q, is off. The bias winding
Q
S
is not shown.

Figure 4 – The switch, Q, is on. The bias winding

is not shown.
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 output voltage and the primary inductance
(Equation 5).
tSW
tON tDEM AG tRES
dISECramp VOUT
= −(N PS )2 ×
GATE
DRIVE
dt LP (5)
NP
N PS =
IPRI NS

Demagnetization is complete when the

ISEC
secondary current has ramped all the way down to
zero. When the core has completely demagnetized,
the energy stored in the parasitic capacitance will
VDS VBULK form a resonant tank with the primary inductance.
The resonant frequency is equal to Equation 6.
1
VOUT fRES = (6)
2 × π × L P × CPARASITIC
Topic 3

VSEC

B. The Difference
The turn-off event does not change, regardless
of whether the converter is a traditional peak-
Figure 7 – Current and voltage waveforms, current-mode-controlled DCM flyback or a peak-
highlighting the demagnetizing time when current-mode-controlled QR flyback. Both
Q is off. versions will turn Q off when the primary current
ramps up to a designed peak value. Both versions
With Q off, no current can flow in the primary. are operating in DCM, so the turn on will be after
The drain voltage, VDS, rises to a value equal to all of the energy has been transferred.
the bulk input plus the reflected output voltage, The difference is soft switching verses hard
referred to as the flyback voltage, in addition to switching. In a traditional flyback, the fixed-
the voltage spike from the transformer’s leakage frequency oscillator initiates the next switching
inductance (see Equation 4). cycle. Because this turn on is completely dependent
upon the oscillator, turn on could be at any point
VDS = VBULK + VFLYBACK + VLEAKAGE (4) during the resonant ringing of the primary
inductance and parasitic capacitance. There’s a 50
The high-frequency ringing on the drain is a percent chance that turn on will occur when the
result of the resonance between the leakage drain voltage, VDS, is higher than the input bulk
inductance and the parasitic capacitance. The voltage, and it may be after many resonant ringing
voltage across the secondary windings rises above cycles depending upon the operating conditions.
ground; now the dot ends of the transformer The QR flyback initiates the next turn-on cycle
windings are more positive than the undotted only after a resonant valley is detected. The
ends. The output diode, DOUT, is forward-biased switching frequency is modulated. Theoretically, a
and begins to conduct, allowing the transformer to quasi-resonant controller does not need an
demagnetize. The secondary current, ISEC, supplies oscillator; it just needs to detect a valley. The
the load and recharges the output capacitor during deepest valley occurs at the first resonant ring
this demagnetizing time. The current on the where the drain voltage, VDS, could potentially
secondary ramps downward, decreasing as a swing down to a level as low as the bulk input
function the primary-to-secondary turns ratio, the voltage minus the flyback voltage.

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 Designing the power stage to operate at critical several resonant cycles because the switching
conduction mode at full load to take advantage of frequency is ultimately a function of the required
this low valley voltage will result in the lowest energy transfer. But even if the first resonant
capacitive switching losses because these losses valley is missed, the QR converter will switch at
are calculated in Equation 7. the next available valley. As a result, switching
1 will never occur when the drain voltage, VDS, is
PCAPACTIVE _ SWITCHING _ LOSSES = × CPARASITIC × VDS
2
× fSW greater than the input voltage.
2
(7)
At this operating point, the switching frequency III. Choosing the controller
will consist of the on-time, the demagnetizing Different quasi-resonant controllers use
time, and one half of the resonant period. Compare different modulation methods to achieve
Figure 9, showing the QR switching waveforms, regulation. It is important to understand the basic
with the previous figures showing the traditional premise under which any particular controller
flyback switching waveforms (Figures 6 and 8) operates. The controller will determine the
and notice where the switch is turned on (and what operating mode based upon input voltage and load
the voltage of VDS is) to appreciate the considerable current. All of the controllers rely on the switching

Topic 3
impact on overall efficiency switching at a valley waveform for valley detection, either by detecting
will have, especially considering this voltage is a change in slope or a zero-crossing threshold; as a
squared. result, all of the controllers force DCM.
tS W
Some controllers, such as the UCC28600 and
tON tDEMAG tR ES TPS92070, will modulate both the switching
GATE frequency and the peak primary current over most
of the operating range. Other controllers, such as
DRIVE

the UCC28610 and TPS92210, will modulate the

IPRI switching frequency but maintain constant peak
primary current over much of the operating range.
There are subtle differences to the design approach
ISEC based upon the specific controller’s modulation
method.

A. Frequency and Peak Current

Modulated
VDS VBULK Some QR flyback controllers will modulate
both the switching frequency and the peak primary
current for a given input voltage and load range.
VOUT When operating in TM, the switching frequency
will increase as the load decreases. Also, for the
VSEC
same load, the switching frequency will be higher
for higher-input voltages. The peak primary
current is also modulated while operating in TM.
Figure 8 – Current and voltage waveforms of a As the output load decreases, the peak current
QR flyback at critical conduction. decreases. This makes it very difficult to calculate
the switching frequency and peak current at any
The on-time and demagnetizing time did not specific operating point.
change when compared to Figures 5 or 7, but the As Michael Madigan explained in his 2006
resonant time and (as a result) switching period Power Supply Design Seminar paper, “Green-
changed. At lighter loads, switching may wait for Mode Power by the Milli-Watt,” solving a cubic

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 equation is necessary to determine the peak The importance of a maximum frequency
primary current; the peak primary current is then clamp is subtly implied in Figure 9. Note that
used to calculate the switching frequency for this without this fmaxCLAMP, the switching frequency
type of controller. Because the peak current varies would increase at a rapid rate as the output load
with input voltage, the power limit will be decreased. The unlimited increase in the switching
unavoidably input-voltage dependent. frequency would be, to put it plainly, very bad.
Figure 9 shows the relationship of the Power losses at light loads would be
switching frequency and peak primary current as a disproportionately high despite the modulated
function of the input bulk voltage and output load peak current, thanks to the switching losses in the
for a converter that modulates both frequency and MOSFET and the output diode, along with the
current in order to establish regulation. higher core losses (all functions of switching
frequency).
The size of the input EMI filter would have to
f maxCLAM P
DCM
be much larger for increased switching frequencies.
TM
Because of this, the chosen controller will clamp
VBULKm ax
the maximum switching frequency and prevent
Topic 3

TM
the unlimited rise in frequency as the load
FFM

decreases. The upper limit of this clamp should be

FFM

fS W VBULKm in less than 150 kHz so that the input filter can be
relatively small but still meet EMI limits. The
converter will operate in DCM while switching at
f minCLAM P
Hysteretic
the clamp level; the frequency will be relatively
No load Output Power Full load
constant while the peak current is modulated. The
VBULKm in current is “relatively constant” specifically
because the controller will still be hunting for the
VBULKm ax
I P RI peak resonant valley in order to switch. The actual
switching frequency from one cycle to the next
No load Output Power Full load
may dither within the range of one-half of the
resonant period of the LPCPARASITIC ringing.
Figure 9 – Switching frequency and peak primary To further maintain efficiency, as the load is
current of a frequency- and current-modulated decreased, the controller will transition into
QR converter. The Texas Instruments UCC28600 frequency foldback mode (FFM) when the load
is an example of this type of controller. and input voltage demand a lower switching
frequency than the clamped DCM level, although
As the load decreases from its maximum full- switching will still occur at the resonant valley. In
load design point, the switching frequency FFM, the switching frequency is modulated but
increases. Why would the frequency be lower if the peak current is held constant. This mode of
the output power is higher? Higher power means operation may pose a problem for the regulation of
that a longer on-time is required to store the higher multiple outputs, as the switching period is
energy, and thus a longer demagnetizing time to increasing with a constant on-time and ensuing
transfer the higher energy. A longer on-time and constant demagnetizing time. The drop in overall
longer demagnetizing time will result in a longer percentage of demagnetizing time with respect to
switching period and reduced switching frequency. the switching period will result in lower voltages
At a higher input voltage, the same amount of of the bias winding and other slaves during light
energy can be stored and transferred in a shorter load conditions when compared to full load. With
amount of time, so the switching frequency for the a further reduction in load, the controller will
same load will be greater. operate down to its lower frequency clamp,
fminCLAMP, in hysteretic mode in order to minimize

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the light load and no-load power consumption that frequency at any given operating point becomes
is so important to meet green initiatives. much easier. With decreasing load, the switching
When designing with QR flyback controllers frequency will decrease, which will result in
that modulate both the switching frequency and decreased switching losses. Another advantage is
the peak current as a function of line and load that power limit is no longer line-dependent, as the
conditions, it is best to size the transformer at the full load switching frequency and peak current do
minimum input voltage and maximum output not vary with input voltage but only with output
power operating point. When calculating the load.
optimum inductor value, assign the switching
frequency to be between the minimum and fmaxCLAM P VB ULKm in
maximum frequency clamps as a starting point for VB ULKm ax

the power-stage design. Experience shows that

setting the frequency too close to the minimum fS W
M
frequency clamp at maximum load and minimum FF

input will result in relatively high peak currents.

Also consider that you do not want transient HYSTERETIC

Topic 3
DCM
conditions, temperature or device tolerances to fminCLAM P
force the controller to try to operate at less than its No load Full load
fminCLAMP; skipped pulses and unstable conditions Output Power

may result.
Assigning too high of a switching frequency at IP RI peak

maximum load, minimum line will result in

transitioning out of TM and into DCM over most
No load Output Power Full load
of the input voltage range and maximum load.
Although still reaping the benefits of resonant Figure 10 – Switching frequency and peak
valley switching, the transformer will not be as primary current of a frequency-modulated,
well-utilized as it would be if the design started constant-current QR converter. The UCC28610
with an assigned switching frequency at minimum is an example of this type of controller.
line, maximum load that was at a more optimum
point: mid-level between the maximum and Frequency-modulated, constant-current QR
minimum clamps. controllers still require maximum and minimum
frequency clamps. The maximum frequency clamp
B. Frequency Modulated, Constant provided by the controller will be less than 150
Current kHz for the same EMI benefits stated earlier. The
In contrast, there are QR flyback controllers switching frequency will be limited to the
that only modulate the switching frequency while minimum clamp level when the load dictates
keeping the peak current constant over most of the transitioning into DCM, peak current amplitude
operating range. As shown in Figure 10, these modulation, and then to hysteretic light load and
controllers essentially force FFM mode and then, no-load operation.
as the output load decreases, transition into DCM, When designing with QR flyback controllers
where the switching frequency is constant and the that modulate the switching frequency but
amplitude of the peak current is modulated. maintain constant peak current as a function of
Throughout FFM and DCM, the controller load conditions, it is best to size the transformer at
will switch at an available resonant valley. Because the minimum input voltage, maximum output
the peak current is fixed over the majority of the power, maximum frequency clamp operating
line and load range, calculating the switching point.

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 C. The Effect on EMI frequency, this same amount of energy is
Flybacks are noisy. They are isolated supplies distributed over a wider range. The resultant peaks
and will generate common- and differential-mode are lower, as shown in Figure 11.
noise. Traditional hard-switching flybacks have
fast rising and falling edges. Increasing the IV. The Design Requirements
switching speed has been known to help improve Assuming that the design is suitable for a
efficiency but creates a major source of noise. The quasi-resonant flyback, being aware of all of the
high current and voltage through the transformer requirements of the end product is very important.
will generate strong EMI fields that will require Simply knowing the basics (such as input voltage,
extensive filtering. line frequency, output voltage and output current)
In the October 2007 edition of Electronics will get you started, but you may not end up with
Components World, L. Haachitaba Mweene an appropriate design that meets all of the
pointed out in his article, “Spread Spectrum specifications. Are there cost constraints?
Switching Improves EMI Compliance in Efficiency, size and ambient temperature will
Switching Power Converters,” that although the impact your component choices. EMI
design of an EMI filter for a fixed-frequency compatibility, safety and isolation requirements
Topic 3

converter is relatively easy thanks to the well- will have an impact on layout and should be
defined frequencies under all operating conditions, accommodated at the onset of the design process.
passing EMI is difficult because the excess energy Hold-up requirements and whether or not power
is concentrated at narrow frequency bands. factor correction is needed will dictate input
QR converters help mitigate conducted and capacitor selection. Output ripple requirements,
radiated noise by switching at the resonant valley, overvoltage protection, short-circuit protection,
which softens the switching action due to the load transients and regulation may require
lower voltage switching. Hunting for the valley additional circuitry. The more information you
results in cycle-to-cycle dithering, which spreads have at the beginning of the design, the better your
out the frequency spectrum. Instead of choices will be as the design progresses.
concentrating the excess energy at a narrow
A. The Design Strategy
-40
Non -Dither Figure 12 shows the design process as a series
of decisions, and the results of the calculations
based upon those decisions. The design example
-50 in this paper will follow the path shown in Figure
Magnitude (dB)

12.
Dither
-60

-70

-80
fSW

Frequency (kHz)

Figure 11 – Comparison of the noise spectrum of

a fixed-frequency non-dithering converter with a
QR converter that searches for a valley in order
to switch, resulting in dithering.

Texas Instruments 3-11 SLUP302

 The Design Decision 1: Decision 2:
Requirements Minimum CIN Flyback
Bulk Voltage Voltage

Decision 3: Decision 4:
NPS fSW tON
Controller Assume tRES

IPRIpeak Decision 5: Build

LP NPB
Bias Voltage Inductor

Topic 3
Decision 6: Decision 7:
COUT
MOSFET Diode or SR

Figure 12 – The design path used in the example.

PARAMETER REQUIREMENT
V ACmin = 85 V RMS V. The Design Example
Input Voltage
V ACmax = 265 V RMS The remainder of this paper will be devoted to
fLINEmin = 47 Hz a step-by-step procedure for designing a quasi-
Line Frequency resonant flyback converter. The specific
fLINEmax = 63 Hz
requirements listed in Table 2 will be used for this
Output Voltage V OUT = 5 V
design example and shown with the design
Output Current IOUT = 2 A calculations. All of the equations used in this
Output Peak Power POUTpeak = POUTmax = 10 W procedure can be directly applied to similar
Cost Low designs by modifying the values shown. The
Efficiency h > 0.8 parameters that are outside of the scope of this
Size Small topic, such as EMI filter design, will not be
EMI Compatibility n/a addressed.
Safety Requirements n/a
Temperature Ambient, No Air Flow
Hold Up No
Output Ripple V OUTripple = 0.15 V PP
Overvoltage Threshold V OVP = 6 V
PFC n/a
Reliability Of Course
Load Transient Full Range
Regulation ± 10%
Brown Out V BROWNOUT = 80 V RMS

Table 2 – The specifications for the design

example, similar to the requirements for a typical
tablet charger (see Appendix A). The term n/a
means “not addressed.”

Texas Instruments 3-12 SLUP302

 A. Decision 1: VBULKmin The discharge time is calculated with Equation
The rectified AC input voltage is filtered by 8 using the minimum line frequency and timing
the input capacitor, CIN, to establish the bulk factors depicted in Figure 13:
voltage, VBULK, which will be the input to the tCHARGE
power stage of the converter. The power stage for tDISCHARGE
a reliable and robust design should be based upon VACmin(peak)
the minimum bulk voltage VBULKmin, which is at V C in
VBULKmin
the valley of the VBULK ripple at the lowest AC
input, VACmin. Because the power stage is so
dependent upon this minimum voltage operating
I C INripple
point, and the input capacitor for an offline supply t
t1 TLINE/4 TLINE/2 t2 TLINE
takes up a considerable amount of real estate on
the printed circuit board due to its voltage rating, it Figure 13 – Input capacitor voltage and current
is wise to choose this component first. waveforms.
There are trade-offs to consider for this first
component. Using the smallest and cheapest input TLINE  VBULK min  (8)
t1 = × sin −1 
Topic 3

2π 
capacitor will result in a lower bulk voltage and  2 × VACmin 
higher peak currents. There will be more stress on
TLINE
the MOSFET, the transformer and the output = + t1
capacitor thanks to these higher currents. Using a 2
larger input capacitor isn’t an ideal solution either, TLINE
t DISCHARGE = t 2 −
as the peak current drawn from the mains will be 4
higher due to the reduced charge time. The input fLINE = 47 Hz
capacitor itself will need to be rated for this ripple TLINE = 21 ms
current and will be physically larger. An acceptable
compromise is to use an input capacitor that will t DISCHARGE = 7.95 ms
limit the input voltage ripple to 20 to 30 percent.
For this design example, specified in Table 2, the Rearranging the energy balance equation
minimum bulk voltage calculation is: allows the ideal CIN value to be calculated per
Equation 9:
VBULK min = 0.7 × 2 × VACmin 2 × PIN × t DISCHARGE
VBULK min = 84 V CIN = (9)
( )
2
2 × VACmin − VBULK
2
min

To achieve this voltage, the input capacitor is POUT

calculated using the energy balance equation, PIN =
η
considering that the energy gained during the
capacitor charge time will be delivered to the CIN = 27 µF
power stage during the capacitor discharge time:
1 Of course, the design specification shown in
( )
2
× CIN ×  2 × VACmin − V2BULK min  = PIN × t DISCHARGE Table 2 requires a low-cost small converter as the
2  
final result. Because of this – and because 27 µF is
To calculate tDISCHARGE, refer to Figure 13, not a standard value – you would expect that the
where you can see that the capacitor discharge actual capacitor used in the design would be the
time is equal to the time it takes for the capacitor next lower standard value available. This would
voltage to drop from its peak value to the desired be equal to 22 µF. But because a lower-than-
minimum bulk voltage. calculated input capacitor is selected, it is wise to
determine the actual minimum bulk voltage and
iterate the calculations starting at the t1 equation.

Texas Instruments 3-13 SLUP302

 After a few iterations, the calculated CIN value There are merits to this approach, as choosing
converges with the actual CIN used and that VFLYBACK to be as high as the maximum bulk
determines the actual minimum bulk voltage. The input voltage will result in zero voltage switching
iteration begins (and will ultimately end) by (ZVS) over the entire operating range, which will
determining VBULKmin in Equation 10, assuming minimize switching losses. However, this will
the same tDISCHARGE as calculated in the previous impose a huge voltage stress on the MOSFET and
step: it will have to be rated for more than twice the
2 × CIN × (CIN × VACmin
2
− PIN × t DISCHARGE ) maximum bulk voltage plus the leakage inductance
VBULK min = spike; higher-voltage-rated devices tend to cost
CIN more than lower-voltage devices. A high-voltage
(10) MOSFET will have a higher on-resistance, RDSon,
and higher gate capacitance when compared to a
After three iterations, using a 22-µF capacitor MOSFET rated for a lower voltage. As a result,
yields a VBULKmin of 76 V. Because heating caused choosing a higher VFLYBACK will gain you lower
by ripple current is the leading cause of failure in switching losses but higher conduction losses and
capacitors, it is necessary to calculate the peak higher component cost.

Topic 3
current ripple and estimate the rms ripple current Choosing VFLYBACK to be lower than the input
for which the input capacitor must be rated. bulk voltage allows you to use a lower-voltage-
Looking at the current waveform shown in Figure rated MOSFET, with lower RDSon, lower gate
13, a conservative approximation for the ripple capacitance and lower component cost. Because
current is calculated with Equation 11 as: this is a QR flyback, choosing a lower VFLYBACK
will eliminate ZVS switching, but the sacrifice
Q t CHARGE × ICINpeak (11) will be minimized, thanks to valley switching.
CIN = = For a more practical approach, consider that
V 2 × VACmin − VBULK min
the flyback voltage, VFLYBACK, will impact not
TLINE
t CHARGE = − t1 only the MOSFET rating but also the blocking
4 stress on the output diode and whether a

ICINpeak =
CIN × ( 2 × VACmin − VBULK min ) synchronous rectifier (SR) can be used on the
output. As the flyback voltage decreases, the
t CHARGE blocking voltage stress on the output diode
ICINpeak increases. The flyback voltage is directly
ICINrms =
3 proportional to the primary-to-secondary turns
ratio, NPS, whereas the output rectifier’s blocking
For this design example, the peak input current, voltage is inversely proportional to the same turns
ICINpeak, is equal to 0.323 A, with a corresponding ratio.
rms ripple current of 0.187 A. The desire for high efficiency requires a little
foresight to the secondary-side design. The output
B. Decision 2: VFLYBACK diode, DOUT, is a major contributor to poor
Most flyback converter designs select efficiency. The design example will use secondary-
VFLYBACK based upon the voltage stress on the side rectification for improved efficiency and a
MOSFET drain, VDS, which has already been controller will be used to drive the synchronous
defined in Equation 4 as: rectifier. The blocking voltage is limited to the
absolute maximum rating of the drain of the
VDS = VBULK + VFLYBACK + VLEAKAGE secondary-side rectifier, VDrating, which is equal to
50 V (see the data sheet “UCC24610 Green
Rectifier Controller Device,” TI literature No.
SLUSA87). By limiting the blocking voltage to 70
percent of the absolute maximum value allowed
by the secondary-side controller to accommodate

Texas Instruments 3-14 SLUP302

 the voltage spike due to leakage inductance, NPS is D. Decision 4: tRES
set and VFLYBACK is established as shown in The resonance created by the primary
Equations 12-14, assuming that VF is equal to the inductance and parasitic capacitance must last for
forward voltage drop of DOUT or the forward drop a long-enough time so that the waveform can ring
of the SR body diode: down to a level that the controller can interpret as
indication that another switching cycle can begin.
VDblocking _ max = 0.7 × VABSMAX (12) This time, tRES, is equal to at least one-half of the
VABSMAX = 50 V resonant period – which is the time to transition
from peak to valley. The switching period is equal
VDblocking _ max = 35 V to the inverse of fSW and (at its minimum, such as
during TM) must consist of the on-time, tON, the
demagnetizing time, tDEMAG, and tRES (Equation
VBULK max
N PS = 15):
VDblocking _ max − VOUT (13) TSW = t ON + t DEMAG + t RES (15)
VBULK max = 2 × VACmax Unfortunately, as mentioned earlier, the
Topic 3

N PS = 12.492 parasitics that make up the capacitance causing

this resonance are essentially unknown, so tRES is
assumed with an initial value. Luckily, by
VFLYBACK = N PS × ( VOUT + VF ) designing for mass market and using worst-case
(14) values as opposed to typical values, this guess for
VF = 0.6 V
tRES will be close enough with minimal design
VFLYBACK = 70 V impact and can be measured and verified once
the converter is built. Assume that fRES will be
The actual turns ratio used in the design less than 1 MHz, so an initial assumption of
example was equal to 12, resulting in a VFLYBACK tRES=500 ns is a valid starting point.
of 67.2 V and a blocking voltage of 36.2 V.
I. Calculate tON, LP, IPRIpeak
C. Decision 3: Chose the Controller Figure 14 represents the volt second product
Controller choice defines the switching during the on-time and the volt second product
frequency for the power-stage calculations. QR during the demagnetizing time. During every
controllers that modulate the switching frequency switching cycle, the flyback transformer maintains
and set the peak primary current to a fixed value energy balance. Equating the on-time energy with
involve less complex calculations and are well- the demagnetizing energy (with respect to the
suited for low-power designs. Because the primary side) and then substituting for tDEMAG
UCC28610 (TI data sheet literature No. SLUS888) allows the calculation of tON. Equations 16-18
uses this control method, I selected it as the calculate the on-time for the specific design
controller for this design. The calculations for the example:
power stage will be based upon setting the (16)
switching frequency at minimum input voltage,
V ×t = N × V +V ×t
BULK min ON PS ( OUT F ) DEMAG

maximum load, at the minimum fmaxCLAMP value t DEMAG = TSW − t ON − t RES (17)
for the UCC28610 to ensure a reliable design. N PS × ( VOUT + VF ) × ( TSW − t RES )
t ON = (18)
1 VBULK min + N PS × ( VOUT + VF )
fSW = fmaxCLAMP = = 127 kHz t RES = 500 ns
7.875 µs
1
TSW = = 7.875 µs
fSW
t ON = 3.46 µs

Texas Instruments 3-15 SLUP302

 tSW Control also requires limitations of the
tON tDEM AG tRES
maximum on-time. If initial calculations for tON
and IPRIpeak fall outside the dynamic modulation
range of the controller, the value for LP must be
iterated so that regulation is achieved over the
VDS VBULK frequency range enveloped by the minimum and
maximum frequency clamps – all while satisfying
the maximum on-time, IPRIpeak, and power limit
tON for the specified input voltage range and output
power. The UCC28610 design calculator tool
VOUT + VF (UCC28610DESIGN-CALC) facilitates the
iterative calculations. After iterating to meet the
VSEC
controller’s requirements, the final results for LP,
tDEMAG IPRIpeak, tON and fSWmax calculated to be 191 µH,
1.16 A, 2.9 µs and 98 kHz, respectively.

Topic 3
E. Decision 5: VBIAS
As previously stated, the QR controller allows
Figure 14 – Volt seconds during the on-time must the switching cycle to begin only after
equal the volt seconds during the demagnetizing demagnetization has been detected. The bias
time for energy balance. winding plays a very important role in most QR
flyback converters. Not only must the bias be
After calculating the initial on-time, it is designed to supply the operating current to the
necessary to calculate the primary inductance, LP, controller, but it is also used to indicate when the
which will satisfy the energy requirement of the core has demagnetized and to detect an output-
load at the switching frequency set for the overvoltage. The winding is scaled down by the
minimum input voltage. Calculating the primary primary to bias turns ratio, NPB, so that the
inductance using Equations 19 and 20 is closely controller can directly monitor the switching
followed by the calculation of the resulting peak event, showing a high to low transition when
primary current, IPRIpeak: demagnetization is finished and the resonant ring
2
η × ( VBULK min × t ON ) × fSW has begun. Note that any filtering on this signal
LP = (19) will delay detection, so proper layout is always
2 × POUT better than external filtering. Excessive ringing
2 × POUT from the leakage inductance when the switch turns
IPRIpeak = (20) off must also be avoided. If this leakage inductance
η × L P × fSW
ringing is severe enough, it may cause the on-time
to be stunted. Low leakage inductance and good
Initial calculations result in a primary layout are always in order, but some snubbing may
inductance, LP, of 369 µH and a peak primary still be required.
current, IPRIpeak, of 0.713 A. Note that the During the off-time of the primary side, the
frequency-modulated, constant-peak-current bias winding will have a voltage on it that is
controller’s internal logic requires a 1-A minimum proportional to the reflected output voltage and is
and 4-A maximum programmed set value for the used for output overvoltage protection. Good
IPRIpeak current. This unmodulated peak current is coupling to the secondary winding is required for
attained at each cycle during FFM operation, an accurate signal. A series resistor will prevent
whether the output load demands 25 percent or peak charging of the energy storage capacitor on
100 percent of its rated value (as shown in Figure the bias pin of the controller; otherwise the voltage
9). The controller will modulate how often, but not level could rise and overvoltage the controller at
the level. turn on, especially at high line voltages. Always

Texas Instruments 3-16 SLUP302

 use an external zener clamp on VDD, even if the here. But some guidelines are necessary to ensure
controller indicates that one is present internally; a successful design. It is crucial that the bias
why dissipate more heat inside the control center winding is well-coupled to both the secondary and
than necessary? primary windings, as it plays such an important
Note that when the load is light on the role in determining the QR switching status and is
secondary output but still within FFM, the bias used for accurate fault detection. You should
winding will sag. This is because the controller interleave the bias and secondary windings
will be modulating the switching frequency to between the primary, as shown in Figure 15 – or
decrease as the load decreases, but the peak current better still, use a bifilar winding technique as
and on-time are held constant. This leads to a opposed to leaving the bias for the outermost
proportionally shorter demagnetizing time and layer. Using bundled stranded wire so that the
less energy transferred to the bias winding. Setting winding layers are distributed across the entire
the bias winding to 16 V is recommended in the width of the bobbin is also recommended.
data sheet for the UCC28610 green-mode flyback Excessive ringing due to leakage inductance
controller (TI literature No. SLUS888) for the must be avoided. To minimize the leakage
most efficient operation and will give enough inductance, use triple-insulated wire to satisfy the
Topic 3

headroom to avoid hitting the absolute maximum isolation requirements instead of layers of tape
rating during turn on and transitions. This setting barrier between the windings. Using a core with a
will also minimize the size of the capacitor needed round center post so that the wires lay well will
to hold up the voltage on the bias pin, VDD, reduce leakage.
during the light-load hysteretic mode of operation. The transformer is a major contributor to EMI.
The following calculations determine the Placing the end of the primary winding that is
primary to bias turns ratio, NPB, to set the bias connected to the MOSFET drain in the innermost
voltage. Admittedly, the bias voltage is directly layer, closest to the core, will help shield the dV/dt
related to the number of turns on the secondary, noise. Likewise, wind the secondary so that if
NS, but most magnetic manufacturers do not multiple layers are required, the outer layer is not
disclose the actual specific number of turns (such the switch node. Winding in this way may help
as NP, NS, NB) used in the manufacture of their avoid the need for a copper radiation shield, or
magnetics. They specify only the turns ratios with “belly band,” around the entire assembly. Adding
respect to the primary. In Equation 21, VF refers to a small capacitor (less than 100 pF) to primary
the output diode’s forward voltage drop; VFbias ground from the diode end of the bias winding will
refers to the forward voltage drop across the diode help divert noise out of the transformer. Gapping
used on the bias winding, assumed to be 0.7 V: only the center leg will reduce the radiated EMI
from fringing that would be present if the gap was
N PB =
(VOUT + VF ) × N PS (21) distributed across all of the outer legs.
VBIAS + VFbias
NP
N PB =
NB
Insulation Tape

One-Half Primary
VBIAS = 16 V Secondary,
N PB = 4 T riple-Insulated
Wire

Bias
i. More about the Magnetic
One-Half Primary
The design of a flyback inductor is covered in
Lou Diana’s “Practical Magnetic Design Inductors
and Coupled Inductors” from the 2012 Power Figure 15 – Recommended winding configuration
Supply Design Seminar, and will not be repeated for a QR flyback transformer, also known as a
flyback coupled inductor.

Texas Instruments 3-17 SLUP302

 A feature of this modulation method is that the frequency clamp becomes evident as the switching
switching frequency at any appreciable load is losses are directly proportional to the switching
beyond the audible range. During very light load frequency (Equation 23).
operation, when the converter is in hysteretic
 C × VDS
2
(VBULK max + VFLYBACK ) × IPRIpeak × t f 
mode, the packets of burst pulses may be within PFETswitching = fmax ×  OSS + 
 2 2 
the audible range but at such a low power level
that it should not be a problem. Any minor audible VBULK max = 2 × VACmax (23)
noise can be eliminated by filling the center gap As Figure 16 shows, DCM switching can
with flexible epoxy and varnishing the entire occur at any point on the resonant ring. The
magnetic assembly to reduce any mechanical waveform shown as “a” represents a hard switcher
chatter between the core, coil and bobbin. whose turn on occurs at the peak of the first
The magnetic specification for this specific resonant cycle, which could be almost as high as
flyback inductor, with manufacturing guidelines, the combined VBULK voltage with VFLYBACK. The
is shown in Appendix A. waveform shown as “b” depicts an ideal valley
switcher where the turn-on occurs at the first and
F. Decision 6: MOSFET deepest valley. The switching voltage at this point

Topic 3
The primary switch is selected to meet the could be almost as low as VBULK minus VFLYBACK.
drain to source, VDS, requirement; the peak Using a typical COSS of 143 pF and a tf of 10 ns for
primary and rms currents; and the allocated size both situations, the difference in the estimated
constraints, with enough derating for a robust switching losses is dramatic.
design. Conduction losses in the MOSFET will be For the situation where the MOSFET is turned
higher at the minimum bulk voltage because on at the peak of the first resonant cycle:
IPRIrms will increase with decreasing input while
the on-resistance, R DSon , increases with VDS = VBULK + VFLYBACK
temperature. Be sure to use the on-resistance PFETswitching = 1.6 W
specified for elevated temperature. Conduction
loss estimates are calculated in Equation 22 as: For the situation where the MOSFET is turned
on at the valley of the first resonant cycle:
PFETconduction = I2PRIrms × R DSon (22)
t ON VDS = VBULK − VFLYBACK
IPRIrms = IPRIpeak ×
3 × TSW PFETswitching = 1.0 W
IPRIrms = 0.356 A
R DSon = 1.2 Ω
PFETconduction = 0.152 W VDS
VFLYBACK

VBULK
The real appeal of QR converters is revealed in
the calculation of the MOSFET switching losses. a. b.
These losses are estimated assuming first-order Figure 16 – Comparison of VDS at turn-on for
effects where the output capacitance of the DCM (a) and QR valley switching (b).
MOSFET, COSS, is considered constant over all of
the operating conditions. The fall time, tf, of the G. Decision 7: DOUT
signal is estimated using the value reported in the By far, one of the lossiest components in an
MOSFET data sheet, and the losses associated offline QR flyback converter will be the output
with the off-time due to the MOSFET’s leakage diode because of the conduction losses from the
current, along with the gate drive losses, are high output current. Luckily, the output diode
considered small and negligible for these commutates off when the current reaches zero in
calculations. Appreciation for the maximum DCM so it will not have reverse recovery losses.

Texas Instruments 3-18 SLUP302

 There are two types of diodes that can be used sufficient margin for the previously calculated
for output rectification: ultra-fast or Schottky. blocking voltage. The rated voltage should
Ultra-fast diodes are cheaper, but their forward accommodate the reflected primary voltage
voltage drop is higher than Schottky diodes. The summed with the output voltage, and include
resulting conduction losses will be higher and may enough margin for the leakage inductance spike
require a large heat sink, creating a less-efficient, (Equation 24). If the device has a maximum-rated
more-expensive and bulkier design. To make reverse voltage that is less than adequate, the
matters worse, the fast switching from these diodes reverse leakage current will be beyond
creates radiated and conducted noise that will specification, as Schottky diodes become very
require filtering to meet EMI requirements. This leaky at elevated temperatures.
less-expensive device may require extra costly
components for adequate performance. V 
VBLOCKINGrated = 1.3 ×  BULK max + VOUT  (24)
Because a Schottky diode’s forward voltage  N PS 
drop is lower than typical p-n junction devices, it
is the rectifier of choice for overall efficiency. The diode also must be able to handle the peak
Unfortunately, the blocking voltage rating of current and the average current on the secondary
Topic 3

Schottky diodes doesn’t have the same range as side. The junction temperature, TJ, will exceed its
ultra-fast diodes. So if the turns ratio results in safe operating range if the load current rises
considerable blocking voltage, the option to use a beyond its maximum average forward current
Schottky may not be possible. rating. The entire load current goes through the
Another consideration is that Schottky diodes diode during each switching cycle. During
have a much higher junction capacitance that conduction, the diode current not only supplies the
requires charging and discharging over every load, but also re-charges the output capacitor with
cycle. Potentially, this capacitance could cause the current that the capacitor discharged while
ringing with any parasitic stray inductances supplying the load during the time the diode was
present. Table 3 compares these two popular reverse-biased. The reflected peak primary current
rectifiers. For most applications, if the blocking should never exceed the peak repetitive forward
voltage allows, Schottky diodes are usually current limit of the device (Equation 25).
chosen. The improved efficiency and reduced heat
dissipation are usually worth the added cost. ISECpeak = IPRIpeak × N PS (25)
The selected Schottky diode must have ISECpeak = 13.9 A

Parameter Ultra-fast Schottky Impact Power loss in the Schottky diode consists of
VF Higher Lower Conduction the summation of the conduction losses and the
Losses reverse leakage losses. Conduction-loss
dl/dt Faster Slower Switching Losses calculations are straightforward. Because all of the
Transition Noise load and replenished output capacitor current must
Cost Lower Higher Cost flow through the diode, the average forward
Blocking Higher Lower Power Stage current is equal to the steady-state load current.
Voltage Design (NPS) The reverse leakage losses result from the reverse
Heat Sink Larger Smaller Cost leakage current and the blocking voltage during
Capacitance Lower Higher Potential to the primary switch on-time (Equations 26 and 27):
Resonate
ISECavg = IOUT (26)
Table 3 – Comparing rectifier options for DOUT
ISECavg = 2 A
and the resulting design impact.
IDleakage = 2 mA

Texas Instruments 3-19 SLUP302

  t  Figure 18 compares the voltage drop across
(
PDIODE = VF × ISECavg ) +  IDleakage × VBLOCKING × ON 
 T 
the SR, equal to the product of the RDSon and the
SW secondary-side current, with that of a Schottky
PDIODE = 1.23 W (27) diode. MOSFETs used for this function have an
RDSon of typically less than 8 mΩ. This results in
The output diode has a brutal impact on the much less of a forward voltage drop across it than
efficiency of high-current converters. An output what the Schottky it replaced would have had,
current of 10 A across a typical 0.5-V forward which significantly reduces conduction losses.
voltage drop produces a huge amount of losses. The reduced losses result in a converter of smaller
Obviously, there must be a better alternative than size and weight, with less or even no heat sinking.
even a Schottky for high-current applications. The efficiency improvements extend beyond
the secondary side, as the currents across the
i. Decision 7: Or Synchronous transformer and through the primary side switch
Rectification? will be lower for the same energy transfer.
A more efficient option for the output rectifier Reliability is enhanced from the reduced
is to use synchronous rectification. SRs can only component stresses. Figure 19 shows the difference

Topic 3
work with QR controllers if they can be forced to in the measured power loss when a Schottky diode
behave as a diode and allow discontinuous is replaced by an SR, driven by the UCC24610, on
operation. A dedicated SR controller such as the the circuit used for this design example. The
UCC24610 (TI data sheet literature No. improved efficiency with the SR was approximately
SLUSQA87) or a discrete drive circuit are required 6 percent over the operating range of the converter
for proper function. The efficiency benefits of when compared to the Schottky.
using synchronous rectification justify the added
complexity and cost, especially for low-voltage,
high-current applications. To reduce the need for a
high-side driver – and still more complexity – ISEC
VDS = ISEC x RDSon
placing the SR on the return leg of the secondary
side, as shown in Figure 17, simplifies the design.
It also eliminates the need for another winding on
the transformer.

VDS_SR
VOUT

VDout VOUT
Figure 17 – Replacing DOUT with an SR is greatly
simplified when DOUT is on the return leg of the
secondary side.
-VF

Figure 18 – The shaded regions compare the

power dissipation of an SR with a Schottky.

Texas Instruments 3-20 SLUP302

 When the output rectifier turns on, current will
SR vs. Schottky Power Loss
4 flow into the capacitor, replenishing its charge.
3.5
SR, 115 VAC, 60 Hz When the output rectifier turns off, the capacitor
SR, 230 VAC, 50 Hz
3 Schottky, 115 VAC, 60 Hz supplies the load current to the output. COUT is
Power Loss (W)

2.5 Schottky, 230 VAC, 50 Hz selected to meet this ripple current requirement at
2
the converter’s switching frequency and operating
1.5
temperature. Chances are good that a single
1
0.5
capacitor will not be rated for the calculated
0 current, and several will be used in parallel to
0.5 1
Load Current (A)
1.5 2
form an output capacitor bank.

Figure 19 – Measured power loss, in the same  t DEMAG  ISECpeak

2

ICout = I +2
× − ISECpeak × IOUT  
 TSW  3
OUT
converter, of an SR compared with a Schottky  
diode.
ICout = 3.96 A
ii. COUT (28)
Topic 3

Thanks to the high ripple currents in DCM and

QR flyback converters, the output capacitor, COUT, The calculations for the output voltage ripple
experiences a relatively large amount of stress. shown in Equation 29 originate from the
The output capacitor should always be based upon combination of the capacitance ripple and the ESR
its working voltage rating, ripple current rating ripple. The ripple caused by the ESR of the
and equivalent series resistance (ESR). The capacitor will account for the majority of the
working voltage rating should be greater than the output ripple. The actual capacitance value of the
output overvoltage threshold, allowing margin for output capacitor bank used to meet the ripple
any overshoot during transients that may occur current requirement will be quite high, so it will
before the overvoltage protection, OVP, fault is contribute very little to the total output voltage
acted upon. The ESR is dependent upon the ripple (Equation 29).
capacitor’s thermal rating and is a function of the
capacitor’s I2R losses. VOUTripple = VrippleESR
2
+ VrippleCout
2
(29)
Aluminum electrolytic capacitors are the least VrippleESR = ISECpeak × ESR total
expensive and offer a lot of capacitance, but also
IOUT × t ON
occupy a lot of space due to their large size. They VrippleCout =
tend to have a wide tolerance range and their COUTtotal
capacitance decreases with temperature and age, ESR total = 9 mΩ
although it is possible to double the specified COUTtotal = 660 µF
lifetime of an aluminum electrolytic capacitor
VOUTripple = 125 mV
simply by reducing its temperature by 10°C.
Tantalums are physically smaller than aluminums
but only have moderate capacitance values. If the resulting output ripple exceeds the
Multilayer ceramic capacitors have very low ESR, desired specification, you can add an output LC
enabling them to handle a lot of ripple current. But filter. The two-stage design can have ceramic
they are only available in a few hundred capacitors on the first stage to handle the high
microfarads or less and tend to be very costly. ripple currents and aluminum for the bulk storage
Organic polymer capacitors offer a good required for transients.
compromise, with stable ESR over temperature,
but cost slightly more than aluminum electrolytic.
The current ripple that the output capacitor
sees is an offset triangular-shaped waveform
whose value is calculated with Equation 28.

Texas Instruments 3-21 SLUP302

H. The Design Example Schematic
The design example was built, tested and
confirmed using the schematic shown in Figure
20.
L1 C2
D1 1 mH 1000pF
DF06M
J5 F2
Universal AC Input C1 T1
2A J1
470 pF 191 µH
AC Line 5 V, 10 W
+ + R4
C3 C19 C6 R1 + + + +Vout
1.54M C7 C4 C5 C8 C12
6.8 µF 22 µF 0.1 µF 51.1 k R2 1 µF
Neutral 1 µF 220 µF 220 µF 220 µF -Vout
78.7
R6 Q1
1.54M FDS5680
D2
UF4007-TP
R7
1.54M R3
20.0
R5
U1
10.0
UCC24610D R8 R9
1 8
SYNC VD 10.0 6.19
D3 R13 2 7
15 EN/TOFF VS
ES1D Q3 3 TON 6
STP9NK70Z GND
R14 4 VCC GATE 5
FB1
2.26
R11 R12 C13
D4 237 k 0.68 µF
133 k
SDM100K30L-7

Topic 3
U2 R29
R16
CNY17F1M 1.47 k R27
1.00 k R25 51.1
3.65 k
R18 R19 D5 R24
20.5 k 169 k U3 RB501V 1.00 k
C20
UCC28610D 220 pf
1 8
R20 FB VDD
100 k 2 ZCD GND 7 C21 R26
3 CL DRV 6 22 nF 15.4 k
4 MOT VGG 5
C15 C17 C18 C16 D7
C14 R21 R22 R23 +
no 0.1 µF 0.1 µF 47 µF MMSZ5253BT1G
100 pF 64.9 k 86.6 k 71.5 k U4
pop. R24
TL431 10.0 k

Figure 20 – QR flyback design example

schematic.

VI. Conclusion
A quasi-resonant flyback converter is ideal for inductance. Bias windings carry much more
low- to mid-power offline isolated applications. responsibility than typically expected, so careful
Many decisions are necessary throughout the consideration must be given to the coupling of all
design process, and each decision has an impact windings. The turns ratio will determine the
on the overall performance of the final product. viability of using a Schottky or a synchronous
Being aware of the effect of each decision is rectifier, and the end result will have a dramatic
important when weighing the trade-offs and effect on the efficiency and reliability of the entire
compromises. system. This practical step-by-step approach of
The quasi-resonant controller’s modulation the available options and actual results showed the
method for regulation sets a known operating benefits of each component selection and the
point for the design process. Selection of the input efficiency improvements to be gained.
capacitor will place restrictions on the primary

Texas Instruments 3-22 SLUP302

 VII. References
[1] Billings, Keith. Switchmode Power Supply [6] Basso, Christophe. “The Dark Side of Flyback
Handbook. New York: McGraw-Hill, Inc., Converters.” APEC 2011. Accessed May 4,
1989. 2012.
[2] Pressman, Abraham I. Switching Power http://www.google.com/url?sa=t&rct=j&
Supply Design. New York: McGraw-Hill, Inc., q=&esrc=s&source=web&cd=1&ved=0C
1991. HIQFjAA&url=https%3A%2F%2Ffanyv88.com%3A443%2Fhttp%2Fcbasso.
pagesperso-orange.r%2FDownloads%2F
[3] Lenk, Ron. Practical Design of Power PPTs%2FChris Basso APEC seminar
Supplies. Piscataway, New Jersey: McGraw- 2011.pdf&ei=A0GkT6b9Eczeggf7mYm
Hill, IEEE Press, 1998. yAQ&usg=AFQjCNF-SWY-NpZ
[4] Brown, Marty. Power Supply Cookbook, K0VbFDUJnZsa5XgQ1.
Second Edition. Woburn, Massachusetts: [7] Zhang, Jacky, Jimmy Liu, and Bing Lu. “A
Newnes, 2001. High Efficiency Synchronous Rectifier
Topic 3

[5] Betten, John, and Brian King. “Boost Flyback for High Density AC/DC Adaptor. TI
Efficiency for Low-Cost Flyback Converters.” literature No. SLUA604.
April 2, 2008.
http://www.edn.com/article/472292-Boost_
efficiency_for_low_cost_flyback_converters.
php.

Texas Instruments 3-23 SLUP302

Appendix A. 10-W Quasi-Resonant Converter for the Power Supply Design
Seminar 2000 Reference Design Example Featuring the UCC28610 and
UCC24610 Controllers.
The transformer used in a QR flyback converter of the specification that was submitted to the
is an essential component that requires careful magnetic manufacturer, Wurth Midcom, which
and specific design. The following is an example achieved a successful design on the first build.

GENERAL:
Topology Quasi-Resonant Flyback
Main Output Power 10 W
Maximum Switching Frequency at Full Load 100 kHz
Minimum Switching Frequency at Light Load 30 kHz
Operating Temperature -40°C to 125°C including temp. rise
Bobbin THT

Topic 3
Creepage and Clearance 8-mm over-surface/4-mm through-air spacings maintained
between primary and each safety-isolated circuit

INPUT:
Minimum Input Voltage 85 VAC
Maximum Input Voltage 265 VAC
Minimum Line Frequency 47 Hz
Minimum Rectified Bulk Input Voltage 76 V
Minimum Rectified Brown Out Voltage 67 V
Primary Side Peak Current 1.155 A
Primary Side RMS Current 0.356 A
Maximum On-Time at Minimum Input, Maximum Load 2.900 µs

OUTPUTS: One Secondary Winding, One Bias Winding

Secondary Output Voltage 5V
Secondary Side Peak Current 13.861 A
Secondary Side RMS Current 4.541 A
Demagnetizing Time 3.222 µs
Bias Voltage 16 V
Bias Current 50 mA

INDUCTANCE AND TURNS RATIOS:

Primary Inductance 190.918 µH < +/- 10%
Leakage Inductance 3.818 µH max
Primary to Secondary Turns Ratio (NP:NS) 12.492 < +/- 10%
Primary to Bias Turns Ratio (NP:NB) 4.097 < +/- 10%
Hipot: Pri to Sec, 2 Seconds 3750 VAC
Reinforced Insulation

Texas Instruments 3-24 SLUP302

 Notes for Design:
• The bias windings must be well-coupled to the • Must be potted or heavily varnished to reduce
primary and secondary. Interleave the bias and audible noise. Also, fill the gap with flexible
secondary windings between the primary for epoxy to reduce audible noise.
good coupling. • Distribute bias windings over entire width of
• Place the undotted end of the primary winding bobbin.
as close to the core as possible to help shield • Use bundled stranded wire to distribute across
dV/dt noise. layer.
• Wind the secondary so that, if multiple layers, • Use round post core to reduce leakage
the undotted end is the outermost layer. inductance.
• Use triple-insulated wire on the secondary to • Gap only the center leg.
meet isolation requirements while minimizing
leakage inductance.
Topic 3

~ NP NS VOUT
VIN
~ to
VDD NB

Figure A1 – Simplified schematic.

Dot End of Primary Winding

Insulation Tape

One-Half Primary

Secondary,
T riple-Insulated
Wire

Bias

One-Half Primary

Undotted End of Primary Winding

Figure A2 – Recommended winding configuration.

Texas Instruments 3-25 SLUP302

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