A4931

3-Phase Brushless DC Motor Pre-Driver

FEATURES AND BENEFITS DESCRIPTION

▪ Drives 6 N-channel MOSFETs The A4931 is a complete 3-phase brushless DC motor pre-driver.
▪ Synchronous rectification for low power dissipation The device is capable of driving a wide range of N-channel
▪ Internal UVLO and thermal shutdown circuitry power MOSFETs and can support motor supply voltages up to
▪ Hall element inputs 30 V. Commutation logic is determined by three Hall-element
▪ PWM current limiting inputs spaced at 120°.
▪ Dead time protection
Other features include fixed off-time pulse-width modulation
▪ FG outputs
(PWM) current control for limiting inrush current, locked-rotor
▪ Standby mode
protection with adjustable delay, thermal shutdown, overvoltage
▪ Lock detect protection
monitor, and synchronous rectification. Internal synchronous
▪ Overvoltage protection
rectification reduces power dissipation by turning on the
appropriate MOSFETs during current decay, thus shorting
the body diode with the low RDS(on) MOSFET. Overvoltage
PACKAGE: 28-contact QFN (ET package) protection disables synchronous rectification when the motor
pumps the supply voltage beyond the overvoltage threshold
during current recirculation.
The A4931 offers enable, direction, and brake inputs that can
control current using either phase or enable chopping. Logic
outputs FG1 and FG2 can be used to accurately measure motor
rotation. Output signals toggle state during Hall transitions,
providing an accurate speed output to a microcontroller or
speed control circuit.
Not to scale
The A4931 is supplied in a 5 mm × 5 mm, 28-terminal QFN
package with exposed thermal pad. This small footprint package
is lead (Pb) free with 100% matte-tin leadframe plating.

Typical Application
0.1 µF
0.1 µF
0.1 µF 2 kΩ 0.1 µF
VIN CLD HBIAS CP1 CP2 VCP VBB VIN

GHA
FG1 SA
A4931 GLA M
System FG2
Control GHB
Logic BRAKEZ SB
GLB
ENABLE
GHC
DIR
SC
GLC
SENSE
GND HA+ HA– HB+ HB– HC+ HC–

4931-DS, Rev. 9 February 10, 2022

MCO-0000383
A4931 3-Phase Brushless DC Motor Pre-Driver

SELECTION GUIDE
Operating Ambient
Part Number Packing Package
Temperature, TA (°C)
A4931METTR-T 1500 pieces per reel 5 mm × 5 mm, 0.90 mm nominal height QFN –20 to 105
A4931GETTR-T 1500 pieces per reel 5 mm × 5 mm, 0.90 mm nominal height QFN –40 to 105

ABSOLUTE MAXIMUM RATINGS

Characteristic Symbol Notes Rating Units
Load Supply Voltage VBB 38 V
Motor Phase Output SX tw < 500 ns –3 V
Hall Input VHx DC –0.3 to 7 V
Logic Input Voltage Range VIN –0.3 to 7 V
Logic Output Voltage Range VFG FG1, FG2 pins –0.3 to 7 V
Range M –20 to 105 °C
Operating Ambient Temperature TA
Range G –40 to 105 °C
Maximum Junction Temperature TJ(max) 150 °C
Storage Temperature Tstg –40 to 150 °C

THERMAL CHARACTERISTICS
Characteristic Symbol Test Conditions* Rating Units
Package Thermal Resistance,
RθJA 4-layer PCB based on JEDEC standard 32 °C/W
Junction to Ambient
Package Thermal Resistance,
RθJP 2 °C/W
Junction to Exposed Pad

*For additional information, refer to the Allegro website.

2
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
A4931 3-Phase Brushless DC Motor Pre-Driver

FUNCTIONAL BLOCK DIAGRAM

0.1 µF

CP2

CP1
0.1 µF
Lock
CLD FG1
Detect
CHARGE PUMP VCP
0.1 µF
HBIAS VREG VBB
2 kΩ
HA+
VIN
0.1 µF HALL
Enable

OVP
HA-

Commun- VCP VREG GHA

HB+ ication
HALL Logic
SA
HB-
GHB
GATE SB
HC+ DRIVE GLB
HALL
GHC
HC-
Control SC
Logic GLC
FG1 GLA
FG2

BRAKEZ SENSE RSENSE

System
DIR 200 mV
Logic
ENABLE

VIN
GND

3
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
A4931 3-Phase Brushless DC Motor Pre-Driver

PINOUT DIAGRAM AND TERMINAL LIST

28 BRAKEZ
27 ENABLE

25 CLD
24 FG2
23 FG1
26 DIR

22 SA
HA+ 1 21 GHA
HA– 2 20 SB
HB+ 3 19 GHB
HB– 4 PAD 18 SC
HC+ 5 17 GHC
HC– 6 16 GLA
GND 7 CP2 10 15 GLB

VCP 12
SENSE 13
GLC 14
VBB 11
8
9
HBIAS
CP1

ET Package Pinout Diagram

Terminal List
Number Name Description Number Name Description
1 HA+ Hall input A 15 GLB Low side gate drive B
2 HA - Hall input A 16 GLA Low side gate drive A
3 HB+ Hall input B 17 GHC High side gate drive C
4 HB - Hall input B 18 SC High side source connection C
5 HC+ Hall input C 19 GHB High side gate drive B
6 HC- Hall input C 20 SB High side source connection B
7 GND Ground 21 GHA High side gate drive A
8 HBIAS Hall bias power supply output 22 SA High side source connection A
9 CP1 Charge pump capacitor terminal 23 FG1 FG 1 speed control output (3 Φ inputs)
10 CP2 Charge pump capacitor terminal 24 FG2 FG 2 speed control output (ΦA input)
11 VBB Supply voltage 25 CLD Locked rotor detect timing capacitor
12 VCP Reservoir capacitor terminal 26 DIR Logic input – motor direction
13 SENSE Sense resistor connection 27 ENABLE Logic input – external PWM control
14 GLC Low side gate drive C 28 BRAKEZ Logic input – motor brake (active low)

4
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
A4931 3-Phase Brushless DC Motor Pre-Driver

ELECTRICAL CHARACTERISTICS*: Valid at TA= 25°C, VBB = 24 V, unless noted otherwise

Characteristics Symbol Test Conditions Min. Typ. Max. Units
Supply Voltage Range VBB Operating 8 – VBBOV V
fPWM < 30 kHz, CLOAD = 1000 pF – 5 6 mA
Motor Supply Current IBB
Charge pump on, outputs disabled, Standby mode – 3 3.5 mA
HBIAS Voltage VHBIAS 0 mA ≤ IHBIAS ≤ 24 mA 7.2 7.5 7.8 V
HBIAS Current Limit IHBIASlim 30 – – mA
CONTROL LOGIC
VIN(1) 2 – – V
Logic Input Voltage
VIN(0) – – 0.8 V
IIN(1) VIN = 2 V –1 <1.0 1 µA
Logic Input Current
IIN(0) VIN = 0.8 V –1 <–1.0 1 µA
ENB pin 350 500 650 ns
Input Pin Glitch Reject tGLITCH
DIR, BRAKEZ pins 700 1000 1300 ns
ENB Standby Pulse Propagation Delay tdENB To outputs off 2.1 3 3.9 ms
HBIAS Wake-Up Delay, Standby Mode tdHBIAS CHBIAS = 0.1 µF – 15 25 µs
GATE DRIVE
High-Side Gate Drive Output VGS(H) Relative to VBB, IGATE = 2 mA 7 – – V
Low-Side Gate Drive Output VGS(L) IGATE = 2 mA 7 – – V
Gate Drive Current (Sourcing) IGate VGH = VGL = 4 V 20 30 – mA
Gate Drive Pull Down Resistance RGate 10 28 40 Ω
Dead Time tdead 700 1000 1300 ns
Current Limit Input Threshold VREF 180 200 220 mV
Fixed Off-Time tOFF 18 25 37 µs
PROTECTION
Thermal Shutdown Temperature TJTSD 155 170 185 °C
Thermal Shutdown Hysteresis TJTSDhys 14 15 26 °C
VBB UVLO Enable Threshold VBBUV Rising VBB 6.2 7 7.85 V
VBB UVLO Hysteresis VBBUVhys 0.4 0.75 1 V
VCP UVLO VCPUV Relative to VBB 4.6 – 6 V
Lock Detect Duration tlock C = 0.1 µF 1.5 2 2.5 s
VBB Overvoltage Threshold VBBOV Rising VBB 30 33 37.5 V

Continued on the next page...

5
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
A4931 3-Phase Brushless DC Motor Pre-Driver

ELECTRICAL CHARACTERISTICS* (continued): Valid at TA= 25°C, VBB = 24 V, unless noted otherwise
Characteristics Symbol Test Conditions Min. Typ. Max. Units
HALL LOGIC
Hall Input Current IHALL VIN = 0.2 to 3.5 V –1 0 1 µA
Common Mode Input Range VCMR 0.2 – 3.5 V
AC Input Voltage Range VHALL 60 – – mVp-p
Hall Thresholds Vth Difference between Hall inputs at transitions – ±10 – mV
TJ = 25°C 10 20 30 mV
Hall Threshold Hysteresis VHYS
TJ = –20°C to 125°C 5 20 40 mV
Pulse Reject Filter tpulse – 2 – µs
FG
FG Output Saturation Voltage VFG(sat) IFG = 2 mA – – 0.5 V
FG Leakage Current IFGlkg VFG = 5 V – – 1 µA

*Typical data are for initial design estimations only, and assume optimum manufacturing and application conditions. Performance may vary for
individual units, within the specified maximum and minimum limits.
For input and output current specifications, negative current is defined as coming out of (sourcing) the specified device pin.
Specifications throughout the allowed operating temperature range are guaranteed by design and characterization.

6
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
A4931 3-Phase Brushless DC Motor Pre-Driver

Logic States Table (See timing charts, below) X = Don’t Care, Z = high impedance
Inputs Resulting Pre-Driver Outputs Motor Output
Condition
HA HB HC BRAKEZ ENB GHA GLA GHB GLB GHC GLC A B C
A + – + HI LO HI LO LO HI LO LO HI LO Z
B + – – HI LO HI LO LO LO LO HI HI Z LO
DIR = 1 C + + – HI LO LO LO HI LO DIR =
LO1 = FORHI Z HI LO
(Forward) D – + – HI LO LO HI HI LO LO LO LO HI Z
A B C D E F
E – + + HI LO LO HI LO LO HI LO LO Z HI
HA
F – – + HI LO LO LO LO HI HI LO Z LO HI
A + – + HI LO LO
HB HI HI LO LO LO LO HI Z
F – – + HI LO LO LO HI LO LO HI Z HI LO
HC
DIR = 0 E – + + HI LO HI LO LO LO LO HI HI Z LO
(Reverse) D – + – HI LO HI LO LO HI LO LO HI LO Z
FG1
C + + – HI LO LO LO LO HI HI LO Z LO HI
B + – – HI LO LO HI LO LO HI LO LO Z HI
SA
Fault* + + + HI X LO LO LO LO LO LO Z Z Z
Fault* – – – HI X LO LO LO LO LO LO Z Z Z
Brake* X X X LO X SB
LO HI LO HI LO HI LO LO LO

* DIR = Don’t Care

SC

DIR = 1 = FOR DIR = 0 = REV

A B C D E F A F E D C B
HA HA

HB HB

HC HC

FG1 FG1

SA SA

SB SB

SC SC

DIR = 0 = REV

A F E D C B
HA

HB
7
Allegro MicroSystems
HC 955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
FG1
A4931 3-Phase Brushless DC Motor Pre-Driver

VBB VBBUV

Charge
Pump

HBIAS
Voltage

Standby Mode
Turn off Hall
tdENB 3 ms
Bias Supply

ENB

Outputs Enabled Outputs Disabled Outputs Enabled

Figure 1: Power-Up and Standby Modes Timing Diagram

VBB VBBUV

VBB+7.5 V
VCPUV
Charge
Pump

7.5V
VHBIAS
HBIAS
Voltage

ENB PWM

Outputs Enabled Outputs Disabled

Figure 2: Power-Down Timing Diagram

8
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
A4931 3-Phase Brushless DC Motor Pre-Driver

FUNCTIONAL DESCRIPTION
Current Regulation Synchronous Rectification
Load current is regulated by an internal fixed off-time PWM When a PWM-off cycle is triggered, either by a chop command
control circuit. When the outputs of the full bridge are turned on, on ENB or by an internal fixed off-time cycle, load current recir-
current increases in the motor winding until it reaches a value, culates. The A4931 synchronous rectification feature turns on the
ITRIP , given by: appropriate MOSFETs during the current decay, and effectively
shorts out the body diodes with the low RDS(on) driver. This low-
ITRIP = 200 mV / RSENSE . ers power dissipation significantly and can eliminate the need for
When ITRIP is reached, the sense comparator resets the source external Schottky diodes.
enable latch, turning off the source driver. At this point, load
inductance causes the current to recirculate for the fixed off-time Brake Mode
period. A logic low on the BRAKEZ pin activates Brake mode. A logic
high allows normal operation. Braking turns on all three sink
Enable Logic drivers, effectively shorting out the motor-generated BEMF.
The Enable input terminal (ENB pin) allows external PWM. ENB The BRAKEZ input overrides the ENB input and also the Lock
low turns on the selected sink-source pair. ENB high switches Detect function.
off the appropriate drivers and the load current decays. If ENB is
It is important to note that the internal PWM current control cir-
held low, the current will rise until it reaches the level set by the
cuit does not limit the current when braking, because the current
internal current control circuit. Typically PWM frequency is in 20
does not flow through the sense resistor. The maximum current
to 30 kHz range. If the ENB high pulse width exceeds 3 ms, the
can be approximated by VBEMF / RLOAD. Care should be taken to
gate outputs are disabled. The Enable logic is summarized in the
insure that the maximum ratings of the A4391 are not exceeded
following table:
in the worse case braking situation, high speed and high inertial
ENB Pin Setting Outputs Outputs State load.
0 On Drive
HBIAS Function
Slow Decay with
1 Source Chopped Synchronous This function provides a power supply of 7.5 V, current-limited to
Rectification 30 mA. This reference voltage is used to power the logic sections
1 for > 3 ms typical Off Disable of the IC and also to power the external Hall elements.

Fixed Off-Time Standby Mode

The A4931 fixed off-time is set to 25 µs nominal. To prevent excessive power dissipation due to the current draw
of the external Hall elements, Standby mode turns off the HBIAS
PWM Blank Timer output voltage. Standby mode is triggered by holding ENB high
When a source driver turns on, a current spike occurs due to the for longer than 3 ms. Note that Brake mode overrides Standby
reverse recovery currents of the clamp diodes as well as switch- mode, so hold the BRAKEZ pin high in order to enter Standby
ing transients related to distributed capacitance in the load. To mode.
prevent this current spike from erroneously resetting the source Charge Pump
Enable latch, the sense comparator is blanked. The blanking timer
runs after the off-time counter completes, in order to provide The internal charge pump is used to generate a supply above VBB
the blanking function. The blanking timer is reset when ENB is to drive the high-side MOSFETs. The voltage on the VCP pin is
chopped or DIR is changed. With external PWM control, a DIR internally monitored, and in case of a fault condition, the outputs
change or an ENB on triggers the blanking function. The duration of the device are disabled.
is fixed at 1.5 µs.

9
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
A4931 3-Phase Brushless DC Motor Pre-Driver

Fault Shutdown • The FG1 signal is not consistently changing.

In the event of a fault due to excessive junction temperature or • The proper commutation sequence is not being followed. The
due to low voltage on VCP or VBB, the outputs of the device are motor can be locked in a condition in which it toggles between
disabled until the fault condition is removed. At power-up, the two specific Hall device states.
UVLO circuit disables the drivers.
Both of these fault conditions are allowed to persist for period
Overvoltage Protection of time, tlock. tlock is set by capacitor connected to CLD pin. CLD
produces a triangle waveform (1.67 V peak-to-peak) with fre-
VBB is monitored to determine if a hazardous voltage is present
quency linearly related to the capacitor value. tlock is defined as
due to the motor generator pumping up the supply bus. When the
127 cycles of this triangle waveform, or:
voltage exceeds VBBOV , the synchronous rectification feature is
disabled. tlock = CLD × 20 s/µF
Overtemperature Protection After the wait time, tlock , has expired, the outputs are disabled,
If die temperature exceeds approximately 170°C, the Thermal and the fault is latched. These fault conditions can only be cleared
Shutdown function will disable the outputs until the internal tem- by any one of the following actions:
perature falls below the 15°C hysteresis. • Rising or falling edge on the DIR pin
Hall State Reporting • VBB UVLO threshold exceeded (during power-up cycle)
The FG1 pin is an open-drain output that changes state at each • ENB pin held high for > tlock / 2
transition of an external Hall element. The FG2 pin is an open-
drain output that changes state at each HAx transition. The Lock Detect function can be disabled by connecting CLD to
GND.
Lock Detect Function
When the A4931 is in Brake mode, the Lock Detect counter is
The IC will evaluate a locked rotor condition under either of disabled.
these two different conditions:

10
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
A4931 3-Phase Brushless DC Motor Pre-Driver

ET Package, 28-Contact QFN

0.30
5.00 BSC
1.15 28 0.50
28

1
2 A 1
0.15 C 2×

5.00 BSC 3.15 4.80

0.15 C 2×
3.15
29× D C
4.80
0.08 C SEATING
PLANE C PCB Layout Reference View
+0.05
0.25 –0.07 0.90 ±0.10 Contact the factory for the sidewall plating PCB
0.50 footprint and assembly instructions.

0.55
B
3.15
XXXX
2 Date Code
1 Lot Number

28
E Standard Branding Reference View 1
3.15
Line 1: Part Number
Line 2: Logo A, 4-Digit Date Code
Line 3: Characters 5, 6, 7, 8 of Assembly Lot Number
For Reference Only; not for tooling use
(reference DWG-0000378, Rev. 3)
Dimensions in millimeters
Exact case and lead configuration at supplier discretion within limits shown
A Terminal #1 mark area
B Exposed thermal pad (reference only, terminal #1
identifier appearance at supplier discretion)
C Reference land pattern layout (reference IPC7351
QFN50P500X500X100-29V1M);
All pads a minimum of 0.20 mm from all adjacent pads; adjust as
necessary to meet application process requirements and PCB layout
tolerances; when mounting on a multilayer PCB, thermal vias at the
exposed thermal pad land can improve thermal dissipation (reference
EIA/JEDEC Standard JESD51-5)
D Coplanarity includes exposed thermal pad and terminals

E Branding scale and appearance at supplier discretion

11
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
A4931 3-Phase Brushless DC Motor Pre-Driver

Revision History
Number Date Description
8 February 10, 2020 Added G temperature rated part option; minor editorial updates
9 February 10, 2022 Updated package drawing (page 11)

Copyright 2022, Allegro MicroSystems.

Allegro MicroSystems reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit
improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of
Allegro’s product can reasonably be expected to cause bodily harm.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems assumes no responsibility for its use; nor
for any infringement of patents or other rights of third parties which may result from its use.
Copies of this document are considered uncontrolled documents.

For the latest version of this document, visit our website:

www.allegromicro.com

12
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com