Unit 1 - Basic Gates and Boolean Algebra

Notes
UNIT 1 - BASIC GATES AND BOOLEAN
ALGEBRA

CONTENTS
1.0 Aims and Objectives
1.1 Introduction
1.2 Logic Gates
1.2.1 NOT-Gate
1.2.2 OR Gate
1.2.3 AND Gate
1.2.4 NOR Gate
1.2.5 NAND Gate
1.2.6 XOR Gate
1.2.7 Exclusive NOR
1.2.8 Complement and Invertors
1.2.9 Logical Multiplication
1.3 Basic Laws of Boolean Algebra
1.3.1 Boolean Algebraic Properties
1.4 Proof by Perfect Induction
1.5 Simplification of Boolean Expressions
1.6 K-Map Method
1.6.1 Rules for Solving Karnaugh Maps
1.6.2 Representing Boolean Terms
1.7 Tabulation Method with don’t cares
1.7.1 Rules of Tabular Method
1.8 Let us Sum up
1.9 Lesson End Activity
1.10 Keywords
1.11 Questions for Discussion
1.12 Suggested Readings

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Notes 1.0 AIMS AND OBJECTIVES

After studying this unit, you should be able to:
 Explain the concept of logic gates
 Define Boolean algebra
 Explain the basic knowledge of map simplification

1.1 INTRODUCTION
Majority of computers found in today’s world belong to digital category, other popular
categories being that of analog and hybrid computers. This is not by chance. Digital
computers offer various advantages over other types of computers. Moreover, it is
relatively easier to design.
Digital computers and all the digital circuits in general, make use of just two different
values of electrical signals for all their internal operations, unlike their analog and
hybrid counterparts. The two signals may be called as 1 and 0; TRUE or FALSE; or
ON and OFF.
Mathematical logic also deals with just two quantities – True and False. Likewise,
binary number system uses only two different digits for all its computations.
Therefore, it is only natural that digital circuits obey mathematical logic as also binary
arithmetic. For centuries, mathematicians felt there was a connection between
mathematics and logic, but no one before George Boolean could find this missing link.
In 1854, he invented symbolic logic known today as Boolean algebra. Each variable in
Boolean algebra can have either of two values; true or false and this algebra is applied
to computer electronics.

1.2 LOGIC GATES

The most fundamental circuit that digital computers are comprised of is called a
logical gate or simply a gate. Gate is a circuit with one or more input signals but only
one output signal. Gates are digital (two state) circuits because the input and output
signals are either low or high circuits. They can be analyzed with Mathematical logic,
Boolean algebra, and binary number system because all these fields of study deal with
just two different values.

1.2.1 NOT-Gate
A NOT gate (also called an inverter) is a gate with only one input signal and one
output signal. The output state is always opposite of the input state.
Figure 1.3 shows a transistor inverter. The common-emitter amplifier switches
between cut-off and saturation states. When Vin is low the transistor cuts off and (0 or
+5V) Vout is high. On the other hand, a high Vin saturates the transistor, forcing Vout
to go low.

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 Unit 1 - Basic Gates and Boolean Algebra

Notes

Figure 1.3: Transistor as Inverter

Table 1.1 summarizes the operation. A low input produces a high output and a high
input results in a low output. Table 1.2 gives the same information in binary 0 stands
for low voltage and binary 1 for high voltage.
Table 1.1

V in V out

Low High

High Low

Table 1.2

V in V out

0 1

1 0

An Inverter is also called a NOT gate because the output is not the same as input.
The output is sometimes called complement (opposite) of the input.

Vin Vout Vin Vout Vin Vout

(a) (b) (c)

Figure 1.4: NOT Gate

Figure 1.4(a) & (b) are symbols for inverters of any design. Whenever the symbol is
either of the two, remember that the output is the complement of the Input.

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Notes Figure 1.4(c) is the symbol for a non-inverting amplifier. A low voltage input
produces a low output.
Consider for example, if we are given a 6-bit register whose output may represent
coded instructions, number, letter and the string of bits called binary word 100101 can
be complemented using Inverters.
Complement of 100101 can be obtained in Figure 1.5(b) and is 011010.

1 1
A A 1
0 0
B B 0
6 bit C 0 0
C 0
register D 1 1
D 1
0 0
E E 0
1 1
F F 1

(a) (b)

Figure 1.5: Complement of 100101

1.2.2 OR Gate
The OR gate has two or more input signals but only one output signal such that if any
one or more input signal is high, output signal is high.

Figure 1.6: One way to build an OR Gate

If both inputs are low, the output is low. If either input is high, the diode with high
input conducts and the output is high. Because of the two inputs, we call these circuits
a two input OR gate. Table summarizes the action.
Similarly, Figure 1.7 shows a 3-input OR Gate

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A B Y Notes
0 0 0
0 1 1
1 0 1
1 1 1

Figure 1.7: 3-Input OR Gate

If all inputs are low, all dipoles are off and the output is low. If 1 or more inputs are
high, the output is high. Table summarizes the action and such a table is called a truth
table, and it lists all the input possibilities and the corresponding outputs. When
constructing a truth table, always list the input words in binary progressions. This
guarantees that all input possibilities will be accounted for Figure 1.8 shows logic
symbols for 2, and 3 input OR gates.

A B C Y
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 1

Figure 1.8: Symbol of OR Gate

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Notes 1.2.3 AND Gate

The AND gate has two or more input signals but only one output signal. All the inputs
must be high to get a high output.
Figure 1.9 (a) shows one way to build an AND gate. In this circuit the inputs can be
either low (ground) or high (+5V). Both inputs are low (Figure 1.9 (b)), both the
diodes conduct and pull the output down to and the other high. In Figure 1.9 (c) the
diode with the low input conducts and this pulls the output down in a low voltage.
The diode with the high input, on the other hand is reverse biased or cut off
symbolized by shading.

(a) (b)

(c) (d)

Figure 1.9: A 2-input AND Gate. (a) Circuit; (b) Both Input Low;
(c) Low Input High; (d) Both Inputs High
When both inputs are high Figure 1.9(d) both diodes are cut off. Since there is number
current in the resistor, the supply voltage pulls the output to high voltage (+5V).
Table below summarize the action so to get a high output, A and B must be high. This
is why the circuit is called an AND gate.
Similarly, we have three inputs AND gate. If all inputs are low, all diodes conduct and
pull the output down to a low voltage. Even one conducting diode will pull the output
down to a low voltage. Therefore, the only way to get a high output is to have all
inputs high. When all inputs are high, all diode are non-conducting and the supply
voltage pulls the output to a high value. Truth table for three inputs AND gate is given
in table.

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A B Y Notes
0 0 0
0 1 0
1 0 0
1 1 1

Figure 1.10: Symbol of AND Gate

1.2.4 NOR Gate

The NOR gate has two or more input signals but only one output signal such that all
inputs must be low to get a high output. In other words NOR gate recognize only the
input word whose bits are all 0’s.

Figure 1.11: Symbol for NOR Gate

NOR gate is an OR gate followed by an inverter. Therefore, the final output is NOT
the OR of the inputs, originally called a NOT-OR gate, the circuit is now referred to as
NOR gate. Notice that the inverter triangle has been deleted and a small circle or
bubble moved to the OR follows the ORing.
For a NOR gate, if both inputs are low the final output is high. If one input is low and
the other is high the output is low. If both inputs are high, the output is low. Table
below summarizes the circuit action and we see the NOR gate recognize only the
input word where bits are all 0’s. In other words all inputs must be low to get a high
output Boolean equation for two inputs, NOR gate is Y = (A+B)’

A B A+B A B
0 0 0 1
0 1 1 0
1 0 1 0
1 1 1 0

Read this as “Y equals NOT A OR B”. If you use the equation remember that the
ORing is done first then the inversion. Similarly, for 3 and 4 input NOR gates are
shown in Figure below:

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Notes

(a) Three input NOR Gate (b) Four input NOR Gate

Figure 1.12: 3 and 4 input NOR Gate

1.2.5 NAND Gate

The NAND gate has two or more inputs but only one output signal such that at least
one input must be low to get a high output. In other words, NAND gates recognized
only the input word whose one input bit is at least low.
NAND gate is equivalent to an AND gate followed by an inverter. Therefore the final
output is NOT the AND of the inputs. Originally called a NOT-AND gate, the circuits
is now referred to as NAND gate.
Figure 1.13 is the standard symbol of NAND gate. Notice that the inverter triangle has
been deleted and a small circle or bubble moved to the AND gate output the bubble is
a remainder of the inversion that follows the ANDing.

Figure 1.13: 2-Input NAND Gate

For a NAND gates, if both inputs are low, the final output is high; if one input is low
and other is high; the output is high if both inputs are high, the output is low.
Table below summarize the circuit action and we see, the NAND gate recognize the
input word whose bits are 0 and 1’s. In other words all inputs are high to get
output low.

A B A .B A.B
0 0 0 1
0 1 0 1
1 0 0 1
1 1 1 0

Boolean equation for two input NAND gate is given by

Y=( A.B )

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Read this as “Y equals NOT A and B”. If you use this equation, remember that the Notes
ANDing is done first then the inversion. Similarly 3 & 4 inputs NAND gate are shown
below:

A A
B Y B
Y
C
C
D
(a) Three input NAND Gate (b) Four input NAND Gate

Figure 1.14: NAND Gate

1.2.6 XOR Gate

XOR Gate has two inputs and a single output which goes high whenever one and only
one input line is high. The symbol of XOR Gate is given below:

A
Y
B

Figure 1.15: Symbol of XOR Gate

The algebraic expression for XOR Gate is given below:
Y=AB
The truth table of XOR operation is given below:

A B Y
0 0 0
0 1 1
1 0 1
1 1 0

1.2.7 Exclusive NOR

The exclusive-NOR or XNOR gate has two or more inputs. The output is equivalent to
inverting the output from the exclusive-OR gate described above. Therefore an
equivalent circuit would comprise an XOR gate, the output of which feeds into the
input of a NOT gate.
In general, an XNOR gate gives an output value of 1 when there are an even number
of 1's on the inputs to the gate. The truth table for a 3-input XNOR gate below
illustrates this point.

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Notes The XNOR gate is drawn using the same symbol as the XOR gate with an invert
bubble on the output line as is illustrated below:

Figure 1.16: Symbol of XNOR

The output from the XNOR gate is written as A B which reads "A XNOR B".
The truth table for a two-input XNOR gate looks like

A B A B
0 0 1
0 1 0
1 0 0
1 1 1

For a 3-input XNOR gate with inputs A, B and C the truth table is given by

A B C A B C
0 0 0 1
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 0

1.2.8 Complement and Invertors

Other than the four basic operations Boolean algebra also supports complement
of a variable i.e. the opposite of its value. Boolean algebra uses capital
alphabetical letters to denote variables.

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Example: Notes

Figure 1.17: Complement

Complement of A is read as A-not or A-bar. We can also use a prime symbol is

used to represent complementation.

1.2.9 Logical Multiplication

Take a close look at the two-term sums in the first set of equations. Does that
pattern look familiar to you? It should! It is the same pattern of 1’s and 0’s as
seen in the truth table for an OR gate. In other words, Boolean addition
corresponds to the logical function of an “OR” gate, as well as to parallel
switch contacts:

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Notes

Figure 1.18: Rules of Multiplication

Example

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Check Your Progress 1 Notes

1. Define logic gates.
……………………………………………………………………………
……………………………………………………………………………
2. Draw the truth table of NOT Gate.
……………………………………………………………………………
…………………………………………………………………………....
3. Give the names of four logic gate.
…………………………………………………………………………....
…………………………………………………………………………....

1.3 BASIC LAWS OF BOOLEAN ALGEBRA

The digital signals are discrete in nature and can only assume one of the two values
0 or 1. A number system based on these two digits is known as binary number system.
In the middle of 19th century, an English mathematician George Boolean developed
rules manipulations of binary variables, known as Boolean algebra. This is the basis of
all digital systems like computers, calculators, etc.
Binary variables can be represented by a letter symbol such as A, B, C, X, Y,…. The
variable can have only of the two possible values at any time, viz. 1 or 1. From these
theorems, we observed that the even numbered theorems can be obtained from their
preceding odd numbered theorems by (i) interchanging + and signs, and
(ii) interchanging 0 and 1.
Theorems which are related in this way are called duals.
Theorems 1.1 to 1.8 involve a single variable only. Each of these theorems can
be proved by considering very possible value of the variable. For example, in
Theorem 1.1,
If A = 0 then 0 + 0 = 0 = A
And if A = 1 then 1 + 0 = 1 = A
And hence the theorem is proved.
Table 1.3: Laws of Boolean Truth Table

Boolean Description Equivalent Boolean Algebra

Expression Switching Circuit Law or Rule

A+1=1 A in parallel with Annulment

closed = "CLOSED"

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Notes
A+0=A A in parallel with Identity
open = "A"

A.1=A A in series with Identity

closed = "A"

A.0=0 A in series with Annulment

open = "OPEN"

A+A=A A in parallel with Idempotent

A = "A"

A.A=A A in series with Idempotent

A = "A"

NOT A = A NOT NOT A Double Negation

(double negative) = "A"

A+A=1 A in parallel with Complement

NOT A = "CLOSED"

A.A=0 A in series with Complement

NOT A = "OPEN"

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Notes
A+B = B+A A in parallel with B = Commutative
B in parallel with A

A.B = B.A A in series with B = Commutative

B in series with A

A+B = A.B invert and replace OR with AND de Morgan’s Theorem

A.B = A+B invert and replace AND with OR de Morgan’s Theorem

The basic Laws of Boolean Algebra that relate to the Commutative Law
allowing a change in position for addition and multiplication, the Associative
Law allowing the removal of brackets for addition and multiplication, as well
as the Distributive Law allowing the factoring of an expression, are the same as
in ordinary algebra.

Table 1.4: Boolean Algebraic Theorems

Theorem No. Theorem

1.1 A+0=A
1.2 A.1=A
1.3 A+1=1
1.4 A.0=0
1.5 A+A=A
1.6 A.A=A
1.7 A + A’ = 1
1.8 A . A’ = 0
1.9 A . (B + C) = AB +AC
1.10 A + BC = (A + B) (A + C)
1.11 A + AB = A
1.12 A (A + B) = A
1.13 A + A’B = (A + B)
1.14 A (A’ + B) = AB
1.15 AB + AB’ = A

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Notes 1.16 (A + B) . (A + B’) = A

1.17 AB + A’C = (A +C) (A’ + B)
1.18 (A + B) (A’ + C) = AC + A’B
1.19 AB +A’C +BC = AB + A’C
1.20 (A + B) (A’ + C) (B + C) = (A + B) (A’ + C)
1.21 (A . B . C…..)’ = A’ + B’ + C’ + ….
1.22 (A + B + C + …)’ = A’ . B’ . C’….

Where (’) symbol means complements

Theorems .9 to 1.20 involve more than one variable and can be proved by making a
truth Table. For example, 1.10 can be proved by making the truth table given in
Table 1.5.
Table 1.5: Truth Table to Prove Theorem 1.10
A B C BC A + BC A+B A+C (A + B) (A + C)
0 0 0 0 0 0 0 0
0 0 1 0 0 0 1 0
0 1 0 0 0 1 0 0
0 1 1 1 1 1 1 1
1 0 0 0 1 1 1 1
1 0 1 0 1 1 1 1
1 1 0 0 1 1 1 1
1 1 1 1 1 1 1 1

From the table we observed that there are 8 (= 23) possible combinations of the three
variables A, B and C. For each combination, the value of A + BC is the same as that
of (A + B) (A + C), which proves the theorem. Theorems 21 and 22 are known as
DeMorgan’s theorems. These theorems can be proved by first considering the two
variable case and then extending this result. From the truth table given in Table 1.13,
we get the relations.
(A . B)’ + A’ + B’
And
(A + B)’ = A’.B’
Table 1.13: Truth Table to prove DeMorgan’s Theorems
A B A’ B’ (AB)’ A’ + B’ (A + B)’ A’ . B’
0 0 1 1 1 1 1 1
0 1 1 0 1 1 0 0
1 0 0 1 1 1 0 0
1 1 0 0 0 0 0 0

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Now consider the NAND operation of three variables. Notes

(ABC)’ = ((AB) . C)’
= (A . B)’ + C’
= A’ + B’ + C’
In similar way, the NOR operation of three variables gives
(A + B + C)’ = ((A + B) + C)’
= (A + B)’ . C’
= A’ . B’ . C’
The above result can be easily extended to any number of variables.
A logic problem can be specified in terms of a set of statements. This set of statements
can be specified in terms of an equation called the logic equation or in terms of a truth
table. A digital circuit using the gates. In general it is possible to simplify a logic
equation. The minimized logic equation will probably need less number of gates
and/or less number of inputs for the gates.

1.3.1 Boolean Algebraic Properties

Another type of mathematical identity, called a “property” or a “law,” describes
how differing variables relate to each other in a system of numbers. One of these
properties is known as the commutative property, and it applies equally to addition
and multiplication. In essence, the commutative property tells us we can reverse
the order of variables that are either added together or multiplied together
without changing the truth of the expression:

Figure 1.19: Commutative property of addition.

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Notes

Figure 1.20: Commutative Property of Multiplication

Along with the commutative properties of addition and multiplication, we have

the associative property, again applying equally well to addition and
multiplication. This property tells us we can associate groups of added or
multiplied variables together with parentheses without altering the truth of the
equations.

Figure 1.21: Associative Property of Addition

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Notes

Figure 1.22: Associative Property of Multiplication

Lastly, we have the distributive property, illustrating how to expand a Boolean

expression formed by the product of a sum, and in reverse shows us how terms
may be factored out of Boolean sums-of-products:

Figure 1.23: Distributive Property

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Notes To summarize, here are the three basic properties: commutative, associative,
and distributive.

1.4 PROOF BY PERFECT INDUCTION

In this section we will discuss about mathematical induction and proof by
perfect induction.
Check every possible input value
If two expressions produce the same value for every possible input
combination, the expressions are equal
Example: Proof by Perfect Induction

Number Theorem Name

T6 B•C = C•B Commutativity

Boolean Theorems of Several Vars

Number Theorem Name
T6 B•C = C•B Commutativity
T7 (B•C) • D = B • (C • D) Associativity
T8 B • (C + D) = (B•C) + (B•D) Distributivity
T9 B• (B+C) = B Covering
T10 ( (B  C) + (B  C) = B Combining

T11 (B  C) + (B  D) + (C  D) = Consensus
(B  C) + (B  D)

T9: Covering
Number Theorem Name
T9 B• (B+C) = B Covering

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Prove true by: Notes

Method 1: Perfect induction

Method 2: Prove true using other Axioms and Theorems

B•(B+C) = B•B + B•C T8: Distributivity
= B + B•C T3: Idempotency
= B•(1 + C) T8: Distributivity
= B•(1) T2: Null element
= B T1: Identity

T10: Combining
Number Theorem Name
T10 ( (B  C) + (B  C) = B Combining

Prove true using other axioms and theorems:

B•C + B•C = B•(C+ C ) T8: Distributivity
= B•(1) T5’: Complements
=B T1: Identity

T11: Consensus
Number Theorem Name
T11 (B  C) + (B  D) + (C  D) = Consensus
(B  C) + (B  D)

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Notes
Prove using other theorems and axioms:
B•C + B •D + C•D = BC + B D + (CDB+CD B ) T10: Combining
= BC + B D + BCD+ B CD T6: Commutativity
= BC + BCD + B D + B CD T6: Commutativity
= (BC + BCD) + ( B D + B CD) T7: Associativity
= BC + B D T9’: Covering

1.5 SIMPLIFICATION OF BOOLEAN EXPRESSIONS

The complexity of the digital logic gates that implement a Boolean function is directly
related to the complexity of the algebraic expression from which the function is
implemented. Although the truth table representation of a function is unique expressed
algebraically, it can appear in many different forms. Boolean functions may be
simplified by algebraic means. However, this procedure of minimization is awkward
because it lacks specific rules to predict each succeeding step in the manipulative
process. The map method provides a simple straightforward procedure for minimizing
Boolean functions.
This method may be regarded either as a pictorial form of a truth table or as an
extension of the Venn diagram. The map method, first proposed by Veitch (1) and
slightly modified by Karnaugh (2) is also known as the “Veitch diagram” or the
“Karnaught map.”
The map is a diagram made up of squares. Each square represents one minterm. Since
any Boolean function can be expressed as a sum of minterms, it follow that a Boolean
function is recognized graphically in the map from the area enclosed by those squares
whose minterms are included in the function. In fact, the map presents a visual
diagram of all possible ways a function may be expressed in a standard form.
By recognizing various patterns, the user can derive alternative algebraic expressions
for the same function, from which he can select the simplest one. We shall assume that
the simplest algebraic expression is any one in a sum of products or product of sums
that has a minimum number of literals.

Two-and Three-variable Maps

A two-variable map is show in Figure 1.24. There are four minterms for two variable;
hence the map consists of four squares, one for each minterm. The map is redrawn
in (b) to show the relationship between the squares and the two variables. The 0’s and
1’s marked for each row and each column designate the values of variable x and y,
respectively. Notice that x appears primed in row 0 and unprimed in row 1. Similarly,
y appears primed in column 0 and unprimed in column 1.

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Notes
y
y
x 0’ 1
m0 m1 x’y’ x’y
0

m2 m3 xy’ xy
x 1

(a) (b)

Figure 1.24: Two Variable Map

If we mark the squares whose minterms belong to a given function, the two-variable
map becomes another useful way to represent any one of the 16 Boolean functions of
two variables. As an example, the function xy is shown in Figure 1.25(a). Since xy is
equal to m3, a 1 is placed inside the square that belongs to m3, Similarly, the function x
+ y is represented in the map of Figure 1.25(b) by three squares marked with 1s. These
squares are found from the minterms of the function:
x + y = x’y + xy’ + xy = m1 + m2 + m3
The three squares could have also been determined from the intersection of variable x
in the second row and variable y in the second column, which encloses the area
belonging to x or y
y y
y y
x 0 1 x 0 1

0 0 1

1
1 1 x 1 1 1

(a) xy (b) x + y

Figure 1.25: Presentation of Function in the Map XY

A three-variable map is shown in Figure 1.26. There are eight minterms for three
binary variables. Therefore, a map consists of eight squares. Note that the minterms
are arranged, not in a binary sequence, but in a sequence similar to the reflected code.
The characteristic of this sequences is that only one bit changes from 1 to 0 or from 0
to 1 in the listing sequence. The map drawn in part (b) is marked with numbers in each
row and each column to show the relationship between the squares and the three
variables. For example, the square assigned to m5 corresponds to row 1 and
column 01. When these two numbers are concatenated, they give the binary number
101, whose decimal equivalent is 5.

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Notes
yz y
x 00 01 11 10
m0 m1 m3 m2 0 x’y’z’ x’y’z x’yz x’yz’

m4 m5 m7 m6 xy’z’ xy’z xyz xyz’

x 1

z
(a) (b)

Figure 1.26: Three Variable Map

Another way of looking at square m5 = xy’z is to consider it to be in the row marked x
and the column belonging to y’z column 01. Note that there are four squares where
each variable is equal to 1 and four where each is equal to 0. The variable appears
unprimed in those four squares where it is equal to 1 and primed in those squares
where it is equal to 0. For convenience, we write the variable with its letter symbol
under the four squares where it is unprimed.
To understand the usefulness of the map for simplifying Boolean functions, we must
recognize the basic property possessed by adjacent squares. Any two adjacent squares
in the map differ by only one variable which is primed in one square and unprimed in
the other. For example, m3 and m7 lie in two adjacent squares Variable y is primed in
m5 and unprimed in m7, while the other two variables are the same in both squares.
From the postulates of Boolean algebra, it follow that the sum of two minterms in
adjacent squares can be simplified to a single AND term consisting of only two
literals. To clarify this, consider the sum of two adjacent squares such as m5 and m7:
m5 + m7 = xy’z + xyz = xz (y’ + y) = xz
Here the two squares differ by the variable y, which can be removed when the sum of
the two minerms is formed. Thus, and two minterms in adjacent squares that are O
Red together will cause a removal of the different variable. The following example
explains the procedure for minimizing a Boolean function with a map.
Example: Simplify the Boolean function:
F = x’yz + x’yz’ + xy’z’ + xy’z
First, a 1 is marked in each square as needed to represent the function as shown in
Figure 1.27. This can be accomplished in two ways: either by converting each
minterm to a binary number and then marking a 1 in the corresponding square, or by
obtaining the coincidence of the variables in each term. For example, the term xyz has
the corresponding binary number 011 and represents minterm m3 in square 011.
The second way to recognize the square is by the coincidence of variable x’, y, and z,
which is found in the map by observing that x belongs to the four square in the first
row, y belongs to the four squares in the two right columns, and z belong to the four
squares in the two middle columns. The area that belongs to all three literals is the
single square in the first row and third column.

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Notes
yz y
x 00 01 11 10

0 1 1

x 1 1 1

Figure 1.27: Map of example F = x’yz + x’yz’ + xy’z’ + xy’z = x’y + xy’
In a similar manner, the other three squares belonging to the function F are marked by
1s in the map. The function is thus represented by an area containing four squares,
each marked with a 1, as shown in Figure 1.27. The next is to subdivide the given are
into adjacent squares. These are indicated in the map by two rectangles, each
enclosing two 1s. The upper right rectangle represents the area enclosed by x’y; the
lower left, the area enclosed by xy’. The sum of these two terms gives the answer:
F = x’y + xy’
Next consider the two squares labeled mo and m2 in Figure 1.26(a) or xyz and xyz in
Figure 1.26(b). These two minterms also differ by one variable y, and their sum can be
simplified to a two-literal expression:
x’y’z’ + x’yz’ = x’z’
Consequently, we must modify the definition of adjacent squares to include this and
other similar cases. This is done by considering the map as being drawn on a surface
where the right and left edges touch each other to form adjacent squares.

1.6 K-MAP METHOD

Another method of minimising logic is to apply a graphical technique called
Karnaugh Mapping. This technique represents a function’s truth table and can be
ordered by using a Gray code. For example, if we let n represent the number of input
variables that require simplification, when n = 2:

Truth Table of Function F

Based on above Table, the minterm for each entry of the truth table can be entered into
a map similar to that shown in Figure below. As a result, the terms can be grouped
according to the corresponding map shown in next Figure where n=2.

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Notes

Karnaugh Map for Function F

The principles outlined in the case of the 2-variable minimisation can be applied to
Karnaugh maps of up to 6 variables. In each case, the min-terms are shown in Figure .
If, as in the case of last example, a new function:

were to be implemented, then min-terms 0 & 1 (the first 2 boxes) would be true. In
this case the function would be simplified to

As the number of input variables increases it becomes more and more difficult to
simplify equations using Karnaugh maps. In these situations computer programs are
employed and techniques such as the Quine-McCluskey method using prime and
essential prime implicants.
Shown in Table are graphical representations of truth tables that provide simplification
of Boolean equations for up to six variables. The ability to solve upto 4-variable K-
Maps is required. Following the table are several rules that should be used in
conjunction with these tables.

Figure 1.28: Karnaugh Maps for 1 to 6 Variables

1.6.1 Rules for Solving Karnaugh Maps

Two-Variable (n=2):
 Two adjacent squares are combined to eliminate one variable.
 The remaining variable is common to both squares.

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Three-Variable (n=3): Notes

 Two adjacent squares are combined to eliminate one variable (leaves a two
variable term).
 Four adjacent squares are combined to eliminate two variables (leaves a
single term).

Four-Variable (n=4):
 Same as Three Variable map.
 Eight adjacent squares are combined to eliminate three variables.
 Imagine a four element K-map wrapped over a sphere where each of the
sides as well as the top and bottom meet to form adjacent squares.

Five-Variable (n=5):
 Same as Four Variable map.
 Sixteen adjacent squares are combined to eliminate four variables.
 Draw two four variable K-maps side by side. Select the first variable such
as A and label one map A and the other map A . Look for common patters
between both maps to reduce the number of variables.

Six-Variable (n=6):
 Same as Five Variable map.
 Thirty-two adjacent squares are combined to eliminate five variables.
 Similar to Five Variable map but select two variables to operate over the
four, 16-variable K-maps.
Solving with Karnaugh maps can be simplified if don’t care conditions are taken into
consideration. These are typically shown on a K-map as an ‘X’ and is an abbreviation
to show the designer that the specific minterm where the ‘X’ is marked, can either be
taken as a logic 1 or a logic 0. Thus, the grouping of terms as discussed above is much
easier if don’t care conditions are included. Note, do not confuse this with the input
variables X1 X2 etc.

1.6.2 Representing Boolean Terms

Sum-of-Products

As mentioned below, minterms consist of all the product (AND) terms that can
possibly exist for a function and that appear once. Given n variables, 2n product
terms exist for that function. For example, a function that supports 3 variables

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Notes will have 23 or 8 individual product terms.The notation used for a function F,
that has three variables, X, Y & Z can be described by it’s minterms, m. The
Boolean function F can be expressed as the logical sum of minterms that produces
a logic 1 or true output for that function. For example the function F can be
represented by minterms 0, 2, 5 and 7 that cause F to be true. This can be represented
by the expression:

The corresponding truth-table representing (1), is shown in Table below:

Truth Table Representing F

The expanded expression can be written as:

Note the four product or AND terms in (2), where each term relates to a
corresponding line and minterm entry in Table. Each of these product terms is
summed (OR’ed), together to form a Sum-of-Products. If all the
minterms (every line in Table), were true then the complete function would be
true i.e., F = 1. Due to the complexity of some expressions the notation used in
(1) is preferred with the exception of extremely simple expressions.
The expanded function F can be represented in diagrammatic form as shown in
Figure below. The Karnaugh map in Table below show how the simplification
can lead to a simplified circuit shown in next Figure.

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 Unit 1 - Basic Gates and Boolean Algebra

Notes

Figure 1.29: Expanded Function F

Karnaugh Map of Function F

Function F After Reduction

Product of Sums
From the previous example using function F, a Product of Sums can be can be
expressed as:

The corresponding truth-table representing the mathematical expression (3), is shown

in Table below:

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Digital Logic Circuits & Microprocessors

Notes

Truth Table Representing F & F’

Another way of interpreting above Table is to write each line where the complement
of the function, is true:

To simplify function F but by using the Product of Sums, we can graphically represent
the function F, defined in Table above but this time collect the logic 0 terms and not
the logic 1 terms as we did earlier. This technique is shown in Table below-

Collecting Complementary Terms of F

Note: The Dual is obtained by taking the De Morgan of the whole function, then each
term.

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 Unit 1 - Basic Gates and Boolean Algebra

1.7 TABULATION METHOD WITH DON’T CARES Notes

In order to understand the tabular method of minimisation, it is better to
understand the numerical assignment of Karnaugh map cells and the incompletely
specified functions also known as the can’t happen conditions. This is because the
tabular method is based on these principles.
The tabular method which is also known as the Quine-McCluskey method is
particularly useful when minimising functions having a large number of
variables, e.g. The six-variable functions. Computer programs have been
developed employing this algorithm. The method reduces a function in standard
sum of products form to a set of prime implicants from which as many variables are
eliminated as possible. These prime implicants are then examined to see if some are
redundant.
The tabular method makes repeated use of the law A + = 1. Note that Binary
notation is used for the function, although decimal notation is also used for the
functions. As usual a variable in true form is denoted by 1, in inverted form by 0,
and the abscence of a variable by a dash ( - ).

1.7.1 Rules of Tabular Method

Consider a function of three variables f(A, B, C):

Consider the function:

Listing the two minterms shows they can be combined

Now consider the following:

Note that these variables cannot be combined

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Notes
This is because the FIRST RULE of the Tabular method for two terms to combine,
and thus eliminate one variable, is that they must differ in only one digit position.
Bear in mind that when two terms are combined, one of the combined terms
has one digit more at logic 1 than the other combined term. This indicates that the
number of 1’s in a term is significant and is referred to as its index.

For example: f(A, B, C, D)

0000...................Index 0
0010, 1000.............Index 1
1010, 0011, 1001.......Index 2
1110, 1011.............Index 3
1111...................Index 4
The necessary condition for combining two terms is that the indices of the two
terms must differ by one logic variable which must also be the same.

EXAMPLES
Example 1 Consider the function: Z = f(A,B,C) = + C+A +
A C

To make things easier, change the function into binary notation with index
value and decimal value.

Tabulate the index groups in a column and insert the decimal value
alongside.

From the first list, we combine terms that differ by 1 digit only from one index
group to the next. These terms from the first list are then seperated into groups
group to the next. These terms from the first list are then seperated into groups
in the second list. Note that the ticks are just there to show that one term has
been combined with another term. From the second list we can see that the
expression is now reduced to: Z = + + C+A

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 Unit 1 - Basic Gates and Boolean Algebra

 From the second list note that the term having an index of 0 can be Notes
combined with the terms of index 1. Bear in mind that the dash indicates a
missing variable and must line up in order to get a third list. The final
simplified expression is: Z =
 Bear in mind that any unticked terms in any list must be included in the
final expression (none occured here except from the last list). Note that the
only prime implicant here is Z =.
 The tabular method reduces the function to a set of prime implicants.
 Note that the above solution can be derived algebraically. Attempt this
in your notes.
Example 2 Consider the function f(A, B, C, D) = (0,1,2,3,5,7,8,10,12,13,15), note that
this is in decimal form.
(0000,0001,0010,0011,0101,0111,1000,1010,1100,1101,1111) in binary
form.
(0,1,1,2,2,3,1,2,2,3,4) in the index form.

The prime implicants are:

The chart is used to remove redundant prime implicants. A grid is prepared
having all the prime implicants listed at the left and all the minterms of the
function along the top. Each minterm covered by a given prime implicant is
marked in the appropriate position.

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Digital Logic Circuits & Microprocessors

Notes

From the above chart, BD is an essential prime implicant. It is the only

prime implicant that covers the minterm decimal 15 and it also includes 5, 7
and 13. BD is also an essential prime implicant. It is the only prime implicant
that covers the minterm denoted by decimal 10 and it also includes the terms 0,
2 and 8. The other minterms of the function are 1, 3 and 12. Minterm 1 is
present in AB and ADD . Similarly for minterm 3. We can therefore use either
of these prime implicants for these minterms. Minterm 12 is present in
and ABC , so again either can be used.
Thus, one minimal solution is: Z = + BD + +A

Sometimes a situation arises in which some input variable combinations are not
allowed.
BCD code has six invalid combinations: 1010, 1011, 1100, 1101, 1110, and
1111.
Since these allowed states will never occur in an application involving the
BCD code, they can be treated as don’t care terms with respect to their effect
on the output. The don’t care terms can be used to advantage on the K-map.

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 Unit 1 - Basic Gates and Boolean Algebra

Notes

Figure 1.30: Don’t care terms

Without the don’t care terms the simplifies expression is Y  AB C  A BCD

Whereas considering the don’t care terms, the expression turns out to be Y  A  BCD

Simplification When Don’t-Care Terms are Present

Example: Reduce S = Sm(1, 2, 4, 5, 6, 8, 9, 12) + d(3, 10, 13, 15).
S = c′ d + bc′ + ac′ + a′ b′ d +a′ cd′ (1)
From the K-map, we obtain the resultant expression as the same one given by Eq. (1).

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Notes Table 1.1: Group and Reduced Form

Group Group members Elimination Reduced

Function
0 0 0 1
0 1 0 1 c′d
A 1, 5, 9, 13, 1 0 0 1
1 1 0 1
0 1 0 0
4, 5, 12, 13 0 1 0 1 b c′
B 1 1 0 0
1 1 0 1
1 0 0 0
8, 9, 12, 13 1 0 0 1
C 1 1 0 0 a c′
1 1 0 1
F 2, 6 0 01 0 a′ c d′
0 11 0

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 Unit 1 - Basic Gates and Boolean Algebra

Notes

Check Your Progress 2

1. Define Boolean algebra.
……………………………………………………………………………
……………………………………………………………………………
2. Name of the scientist who give the Boolean expression theorem.
……………………………………………………………………………
…………………………………………………………………………
3. Define Boolean function.
…………………………………………………………………………
…………………………………………………………………………

1.8 LET US SUM UP

Digital computers and all the digital circuits make use of 1s and 0s. Logic gates
are digital circuits with two states: TRUE and FALSE. Basic logic gates
include NOT, OR and AND gates. Some other logic gates include NOR,
NAND and XOR gate. NAND and NOR gates are also called universal gates
because all the three basic gates can be implemented using these two gates.
The traditional methods of simplification of Boolean expressions have been
discussed. The logic expressions can be expressed in one of the standard forms
SOP or POS and then simplified using K-maps. This saves on hardware in
terms of number of gates required and the number of input terminals of the
gates. K-maps can be conveniently used for 4 variables. After the K-map
another method tabular method for simplification has been presented.

1.9 LESSON END ACTIVITY

Why NAND and NOR gates are called Universal gates?

1.10 KEYWORDS
AND Gate: A gate with two or more input signals but only one output signal. All the
inputs must be high to get a high output.
Gate: A circuit with one or more input signals but only one output signal.
NAND Gate: A gate with two or more input signals but only one output signal such
that at least one input must be low to get a high output.
NOR Gate: A gate with two or more input signals but only one output signal such that
all inputs must be low to get a high output.

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Digital Logic Circuits & Microprocessors

Notes NOT Gate: A gate with only one input signal and one output signal. The output state
is always opposite of the input state.
OR Gate: A gate with two or more input signals but only one output signal such that if
any one or more input signal is high, output signal is high.
XOR Gate: A gate with two inputs and a single output which goes high
whenever one and only one input line is high.

1.11 QUESTIONS FOR DISCUSSION

1. Simplify the Boolean function
F (A, B, C, D) =  ( 1, 3, 5, 7, 11, 15)
Using k-map
2. Simplify the following function in sum of products:
F (A, B, C, D) =  ( 0, 7, 8, 10, 12)
d =  (2, 6, 11)
where d is a function of don't care conditions.
3. Simplify the following function in sum of products Product of sums form:
F (A, B, C, D) =  ( 0, 7, 8, 10, 12)
d =  (2, 6, 11)
where d is a function of don't care conditions.
4. Simplify the following function in POS form
F (A, B, C, D) =  (1, 3, 4, 5, 9, 13, 14, 15)
D =  (2, 6, 11)
5. Simplify the following function using 5-variable K-map.
F (V, W, X, Y, Z) =  (2, 3, 6, 7, 10, 12, 13, 14, 22, 28, 30).
6. What are Logic Gates? What is Truth Table? Show Truth Table & Logic Diagram
of X-OR Gate.
7. Write Truth Table of NAND, NOR, XOR and X-NOR Gate. Construct NAND
gate from NOR gate.
8. Construct NOR gate from NAND gate.
9. Explain what K-map is and what its use is. Explain how K-Map method can be
used to minimize a 5-variable function.
10. Inspect each of these Boolean expressions, and determine whether each
one is a sum of products, or a product of sums

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 Unit 1 - Basic Gates and Boolean Algebra

(B + C + D)(A + B) Notes
A B C + A BC
(X + Y + Z)(Y+ Z)(X + Y)
M N O + MN O + M N O
(X + Y + Z)(Y + Z)
ABC + A B C
11. Sum-of-Product Boolean expressions all follow the same general form. As such,
their equivalent logic gate circuits likewise follow a common form. Translate each of
these SOP expressions into its equivalent logic gate circuit:
AB + A B
AB+AB
ABC + A B C + AB C

Check Your Progress: Model Answers

CYP 1
1. Logic gate an electronic circuit which operates on one or more input
signals to produce standard output signals.
2. Truth table of NOT gate
Input Output
0 1
1 0

3. AND, OR, NOT and EX-OR

CYP 2
1. Boolean algebra an algebra that deals with logical propositions which are
either true or false and to simplify such propositions.
2. Gorge Boole
3. A mathematical function in Boolean algebra. For example, w = x + y.z

1.12 SUGGESTED READINGS

 Langholx, Kandel, Gideon Longholx, Abraham Kandel, Joe L. Mott,
Foundations of Digital Logic Design, World Scientific.

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Digital Logic Circuits & Microprocessors

Notes  Farhat A. Farhat, Hassan A. Farhat, Digital Design and Computer

Organization, Press
 M. Morris Mano, Computer System Architecture, 3rd Edition, Prentice Hall
 Linda Null, Julia Lobur, The Essentials of Computer Organization and
Architecture, 2nd edition, Jones & Bartlett Pub
 M. Morris Mano, Digital Logic & Computer Design, PHI, 2006.
 Alan B. Marcovitz, Introduction to Logic Design, 2nd Edition, TMH, 2005
 R.P. Jain, Modern Digital Electronics, TMH.
 Stallings, Computer Organisation and Architecture, 2nd Edition, PHI
 Rhyne, V.T., Fundamentals of Digital Systems Design, Englewood Cliffs, N.J,
PHI.

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