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Section C - Digital MCQ3

The document contains 16 multiple choice questions about sequential circuits and digital electronics topics like counters, flip-flops, and registers. Some key details covered are that a mod-16 counter requires 4 flip-flops, a toggle in a JK flip-flop changes the output to the opposite state, and synchronous counters eliminate delay problems by applying clock pulses simultaneously to each stage.

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34 views3 pages

Section C - Digital MCQ3

The document contains 16 multiple choice questions about sequential circuits and digital electronics topics like counters, flip-flops, and registers. Some key details covered are that a mod-16 counter requires 4 flip-flops, a toggle in a JK flip-flop changes the output to the opposite state, and synchronous counters eliminate delay problems by applying clock pulses simultaneously to each stage.

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We take content rights seriously. If you suspect this is your content, claim it here.
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PreCAT – Section C – Digital Electronics

Sequential Circuits
Question 1: How many Flip-Flops are required for mod–16 counter?
A. 5
B. 6
C. 3
D. 4

Question 2: In a JK Flip-Flop, toggle means


A. Set Q = 1 and Q = 0.
B. Set Q = 0 and Q = 1.
C. Change the output to the opposite state.
D. No change in output.

Question 3: A ring counter consisting of five Flip-Flops will have


A. 5 states
B. 10 states
C. 32 states
D. Infinite

Question 4: How many flip flops are required to construct a decade counter
A. 10
B. 3
C. 4
D. 2

Question 5: For JK flip flop with J=1, K=0, the output after clock pulse will be
A. 0
B. 1
C. no change
D. None of the above

Question 6: The output of SR flip flop when S=1, R=0 is


A. 1
B. 0
C. No change
D. None of the above

Question 7: Which statement BEST describes the operation of a negative-edge-triggered D flip-


flop?

Sunbeam Institute of information Technology, Pune


PreCAT – Section C – Digital Electronics

A. The logic level at the D input is transferred to Q on NGT of CLK.


B. the Q output is ALWAYS identical to the CLK input if the D input is HIGH.
C. the Q output is ALWAYS identical to the D input when CLK = PGT.
D. the Q output is ALWAYS identical to the D input.

Question 8: Synchronous counters eliminate the delay problems encountered with


asynchronous counters because the:
A. input clock pulses are applied only to the first and last stages
B. input clock pulses are applied only to the last stage
C. input clock pulses are not used to activate any of the counter stages
D. input clock pulses are applied simultaneously to each stage

Question 9: How many different states does a 3-bit asynchronous counter have?
A. 2
B. 4
C. 8
D. 6

Question 10: The bit sequence 0010 is serially entered (right-most bit first) into a 4-bit parallel
out shift register that is initially clear. What are the Q outputs after two clock pulses?
A. 0000
B. 1000
C. 0010
D. 1111

Question 11: Determine the number of flip flops needed to construct a register capable of
storing octal number up to 10.
A. 5
B. 4
C. 8
D. 10

Question 12: Assume that 4 bit counter starts in the 0000 state. What will be the count after 12
input pulses?
A. 12
B. 11
C. 10
D. None of these

Sunbeam Institute of information Technology, Pune


PreCAT – Section C – Digital Electronics

Question 13: Johnsons and Ring counter are


A. Asynchronous counters
B. synchronous counters
C. Both A and B
D. None of the above

Question 14: The output of a JK flip flop with clear inputs is ‘1’. The output can be changed to
‘0’ with one of the following conditions.
A. J=K=0 and clock
B. J=1, K=0 and clock
C. J=K=1 and clock
D. J=0, K=1 and clock

Question 15: The terminal count of a modulus-11 binary counter is ________.


A. 1010
B. 1000
C. 1001
D. 1100

Question 16: On the third clock pulse, a 4-bit Johnson sequence is Q0 = 1, Q1 = 1, Q2 = 1, and Q3
= 0. On the fourth clock pulse, the sequence is ________
A. Q0 = 1, Q1 = 1, Q2 = 1, Q3 = 1
B. Q0 = 1, Q1 = 1, Q2 = 0, Q3 = 0
C. Q0 = 1, Q1 = 0, Q2 = 0, Q3 = 0
D. Q0 = 0, Q1 = 0, Q2 = 0, Q3 = 0

Sunbeam Institute of information Technology, Pune

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