Sihf 9640
Sihf 9640
Sihf 9640
www.vishay.com
Vishay Siliconix
Power MOSFET
FEATURES
PRODUCT SUMMARY • Surface mount
VDS (V) -200 • Available in tape and reel
RDS(on) () VGS = -10 V 0.50 • Dynamic dV/dt rating
Available
• Repetitive avalanche rated
Qg max. (nC) 44
• P-channel
Qgs (nC) 7.1 • Fast switching Available
ORDERING INFORMATION
Package D2PAK (TO-263) D2PAK (TO-263) D2PAK (TO-263) I2PAK (TO-262)
Lead (Pb)-free and Halogen-free SiHF9640S-GE3 - - SiHF9640L-GE3
IRF9640SPbF IRF9640STRLPbF a IRF9640STRRPbF a IRF9640LPbF
Lead (Pb)-free
SiHF9640S-E3 SiHF9640STL-E3 a SiHF9640STR-E3 a SiHF9640L-E3
Note
a. See device orientation.
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)
PARAMETER SYMBOL LIMIT UNIT
Drain-Source Voltage VDS -200
V
Gate-Source Voltage VGS ± 20
TC = 25 °C -11
Continuous Drain Current VGS at -10 V ID
TC = 100 °C -6.8 A
Pulsed Drain Current a IDM -44
Linear Derating Factor 1.0
W/°C
Linear Derating Factor (PCB mount) e 0.025
Single Pulse Avalanche Energy b EAS 700 mJ
Avalanche Current a IAR -11 A
Repetitive Avalanche Energy a EAR 13 mJ
Maximum Power Dissipation TC = 25 °C 125
PD W
Maximum Power Dissipation (PCB mount) e TA = 25 °C 3.0
Peak Diode Recovery dV/d c dV/dt -5.0 V/ns
Operating Junction and Storage Temperature Range TJ, Tstg -55 to +150
°C
Soldering Recommendations (Peak temperature) d for 10 s 300
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. VDD = -50 V, starting TJ = 25 °C, L = 8.7 mH, Rg = 25 , IAS = -11 A (see fig. 12).
c. ISD -11 A, dI/dt 150 A/μs, VDD VDS, TJ 150 °C.
d. 1.6 mm from case.
e. When mounted on 1" square PCB (FR-4 or G-10 material).
- 7.0 V
- 6.0 V
- 5.5 V 2.0
(Normalized)
- 5.0 V
101 Bottom - 4.5 V
1.5
1.0
- 4.5 V
0.5
20 µs Pulse Width
TC = 25 °C
100 0.0
100 101 - 60 - 40 - 20 0 20 40 60 80 100 120 140 160
91087_01 - VDS, Drain-to-Source Voltage (V) 91087_04 TJ, Junction Temperature (°C)
VGS 2400
VGS = 0 V, f = 1 MHz
Top - 15 V Ciss = Cgs + Cgd, Cds Shorted
- 10 V 2000 Crss = Cgd
- 8.0 V
- ID, Drain Current (A)
- 6.0 V 1600
101
- 5.5 V
Ciss
- 5.0 V
Bottom - 4.5 V 1200
800
- 4.5 V
Coss
400
20 µs Pulse Width Crss
TC = 150 °C
100 0
100 101 100 101
91087_02 - VDS, Drain-to-Source Voltage (V) 91087_05 - VDS, Drain-to-Source Voltage (V)
Fig. 2 - Typical Output Characteristics, TC = 150 °C Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
20
ID = - 11 A
- VGS, Gate-to-Source Voltage (V)
VDS = - 160 V
16
- ID, Drain Current (A)
100 4
20 µs Pulse Width For test circuit
VDS = - 50 V see figure 13
0
4 5 6 7 8 9 10 0 10 20 30 40 50 60
91087_03 - VGS, Gate-to-Source Voltage (V) 91087_06 QG, Total Gate Charge (nC)
Fig. 3 - Typical Transfer Characteristics Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
12
- ISD, Reverse Drain Current (A)
10
25 °C
150 °C 6
100
4
VGS = 0 V
10-1 0
0.0 1.0 2.0 3.0 4.0 5.0 25 50 75 100 125 150
91087_07 - VSD, Source-to-Drain Voltage (V) 91087_09 TC, Case Temperature (°C)
Fig. 7 - Typical Source-Drain Diode Forward Voltage Fig. 9 - Maximum Drain Current vs. Case Temperature
RD
102 VDS
Operation in this area limited
by RDS(on)
5 VGS
10 µs
D.U.T.
- ID, Drain Current (A)
Rg -
2 +VDD
100 µs
10 - 10 V
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
5 1 ms
Fig. 10a - Switching Time Test Circuit
2 TC = 25 °C
TJ = 150 °C 10 ms
td(on) tr td(off) tf
Single Pulse
1 VGS
2 5 2 5 2 5
1 10 102 103 10 %
91087_08 - VDS, Drain-to-Source Voltage (V)
10
Thermal Response (ZthJC)
1
D = 0.50
PDM
0.20
0.1 0.10 t1
0.05 t2
Single Pulse Notes:
0.02
(Thermal Response) 1. Duty Factor, D = t1/t2
0.01
2. Peak Tj = PDM x ZthJC + TC
10-2
10-5 10-4 10-3 10-2 0.1 1 10
L IAS
VDS
Vary tp to obtain
required IAS
VDS
Rg D.U.T
-
+ V DD
IAS VDD
- 10 V tp
tp 0.01 Ω
VDS
Fig. 12a - Unclamped Inductive Test Circuit Fig. 12b - Unclamped Inductive Waveforms
1600
ID
EAS, Single Pulse Energy (mJ)
Top - 4.9 A
- 7.0 A
1200 Bottom - 11 A
800
400
VDD = - 50 V
0
25 50 75 100 125 150
Current regulator
Same type as D.U.T.
QG 50 kΩ
- 10 V 12 V 0.2 µF
0.3 µF
QGS QGD -
D.U.T. + VDS
VG
VGS
- 3 mA
Charge
IG ID
Current sampling resistors
Fig. 13a - Basic Gate Charge Waveform Fig. 13b - Gate Charge Test Circuit
- - +
Rg • dV/dt controlled by Rg +
• ISD controlled by duty factor “D” VDD
• D.U.T. - device under test -
Note
• Compliment N-Channel of D.U.T. for driver
VGS = - 10 Va
Reverse
recovery Body diode forward
current current
dI/dt
D.U.T. VDS waveform
Diode recovery
dV/dt
VDD
Re-applied
voltage
Body diode forward drop
Inductor current
ISD
Ripple ≤ 5 %
Note
a. VGS = - 5 V for logic level and - 3 V drive devices
A
2 x b2
2xb c
E
0.010 M A M B
± 0.004 M B
2xe
Base
5 metal D1
Plating 4
b1, b3
(c) c1 5
(b, b2)
Lead tip Section B - B and C - C E1 4
Scale: none View A - A
A
L1
Seating
D1
plane
D
C C
L2
B B L
A
c
3 x b2 E1
3xb A1 Section A - A
2xe Base
metal
Plating b1, b3
0.010 M A M B
c c1
(b, b2)
Lead tip
Section B - B and C - C
Scale: None
0.420
(10.668)
(9.017)
0.355
(16.129)
0.635
0.145
(3.683)
0.135
(3.429)
0.200 0.050
(5.080) (1.257)
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