An Introduction to DFT

Built In Self Test (BIST) | Topic 8 of 10

 “ Abstract
So far we have considered the fault identifaction methods which actually required
a physical tester after fabrication to apply patterns & observe responses; but
sometimes it become necessary to test circuits before every opearions and the
test can be done very easily without a bulky tester, even end user can test
whenever it is necessary and most importantly at the application site; here in this
module we are going to consider such scenarios and method to perform a fault
test in such cases, also there are few more cases are there where in field testing
is required, that also is going to be considered as well.
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Where We are?

Fault Models Pattern Generation DFT Techniques

• Stuck at faults • Pattern • Scan Insertion
• Bridging faults generation • Scanned
• Delay faults • Fault simulation Flipflop
• Switch level • ATPG • Boundary scan
• Pattern (JTAG)
faults
generation • BIST
algorithms

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What is BIST?

• BIST stands for Built In self test, which enables the testing personal
to test a design without using an external automated test equipment
(ATE), which is usually used in post-production testing
• BIST are a couple of techniques which includes additional hardware
and software features into integrated circuits to allow them to perform
testing of their own operation (functionally, parametrically, or both)
using their own circuits

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Goals for adapting BIST?

• With the increasing complexity & clock speed the use of a general automated
test equipment (ATE) doesn’t suffice the testability of an IC
• Modern SoC usually includes multiple high-speed clocks and testing those
circuitry at their operational frequencies becomes a challenge for ATE
• BIST is also the solution to the testing of critical circuits that have no direct
connections to external pins, such as embedded memories, sometimes analog
blocks used internally by the devices
• BIST enables us to use simple interface which can be used to create software-
based testing mechanism reducing the cost of post-production testing of IC

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Advantages of implementing BIST

• lower cost of test, since the need for external electrical testing using an ATE will
be reduced, if not eliminated
• shorter test times if the BIST can be designed to test more structures in parallel
• Better fault coverage, since special test structures can be incorporated onto the
chips at the desired location according to the type of application circuitry (Analog,
digital, or memory)
• One of the advantages of BIST is it provides us the opportunity to test the circuit
at its intended frequency
• Provides the capability to perform tests outside the production electrical testing
environment
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Disadvantages of implementing BIST

• Area Overhead: Additional active area due to test controller, pattern

generator, response evaluator and testing of BIST hardware (which is
complex than simpler SC insertion)
• Pin Overhead: At least 1 additional pin is needed to activate BIST
operation. Input MUX adds extra pin overheads
• Possible issues with the correctness of BIST results, since the on-chip
testing hardware itself can fail, so we need simpler DFT methods (SC)
to ensure that the BIST circuit is not faulty

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General block diagram of BIST?

• The basic BIST

architecture requires the
addition of three
hardware blocks to a
digital circuit:
1. A test pattern generator,
2. A response analyzer, Normal
input

3. A test controller
Courtesy: course on BIST/DFT, IIT Kharagpur
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How BIST works?

• In normal operation, the CUT receives its inputs from other modules
and performs the function for which it was designed
• A mode selector, at the MUX select input signal is used to switch
from functional mode to test mode
• During test mode, a test pattern generator circuit applies a sequence
of test patterns to the CUT, and the test responses are evaluated by
an output response compactor
• If obtained patterns are matching with the expected previously stored
patterns, then we can tell if the CUT is good / faulty
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How BIST works?

• In the most common type of BIST, test responses are compacted in

output response compactor to form (fault) signatures,
• The response signatures are compared with reference golden
signatures generated or stored onchip ROM, and the error signal
indicates whether chip is good or faulty
• As the responses of the patterns are stored in a ROM as a golden
refernce, one of the key element in desining BIST systems to compact
the responses from a CUT so that a compressed version of responses
can be stored in the ROM as a golden reference

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H/W pattern generator

• We know the heart of a testing facility is a way to generate patterns,

and if the patterns generator is itself situated in the vicinity of the
design, it would be fast, accurate also less expensive
• Its primary functionality is to Generate patterns so that the test
controller can send it to circuit Under Test (CUT)
• The ways in which modern ATPG generates patterns are based on
some sophesticated algorithms which is ran on a dedicated
processing elements in a tester
• The same ATPG process can’t be reused in Si designs and also is
not practically feasible
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H/W pattern generator

• Rather some simple mechanism should be used which is practically

possible to fabricate alongside of the design and provide effortless
streams of patterns to design
•
-
Types of Hardware PG:

-
Stored patterns

-
Exhaustive patterns

-
Pseudo-exhaustive patterns

-
Pseudo-Random Pattern Generation

-
Pattern Generation by Counter
Weighted Pseudo-random Pattern Generation
Note: Some important categories of pattern generation will be considered
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H/W PG | Stored Pattern

• An ATPG process previously generates the required patterns and the

patterns are stored in a ROM
• When BIST is activated, test patterns are applied to the CUT and the
responses are compared with the corresponding stored patterns,
called a Golden response
• Stored-pattern BIST can provide excellent fault coverage, it has
limited applicability due to its high area overhead

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H/W PG | Exhaustive Pattern

• Exhaustive testing is something which applies each and every possible combination
(2n) for an n input pins
• Although it has very high fault coverage it has very high time overhead, and if
required in any BIST mechanism can be generated with the simple circuit below:

• Circuit is basically a simple counter mechanism

which travers through a set of predefined states
which is governed by combinationals logics
before flop inputs
• It has 3 flops and able to produce a maximum
2^3 or 8 patterns

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H/W PG | Pseudo-Random

• Random patterns are one of the parts of the PG processes where we can quickly try
to identify some faults and based on the identification we discard some faults from
the fault list speeding up the PG process
• One of the processes of random pattern generation is to use Linear Feedback Shift
Register (LSFR), though is not purely random in nature but the random outputs are
repeated after a very long time if we carefully design a LSFR, the scheme is
popularly known as a pseudo-random pattern generation

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H/W PG | Pseudo-Random | LSFR

• A linear feedback shift register is a shift register with feedback paths which consist
only of unit delays and XOR operators (Linear operator), a general diagram has
been shown as below:
• There are n flip-flops
(Xn-1,……X0), (hn-1,
hn-2, ..., h1) are some
weights which are
multiplecative
• From the figure it is clear
that the present state of a
output is module sum of
other flops
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H/W PG | Pseudo-Random | LSFR

Let’s take an example: Table: 1

+
+
1 0 0 0

= , now using 1 1 0 0
1 1 1 0
asynchronous inputs of the flops if 1 1 1 1
we initialize the value 1000, the 0 1 1 1

state table would look like table1, 1 0 1 1

If we change the initial value 1000 to a different one, the circuit will go 0 1 0 1
1 0 1 0
through different states, thus by changing the inital (sometime called 1 1 0 1
seed) we are able to generate some random value, more precisely 0 1 1 0

psudo random values which can be used in pattern generation in BIST 0 1 1 0

0 0 1 1
cicuits
1 0 0 1
0 1 0 0
0 0 0 1
1 0 0 0

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H/W PG

• While Implementing a BIST strategy, the main issues are fault coverage,
hardware overhead, test time overhead, and design efforts
• To find a pattern generation method which is a complete in terms of all the
above mentioned points, optimization for each can be considered, here is a
table which might help identifying the PG methods for practical applications:

Courtesy: DFT lecture series, IIT Kharagpur

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Output Response Analyzer

• The task of response analyser is to compare the outcome of the H/W

Patterns from CUT to a golden or expected outcomes which is stored
onboard
• But sometimes, if the no of input ports of a module becomes large, the
responses from it becomes exponentially large and thus unmanagable, For
example, if we consider a circuit of 200 outputs and if we want to generate
5 million random patterns, then the CUT response to response analyser will
be 1 billion bits, practically unmanageable
• So, it is necessary to compact this enormous amount of circuit responses to
a manageable size that can be stored on the ROM chip, & the response
analyzer compresses a very long test response into a ‘single word’ called a
signature

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Output Response Analyzer

• The signature is then compared with the prestored ‘golden signature’

obtained from the fault-free responses using the same compression
mechanism, If the signature matches the golden copy, the CUT is regarded
fault-free; otherwise, faulty
• Note: Compression a reversible process used to reduce the size of the
response but is difficult in hardware VS Compaction an irreversible (lossy)
process used to reduce the size of the response
Patterns O/P responses Golden signature

Output
Pattern Response ? Faulty /
CUT =
Generator Analyzer Good
(ORA)
signature
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Output Response Analyzer

• Characteristics of a good ORA should be:

1. Small size of signature
2. Aliazing free signature
3. Circuit should consume small Silicon area
• Mathematically, ORA maps a certain symbol (response) from patterns
outputs space to a signature space, and type of mapping is many to one:

• A Faulty response never

O/P
Space O/P-1
Non-Aliasing
S-1
Signature
Space
points to a Golden Response,
where a good response O/P-2 S-2
always does
• But aliasing happends when O/P-r
both a faulty & good response G-2
maps to a golden response, O/P-N
which is not desireable Aliasing

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Output Response Analyzer

• So, aliasing is never desirable, as there are chances where a faulty output
can pass a test
• Also, a good response analyzer should produce alias free responses
• Aliasing give rise to reduce the coverage, which is a metrics of how much
faults are detectable out of a given set of faults
As, both {01} (faulty
{00} response) & {10}
1
(good response)
CUT S, signature {10} {1} produces golden
response {0}, XOR
0 ORA = XOR Gate {01} {0} gate is not good as
Good output is {10} & Golden signature = 1 {11} an ORA

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ORA Types

• There are a number of different types of ORA available:

1. Simple ORA:
- Duplication, Reverse operation
- Checksum (aka. Parity Checker)
- Ones counter
- Transition counter
2. LFSR-based ORA
• Each one of them has their own advantages &
disadvantages, analysis of each of them are beyond the
scope of this introductory course
For details: VLSI TEST PRINCIPLES AND ARCHITECTURES DESIGN FOR TESTABILITY, Laung-Terng
Wang, Cheng-Wen Wu, Xiaoqing Wen, Publisher: Elsvier
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ORA Types | LFSR

• LFSR can be used both for PG and ORA just by incorporating some input to the
LFSR structure
• But Method is slow, as shifiing operation is associated, for N flop LSFR after N
clock pulses the signature is generated

Used for TPG (Without any Input) Used for ORA (With an Input)

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BIST Types

• Based on Test Time:

1. On-line BIST:
- On-line testing while chip in normal operation
- e.g. error detection and correction for RAM
2. Off-line BIST:
- Off-line testing while chip not in normal operation
- e.g. testing CPU core IP etc.

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BIST Types

• Based on CUT:
1. LBIST: Logic BIST is used to test the circuits where logical circuitry is
involved and no embedded memories are used, as for example,
dedicated modules like CPU, GPU or DSP cores can be tested using
LBIST techniques
2. MBIST: Memory BIST is ued to test embedded memory elemets of a
circuits, for example an embedded RAM or a general RAM can be tested
with MBIST techniqes, MBIST are little bit complex as compared to
LBIST & requires special attention

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BIST Types

• The general testing structure (consists of TPG & ORA) which has been
shown in previous slides are generally used for LBIST operations, all the
basic Digital circuitry (or even some analog & ADC-DAC circuits are
tested using) are tested by using Logic BIST techniques
• However, embedded memories are one of the most complex and densed
structures (which requires their own fault models appart from previously
stated ones) are tested by using Memory BIST techniques, as they seek
special attention than LBIST

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Memory BIST | Typical Memory

Memory is the most-dense physical structure present in the design, which are highly
repetative and simple
Considering the increase density, memory arrays are more sensitive to defects, which
are modeled in uniques ways unlike Logic circuits

Typical Memory Model

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Memory BIST | Memory Faults

Typical Parts Fault Modes Fault Models

Memory Cells Data Storage Stuck-At (Single, Multiple),
transitional, Coupling
Neighborhood pattern sensitive
fault(NPSF) etc.
Data Bus Data Delivery Stuck-At (Single, Multiple),
transitional, transisitor faults,
Data Recovery bridging etc
Address Bus Address Recovery Stuck-At (Single, Multiple),
transitional, transisitor faults,
Address Delivery bridging etc
Controller Data Decode Stuck-At (Single, Multiple),
transitional, transisitor faults,
Address Decode bridging etc
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Memory BIST | Memory Fault Models

Stuck at fault model in memory:
We can have a single cell, or a group of cells
stuck to some constant value “0” or “1”
Fault exercise and detection: Write both 0 and 1
and read 0 and 1, respectively
Bridging fault model in memory:
Bridges can be 0 Ohm or resistive or diodic,
They can cause change in one or multiple cells
Fault exercise and detection: write and read
alternating or complementing patterns such as
0-F, 5-A etc. Diodic bridges may be sensitive
to address writing order
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Memory BIST | Memory Fault Models

Fault model in Decoder circuit :
stuck at faults result choosing always a wrong address
(location 1 &2) Vcc

bridges result always choosing multiple columns and rows

(location 3 & 4)
Given a certain address, no cell will be accessed
A certain cell is never accessed by any address
A certain cell can be accessed by multiple addresses

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Memory BIST | Memory Fault Models

Data retention fault model in Memory :

It means data changed after a certain time, though power is suplied to memory
Leakage or bridging may cause the stored data value to degrade over time
DRAM
1. Charge leakage loose data in capacitor
2. Refresh logic fails to refresh correctly
SRAM
Defective pull-up device inducing excessive leakage current
which changes the state of cell
Fault exercise and detection: put data in target memory cell and surround with
complementary values

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Memory BIST | Memory Fault Models

Other faults :
Sense amplifier recovery fault
Sense amp. saturated after reading/writing a long string of 0 or 1
Write recovery fault
A write followed by a read/write at a different location results in reading or writing at the
same location due to slow address decoder

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Memory BIST | Memory Test Algorithms

A Test algorithm is a finite sequence of test elements, which contains a number of:
1. Memory operations
Read or Write
2. Data pattern (aka. data background)
Zero or One (in single cell or in blocks)
3. Address sequence
Ascending or Descending
Test (time) Complexity of test algorithm is expressed in terms of number of memory cells
(N) under consideration, higher the memory higher is the complexity
Typical examples: MSCAN, Checkerboard, GALPAT, Butterfly, March

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MBIST | MSCAN & Cheakerboard Algo

MSCAN Cheakerboard
Steps: Steps:
1.Write zero to every cell 1. Write chkrbd pattern to all cells
2.Read zero from every cell 2. Read chkrbd pattern from all cells
3.Write one to every cell 3. Write chkrbd’ pattern to all cells
4.Read one from every cell 4. Read chkrbd’ pattern from all cells
Advantages: Detects all SAF Advantages: Detects all SAF, Bridging
Disadvantage: Complexity is in faults
the order 4N Disadvantage: Complexity is in the
order 4N
chkrbd means 01 alternatively, chkrbd’ is its complement,
Note: Other Algos are beyond the scope of the introductory course
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Typical MBIST Architecture

rd/wr or other
controll pin

Addr
Memory
Data

• Typically MBIST consists of a controller (manages the overall operation of the BIST circuit), a
sequencer and a TPG, we already have discussed TPG schemes used in BIST,
• The sequencer generates the address sequence and various memory access commands based
on the specifications of the memory under test. For example, the sequencer generates the read,
write, refresh, precharge, load_mode_register, active, and nop (no operation) commands for an
SDRAM, but only the read, write, and nop commands for a simple single-port SRAM

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BIST summary

• What is BIST, application, types MBIST/LBIST

• BIST Structure (TPG, ORA etc.)
• TPG schemes, LFSR as TPG & ORA
• MBIST fault models, MBIST basic algo (MSCAN, checkerboard),
MBIST architecture

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THANKS!
Any questions?
You can find me at linkedin.com/in/dastanmoy92/ or
[email protected]