STREAMING SCAN

NETWORK

Jayabharath P (1st module-videos 1,2,3,4,5,6,7,8,9,10).

MOTIVATION TO USE SSN
• Identify scan test problems(limites number of channels for test,
routing, timing closure, test time, data volume, planning and flow,
diagnosis and debug
• ROUTING AND TIMING-many cores ,large number of muxes and wires
• DIAGNOSIS AND DEBUG-many retarget modes, many pattern sets,flat
models to image
• SSN-limited number of cores can be tested and run diagnosis
parallely.
• In SSN failures captured on the tester are reverse mapped to block
level failures and layout diagnosis is performed
SSN
ARCHITECTURE
It is an synchronous N bit wide
bus ued to stream scan test
data
Scan data streamed through
SSN datapath ,SSH nodes
transfer data between the
datapath and the EDT/scan
chains.
SSN bus and SSH nodes can be
inserted at either RTL or gate
level and integrated into your
design manually or tessent tool.
SSN
MULTIPLEXER
AND PIPELINE
• MUX is bult with the retiming
pipeline stage
• It provides debug return from
ssn bus in to out
• Excledes blocks from datapath
• Pipeline is optionally inserted
into register ,it is used to
support timing closure along
the datapath
• It can be inserted at any point
along the datapath
SSH
• It was set bus register reset is
on ,this will enableall nodes to
reset the bus registers during
iReset
• After receiving the data from
ssn bus it is registered and it
reaches the first cloud of logic
• Scan test data delivered to ssh
over ssn in bundles called
packets
Packets can hold more than one
data, once it is directed to scan in
path other ssh scan in data will be
in untouched
 SSH
• After receiving packest from edt scan will be over written in ssn bus
• SSH transfers the packet into ssn bus through ssn bus out
• It is synchronously driven into the output network
• Important feature is scan signals controlling the state of the scan
circuitry for each physical block are local generated within the SSH
node
• Clk gen generated the scan enable,edt clock,edt update,shift capture
clock,it transists the circuit between shift and capture independently
SSH
• If edt is active ssh also be in active otherwise it just pass the dat
through 2 stage pipeline
• Loopback mux will direct the scan data again to register it will check
the ssh internal logic whether it is not having we error if it is it will be
neglected.
• Ijtag will be inserted in tool automation .
SCAN DATA STREAMING PACKETS
• SSN node can be reset through the ijtag reset ,it reset the registers in
the SSN
• SSn bus width is not dependent on the scanned cores and edt
number of channels ,it is dependent on the availability of the pins
• It is efficient like design floorplaning relies core content
• Payload from tester ,Packet is a scan data needed for single shift
operation.
SCAN DATA
STREAMING
PACKETS
• Total 9 bits required for edt,
• Two blocks are not connected
serially,it is separated and 4bit
scan word given to block B and
5bit for block A.
• Packet size is 9 bit but bus size
is 8 bit ,so one bit is wrapped to
other packet
• In packet 0 from block A 5 bits
and block B 3 bits clocked to edt
• In Next cycle pending bit is
clocked with remaing bits from
packet 0 is untouched
SCAN STREAMING DATA PACKETS
• In the same clock cycle 7 bits is clocked.
• Additional packets are added until all scan data retrieved to the
network
• Two packets skew occurs.
• N bits per packet often exceeds the bus width when many edts are
running parallely
• Packets repeat with the fixed time slots for each active block
STANDARD
OCC
• JDBCJSCB
• Local clock injection
• Enables efficient pattern
retargeting
• Independent transition
between shift and capture
• Enables intta,inter domain
testing through synchronized
capture –uses only shift mude
feature only
• SSH locally generates clocking,
eases no crossing the hierarchy
boundary
SSN
RETARGETING
USING STANDARD
OCC
• Standard occ in each
wrapped block
• SSH node generates local
shift clock, enables local shift
clock injection and scan
enable.
• Independent transition
between shift capture
• If you synchronize the
capture using padding it is an
non ssn patterns
SSN INTER AND INTRA
BLOCK DOMAIN
TESTING USING OCC

• Block SSH stll generates local

shift clock,occ enables
injection of local shift clock
• Ssh nodes captured are
aligned ,edt chains continue
to be ready at different times
• Block level occ are
transparent during capture ,
built with shift only mode so
capture is synchronized
• Synchronized capture with
chain load tuning per pattern
INTRA ,INTER DOMAIN TESTING
• Core b , c are placed inside the core a ,internal edt placed in core b,c
• Intra domain is tested with inter domain path through capture cycle
because of synchronization but shift will be independent.
• Bandwidth tuning ssn is due to the adjustment of padding.
BANDWIDTH
TUNING IN SSN
• Cores with lower pattern
counts will repeat the last
pattern repeatedly and waits
for other cores to complete the
pattern
• It wastes the time lot of
bandwidth
• Only G and S has used the cycle
others are wasted
• So calculate the total bits
180,bus width is 32,so 6
channels required
• From that controlling fill rate
we will achieve the tuning
BANDWIDTH
TUNING
METHOD
• If you control in the SSN
nodes with different fill rates
according to the core
• Initiall core is larger size so
pattern filling is very fast rate
• Small core have slow fill rate
• Patterns cycles will not be
wasted on retargeting
BANDWIDTH
AFTER TUNING
Almost every core has used
cycle more than thewasted
cycle
Tuning done automatically
while retargeting
SSN VERIFICATION
USING LOOPBACK
PATTERN

• ssn nodes verifying with the

continuity patterns
• Simulate the loopback
patterns and verify the SSH
functionality,verify packet
format for given ssn
configuration
• Verify networks ability to
deliver packetized data
• In simulation Run the
patterns during scan pattern
verification
VERIFYING SSN PATH with ICL
• To ensure any potentialproblems are captured in the flow
• SSN retargets DRC,Testbenches(ICL.loopback,continuity patterns)
SSN NODES VERIFYING WITH ICL
• Verifying serial access path to all SSN registers,ICL semantic rule
checks
• Verifies serial access through scan host interface and write,read
access to ijtag registers
VERIFYINF SSN PATH AND
CREATINGLOOPBACK PATTERNS
VERIFYING SSN WITH CONTINUITY PATTERNS
• Simulating the continuity patterns,testbench configuration based on
the mux,specified instances
• Use SSN continuity patterns during integration by verifying the
datapath
CREATING SSN CONTINUITY PATTERNS
• Created from ICL model of current design,automatically created with
create _patterns_specification
• Use iproc to configure Mux along datapath,simulate with run
testbenchpatterns.
SSN DRC
• SSN_R1-verifies each SSH ICL module that the TCD for that
instrument is in memory;Handling –error,
• SSN_R3-ensures the SSH interfaces in TCD of the current design map
to SSH ICL instances; Handling –error
• SSN_R4- checks the connections between the EDT or uncompressed
scan chains connect only to a single SSh ; Handling- error
• SSN_R5-it verifies the presence of a pulse always clock with internal
capture SSN
SSN BLOCK LEVEL WORK FLOW
Jayabharath P 2nd module (video 1,2,3,4,,5,6,7,8,9)
BASIC TOOL FLOW
of BLOCK LEVEL SSN.
• Inserts no scan MBIST ,IJTAG in first
insertion and checks pass in simulation
• Inserts oss,edt,ssn with second pass
• Inserts the stitched chains for tha
added blackboxes after the synthesis
• Verify the ICL patterns by whether
read write are done by IJTAG registers.
• Generated the patterns for the stuck
at fault for respective inserted scan
chains of blackboxed memory instance
• Save the patterns and verify it
byssimulation.
SSN BLOCK
LEVEL FIRST DFT
INSERTION PASS
• Dft insertion for wrapped
core (processed core,where
gps baseband is bypassed
using mux)
• It is bottom up flow
• Set the design to processed
core and physical block
• Non scan mbist and ijtag
inserted and validated
• It consists of 2 memory
instance in block
FIRST DFT INSERTION
• Two pipeline stages one is transmitting end and other is receiving
ends
• SSN bus width is 2 bits
• Dft requirements Memory test on –will set mbist ,bisr chains,bisr
architecture.
• Check patterns with testbench and no mismatches will come
• Two passes will come at the simulation of pattern verification
SECOND DFT
INSERTION
• Add dft signals ltest enable,memory
bypass enable,tck_occ enable and required
signals.
• Dft requirements are logic test on which
sets edt, mttslogicbistf, mtmslogicbistf,
mlogicbistf, mtscanprof)
• Insert the three wrappers
1.edt,2.SSN,3.occ through sri sib switch list
• Ijtag will be an host interface it insert occ
then ssn then edt
SECOND DFT INSERTION.
• Ssn bus width is 2bits
• External Edt with2 chain and 1 channel for both input and output
• Internal edt is scan chain of 70,3 channels for both input and output
SSN BLOCK
LEVEL
SYNTHESIS AND
SCAN
INSERTION.
Wite import design scripts to
synthesize the inserted
wrappers
Insert the scan chains for the
blackboxes
Here memory instance is an
blackbox
Analyze the wrapper cells find
out the edt instances and edt
modes
Assign it to the scan modes
and scan chains were stitched
by creating the scan ports(20)
SSN BLOCK FLOW
FOR GENERATING
ATPG
For generating atpg patterns
externally run it in external box
by generating graybox.
In internal mode we can
retarget it to chip level for the
stuck at models
Set occ parameters for capture
timing
PATTERN GENERATION
• After creating patterns for the blackbox (memory instance ),simulate
it.
• Save the patterns in chain, SSH loopbach, SSH continuity, scan
formats.
• Four testbenches namely parallel load testbench, SSH loopback
testbench, chain patterns, scan patterns,SSH continuity testbenches
SSN PATTERN
VERIFICATION
Continuity patterns checks the
early detections in SSN datapath
Loopback patterns verifies it will
handle the packetized data and
checks SSH active ,it will not send
the scan data out,it will be looped
without EDT, scan.
Occ ptterns checks the timing
logic of on chip controller
Top level patterns checks the
scan test and chain patterns
ICL patterns verifies whether
write,read operation done by ijtag
register.
TESTBENCH PARAMETERS
SIM_PARALLEL_MONITOR- monitoring of scan load values on internal
scan nodes,limited to serial patterns
SIM_SSN_TIMING_CHECKS-SSN shift and capture timing checks
SIM_SSN_MAXIMUM_BUS_SPEED-packet is padded as needed so SSN
bus can run at maximum frequency.
SSN DATAPATH PLANNING
JAYABHARATH P(3 rd module-video 1,2,3)
SSN
DATAPATH
Connection between the input
and output ports
In datapath we insert mux,
pipeline,SSH host.five cores pad
io,block a,b,c,d.
Datapath will go through
hierarchies
In block d we can find extra
datapath can be sort out by
branching the ports.
Pipeline will handle timing
enclosure especially in edt
controllers(between SSN datapath
and logic circuitry)
SSN
DATAPATH
• Mux node is added and
exclusion of section of a
datapath
• While the multiplexer can be
programmed to include the
other instances.
SSN TOP LEVEL WORK FLOW
Jayabharath P
Video(1,2,3,4,5,6,)
SSN TOP LEVEL
WORK FLOW
• We build ijtag network for
wrapped cores at the top
level and insert the TAP
controller.
• We use Dft specification to
specify the physical order of
lowerlevel cores from
theSSN bus im to SSN bus out
 FIRST DFT INSERTION PASS
• Specify the TAP pins
• Define all clocks
• Configure the boundary scan to be used during logic test patterns
• Specify to add auxiliary muxes on inputs and outputs used for SSN
bus and clock.
• IJTAG graybox is a netlist of a physical block that describes only the
ICL logic of the block
• Second graybox netlist contains the IJTAG instruments and the
wrapper chains and logic between the wrapper chains.
 SECOND DFT INSERTION PASS
• Add DFT signals to support the automation with ATPG.
• Specify to create test logic
• Create DFT specification for OCC,EDT, SSN logic.
• EDT is connected automatically and includes boundary scan chain
segments.
• Three wrapeers (edt,occ,ssn)have its own wrapper and SIB
• Tool automatically maps thespecified port connections to the
corresponding data pins
SSN TOP LEVEL SYNTHESIS AND SCAN
INSERTION
• Synthesize the new DFT logic with the design using created
synthesized script
• If scan chains are inserted and stitched in synthesis ,follow that with
a TSDB view creation step
• Creating the post synthesis TSDB view occurs automatically as part of
the scan insertion when using tessent scan
• First find EDT instance and create scan mode for external test
• Load and specify iproc to include all SSH blocks, setup the OCC
capture window size.
• Create IJTAG graybox view of scan inserted design.
 TEST PATTERNS GENERATION
• Verify the ICL based patterns after synthesis
• Generate top level ATPG test patterns
• Retarget block level patterns to top level
• ICL BASED VERIFICATION-set and open the TSDB block ,read the top
design interface view and include lower level test IP in testbench and
load chip level iprocs and generate patterns to verify DFT logic at all
levels
• TEST PATTERNS GENERATION- create test patterns and write results
into the TSDB,write parallelel simution testbench patterns to verify
the patterns by simulation
PATTERNS RETARGETING
• Write the updated TCD file in TSDB
• Read the block patterns to retarget
• Create and write out simulation testbenches(parallel, loopback, serial
chain and scan).
ADVANCED SSN
Video(1,2,3,4,5,6)
ADVANCED SSN
TOPICS

• Requires slow clock injection

Mux and shift only mode
• For timing information about
a design is SDC- Synopsis
Design Constraints.
• Generated SDC with SSN
using SSN IPs
CLOCK TREE
TYPES
• Clock networks to use with
SSN bus clk
BFD and BFM are specified by
the user
SOURCE SYNCHRONOUS
TIMING
Always present between the
chip and ATE ,used also for
localized clock tree
Clock and data in delay must
match to within clock period.
CONCEPTS OF
LOOP TIMING
• Loop timing between the ATE
and the chip
• Where the timing path is
returned to the element
sourcing the clock.
• Clock in data out delay must
be less than fil clock period.
• Output pipeline stage clock
should be pulled from an
early branch of the CTS tree.
MANAGING
TIMING OF SSN
DATAPATH
• Place FIFI between or within
a physical block along the
datapath
• Smaller in area than using a
BFD and BFM pair
• Time multiplexing of SSN bus
• BFD-slow down frequency
and widen by factor of N
• BFM-speeds up the bus
frequency and narrow by
factor of N.
FAILURE MAPPING OF SSN PATTERN
FAILURES
• Required to reverse map step of all SSN pattern failures before
diagnosis(scan pattern retargeting,Top level ATPG)
• Source of pattern failures on SSH output are from EDT
outputs(behind active SSH,packet rotation around the SSN bus)
• No additional prerequisites to SSN failure mapping.
ON CHIP COMPARE

• Treat as non identical cores,

broadcast scan inputs,compact
scanout
• All cores contribute to accumulate
status by default (test setuo
procedure setting)
• Accumulated scan output
responses failures from failing core
A1.
OPTIMAL
ANALYSES ON
ON CHIP
COMPARE
• Examine the patterns from
STIL
• Identify the 0,1,Multiple
failing identical cores
• Treat thefailing cycles as a
regular fail data
• Execute the patched patterns
• Collect fail data
• Continue with other data
and fed to the diagnosis.
THANK YOU