Name: Hafiz M.

Hassaan EE-272L Digital Systems Design

Reg. No.:2021-EE-166 Marks Obtained: ____________

Lab Manual

DSD Lab Manual Evaluation Rubrics

Total Marks
Assessment 0-30% 30-60% 70-100%
Marks Obtained
Proper
No Proper Proper
Indentation and
Indentation and Indentation or
descriptive
descriptive descriptive
naming, code
naming, no code naming or code
Code organization.
Organization 3 organization. organization.
Complete
Zero to Some Mild to Complete
understanding,
understanding but understanding but
and proper
not working not working
working
Working
simulation with Working
Simulation not errors, don't simulation
done or incorrect, cares's(x) and without any
Simulation 5 without any high errors, etc and
understanding of impedance(z), complete
waveforms partial understanding of
understanding of waveforms
waveforms
Correctly Correctly
Not implemented
Implemented on Implemented on
on FPGA and
FPGA or FPGA and
questions related
FPGA 2 to synthesis and
questions related questions related
to synthesis and to synthesis and
implementation
implementation implementation
not answered.
answered. answered.
 Tasks

a) Truth table:

a b c x Y
0 0 0 1 1
0 0 1 0 1
0 1 0 0 0
0 1 1 1 0
1 0 0 0 0
1 0 1 1 0
1 1 0 0 1
1 1 1 1 1
b) Errors found in the codes (listing 4 and listing 5).
c) Corrected codes.

Listing 4: System Verilog Code

Listing 5: System Verilog Code