Index

Note: Page numbers followed by f indicate figures and t indicate tables.

A leakage currents, 19
AC symmetry test, 222–224, 223f , 224f Newton-Raphson iteration, 18
Analog compact model surface potential solution, 18
application, 16–17 threshold voltage, 19
gain-bandwidth product, 16–17 velocity saturation, 18–19
gain compression, 39–41, 40f , 41f signal-dependent charge injection, 17
geometric scaling speed, unity gain frequency, 31–32, 31f , 33f
DIBL, 21 thermal noise
performance optimization, 19–21 common-gate amplifier, 33–35
three-dimensional structures, 22–23 extrinsic noise sources, 35
threshold voltage vs. channel length, 21, 22f flicker noise, 35, 35f
Gummel symmetry test, 42–43, 42f , 43f intrinsic noise sources, 35
harmonic distortion spot noise variance vs. gate bias voltage,
drain-source voltage, 36 32–33, 34f
even harmonics, 37 variability modeling
Gm nonlinearity, 39 differential circuit, 23–24, 24f
input sinusoid, 36, 37, 38f doping and lithography, 24
loop gain, 36 physical parameters, 23
odd harmonics, 37 random variations, 23
power series, 39 systematic variations, 23
second harmonic vs. third harmonic signal, transistor performance, 23
37–39, 38f Asymptotic correctness, 216–217
terminal voltage, 36
transient/steady-state simulation, 39 B
weak distortion, 37 Band-to-band tunneling (BTBT) leakage current,
intermodulation distortion, 42 206–207
intrinsic gain Body effect model, 119–120
channel length, 24–25, 25f BSIM-CMG model
Coulomb scattering, 28 bird’s-eye view, 156–157, 157f , 158, 159f
device bias current, 25–26 channel current modeling
gate source vs. drain source voltage, 28, 29f body effect model, 119–120
optimum overdrive voltage, 26, 26f , 27f channel length modulation, 121–122
output conductance, 28–31 characteristic length model, 100–102
output resistance, 28–31, 30f DIBL effect, 104–105, 122–123
single-stage amplifier, 24–25 drain saturation voltage, 109–114
small-signal parameters, 25 drain-to-source current, 123
transconductance efficiency vs. gate source electrostatic potential profile, 102–104
voltage, 26, 27f geometrical confinement, (see Quantum
V ds function, 27–28, 28f mechanical effect)
memory effects, 41 lateral nonuniform doping, 119
mixed-signal design, 17 output resistance model, 120–123
quiescent operation point reverse short-channel effect, 105
absolute accuracy, 18 SS degradation, 106, 107f
convergence properties, 18 threshold voltage roll-off, 104
device current vs. absolute bias voltage, 19, 20f velocity saturation model, 114–118
device current vs. drain-source voltage, 19, 21f vertical field mobility degradation, 109
I-V curves, 17–18 cross-sectional diagram, 158, 159f

287
288 Index

BSIM-CMG model (Continued) channel doping concentration, 84, 84f

doped double-gate FET Cy-GAA FET, 81–83
Boltzmann distribution, 72, 73f drain current normalization, 83–84
drift-diffusion equation, 79 long-channel silicon-on-insulator, 85–87,
fin potential vs. fin position, 73–75, 86f , 87f
74f , 75f rounded trapezoidal shape, 80–81, 81f
Gauss’s law and boundary condition, trapezoidal TG FinFET, 84, 85, 85f , 86f
75–76
GCA condition, 72, 73f
mobile charge density, 76–77, 78f
C
Channel induced gate resistance model, 149–150,
parameter COREMOD, 77–79
149f
perturbation potential, 75–76
Channel length modulation (CLM), 121–122
Poisson’s equation, 72
Charge/capacitance model
saturation condition, 79–80, 80f
forward-bias model
subthreshold region, 79–80, 80f
BSIM-CMG, 212–213, 214
surface potential, 76–77, 77f (see also
junction capacitance, 211–212, 212f , 213
Newton-Raphson method)
junction charge, 211–212, 213
triode region, 79–80, 80f
PBS, 211–212
drain charge, 143–144
reverse-bias model
flicker noise
charge density, 209–210
carrier number fluctuation theory, 196
junction capacitance, 208, 209–211, 209f
definition, 196
junction depletion depth, 209–210
drain current, 196
Charge segmentation model
drain noise spectral density, 197–198
boundary conditions, 151
mobility fluctuation theory, 196
continuity equation, 150, 152
strong-inversion region, 198
gate terminal charge, 153
trap density fluctuation, 197
spline-collocation method, 150–151
unified model, 196
Ward-Dutton partitioning, 152
weak-inversion region, 198
CLM. See Channel length modulation (CLM)
gate charge, 142–143
gate electrode resistance model (see Parasitic Compact model
resistance) AC symmetry test, 222–224, 223f , 224f
gate-induced drain leakage, 130–131 analog metrics (see Analog compact model)
gate oxide tunneling, 132–133, asymptotic correctness, 216–217
132f Gummel symmetry test, 220–221, 220f , 221f
model parameters (see Parameter extraction) harmonic balance simulation test, 222, 222f , 223f
NQS model (see Non-quasi-static (NQS) effects) reciprocity test, capacitances, 225, 225f
parasitic capacitance (see Parasitic capacitance) RF metrics. (see RF compact model)
quasi-static assumption, 147 self-heating effect, 225–226, 226f
shot noise, 198–199 source-drain symmetry, 219–220
SOI, 157–158, 157f thermal noise, 226
source charge, 144 weak and strong inversion region
source/drain resistance conductance test, 218, 219f
components, 159, 160f slope ratio test, 217–218, 218f
contact resistance (Rcon ), 159, 160–161, 161f , volume inversion test, 219, 220f
162f Contact resistance (Rcon ), 159, 160–161, 161f , 162f
extension resistance (Rext ), 159, 165–167, Continuous starting function (CSF)
165f , 166f doping concentration, 89–90, 90f , 91f , 92f , 93f
spreading resistance (Rsp ), 159, 161–165, strong-inversion region, 88–89
162f , 164f subthreshold region, 88, 89–90
symbol definition, 157–158, 158t Core model. See BSIM-CMG model
thermal noise, 194, 195f CSF. See Continuous starting function (CSF)
unified compact model Cylindrical gate-all-around (Cy-GAA) FET, 81–83
 Index 289

D Gradual-channel approximation (GCA) condition,

Drain-induced barrier lowering (DIBL) 72, 73f
intrinsic gain, 27–28 Gummel symmetry test
off-state leakage current, 129, 130f drain-current model, 24f , 25f , 31–32
parameters, 237, 237t potential symmetry problem, detection, 42–43,
threshold voltage, 21, 22f , 104–105, 105f , 42f , 43f
122–123
Drain saturation voltage H
RDSMOD = 0, 111–114 Harmonic balance simulation test, 222,
RDSMOD = 1 and 2, 110–111 222f , 223f
Hybrid-pi model
E frequency dependence, 44–45
Extension resistance (Rext ) intrinsic transistor, 44, 44f
accumulation resistance (Racc ), 165–166 Mason’s unilateral gain U, 54–55, 55f
components, 166–167 maximum gain
definition, 165 capacitance neutralization, 53–54, 53f
doping profile, 165, 165f channel resistance, 51, 52f
resistance modeling, 165, 166f physical gate resistance, 51, 52f
spacer configurations, 165, 165f power gain, 51, 51f
quadrature phase relation, 49–50, 49f

F source and load admittance, 48–49

stability factor, 48–49, 50, 51f
Flicker noise
pi-circuit parameters, 45–46, 45f , 47f
carrier number fluctuation theory, 196
small-signal assumption, 44–45
definition, 196
tuned amplifier, 46–48, 48f
drain current, 196
Y parameters, 45–46, 45f
drain noise spectral density, 197–198
mobility fluctuation theory, 196
phase noise, 63–64, 63f I
standard compact model, 9–10 Impact ionization model
strong-inversion region, 198 intrinsic gain, 28f , 134
thermal noise, 35, 35f temperature dependence, 249
trap density fluctuation, 197 velocity saturation model, 138–139
unified model, 196 Induced gate noise, 194, 195f
weak-inversion region, 198 Inversion charge density, 142, 176

G J
Gate-induced drain leakage (GIDL), 9 Johnson–Nyquist noise. See Thermal noise model
BSIM-CMG model, 130–131 Junction diode
deep depletion, 128–129 current model
hole layers, 129 BSIM-CMG model, 204, 205f , 206, 207–208
narrow tunneling barrier, 129 BTBT-based current, 206–207
solid-source diffusion, 129 first-order Taylor expansion, 205, 206
Gate-induced source leakage (GISL), 128, 131 ideal junction current, 203
Gate oxide tunneling quadratic equation, 204
BSIM-CMG model, 132–133, 132f reverse-bias saturation current, 203–204
gate-to-body, 133–135, 133f , 134f SRH leakage current, 206, 207–208
gate-to-channel, 135–136, 136f TAT leakage current, 207–208
high-κ oxide interfaces, 131–132 junction capacitance (see Charge/capacitance
source/drain current, 136–137, 137f model)
Genetic algorithm, 230 planar bulk MOSFETs, 201–203
GIDL. See Gate-induced drain leakage (GIDL) p-type FinFET, 201–203, 202f
GISL. See Gate-induced source leakage (GISL) punch-through stop implant, 201–203, 202f
290 Index

L strong-inversion region, 88–89

Lateral nonuniform doping model, 119 subthreshold region, 88, 89–90
Leakage current modeling. See Off-state leakage quartic modified iteration
current explicit surface potential model, 91–95,
Levenberg-Marquardt algorithm, 230 95f , 96f
high-order correction, 91–95
Non-quasi-static (NQS) effects
M channel induced gate resistance model, 149–150,
Metal-oxide-semiconductor field-effect transistor
149f
(MOSFET)
charge segmentation model
charge segmentation, 150f
boundary conditions, 151
drain current, 196
continuity equation, 150, 152
lithography scaling
gate terminal charge, 153
germanium and group III-V materials, 5
spline-collocation method, 150–151
manufacturing cost, 5
Ward-Dutton partitioning, 152
shallow trench isolation oxide, 4, 5f
subthreshold swing, 5, 6f effective transconductance Gm vs. frequency,
thin body transistor, 4, 5f 56, 58f
power dissipation, 125 lumped circuits, 56–57, 58f
saturation region, 121, 121f , 122f RC time constant, 55–56
short-channel effects relaxation time approximation model, 147–149,
gate critical dimension variation, 2, 2f 148f
gate oxide thickness, reduction, 2–3, 2f , 3f Y11 component, 56, 57f
leakage paths, 3, 3f NQS effects. See Non-quasi-static (NQS) effects
random dopant fluctuation, 2, 2f
standard compact model O
accuracy, 9, 10f Off-state leakage current
BSIM-CMG, 8–9, 11–12 gate-induced drain leakage
CMOS technology, 9 BSIM-CMG model, 130–131
core model, 9 deep depletion, 128–129
flicker noise, 9–10
hole layer, formation, 129
germanium, 10, 11f
narrow tunneling barrier, 129
GIDL, 9
solid-source diffusion, 129
random telegraphic noise, 9–10
gate oxide tunneling
real device model, 9, 10, 10f
BSIM-CMG model, 132–133, 132f
SPICE simulation, 7–8, 8f
gate-to-body, 133–135, 133f , 134f
transfer characteristics, 10, 11f
gate-to-channel, 135–136, 136f
ultrathin body
advantages, 6 high-κ oxide interfaces, 131–132
channel doping, 4, 4f source/drain current, 136–137, 137f
leakage current, simulation, 6–7, 7f impact ionization model, 138–139
nanometers, 6–7, 6f weak-inversion current
random dopant fluctuation, 4, 4f electrostatic control, 128
temperature bias instability, 4 source-channel barrier, 127, 127f
tunneling leakage, 4 subthreshold swing, 126f , 127
two-dimensional semiconductors, 7
weak-inversion current, 127–128 P
Mobility degradation, 109 Parameter extraction
core model derivation, 229
N genetic algorithm, 230
Newton-Raphson method global parameters, 230
continuous starting function DIBL effect parameters, 237, 237t
doping concentration, 89–90, 90f , 91f , drain-current model parameters, 239
92f , 93f extraction flowchart, 231, 231t, 232f
 Index 291

interface charge, 235, 235t RF compact model

low-field-mobility, 235, 236, 236f , 236t intermodulation distortion
mobility parameters, 235, 235t second-order intermodulation, 64, 65, 66f
resistance scaling, 232, 232f spectral regrowth, 67–68
saturation I d - V g characteristics, 238, 239f third-order intermodulation, 64–65, 66f
subthreshold slope parameters, 234, 234f two-tone signal, 64
threshold voltage difference, 233, 233f Volterra series, 67
velocity saturation, 237, 238, 238t minimum achievable noise figure, 59, 60f
work function, 235, 235t noise voltage, 58–59, 58f
Levenberg-Marquardt algorithm, 230 NQS
local parameters, 230 effective transconductance Gm vs. frequency,
particle swarm optimization, 230 56, 58f
real-device effects, 229, 240f lumped circuits, 56–57, 58f
Parasitic capacitance RC time constant, 55–56
three-dimensional fringe capacitance, 185–186, Y11 component, 56, 57f
185f , 186f phase noise
two-dimensional fringe capacitance digital communication system, 62–63, 62f
contact-to-gate capacitance (Ccg ), 180f , 182, flicker noise, 63–64, 63f
183, 184 frequency domain, 61, 61f
fin-to-gate capacitance (Cfg ), 180, 180f , 181f local oscillator, 61–62, 62f
Parasitic resistance Lorentzian spectrum, 63
contact resistance model, 177 Pospiesalski noise model, 59–61
definition, 155 two-port parameters (see Hybrid-pi model)
device optimization, 168–170, 169f
extension resistance model, 176 S
gate electrode resistance model, 177 Selective epitaxial growth (SEG) process, 156–157
gate resistance, 156 Self-heating effects, 225–226, 226f
individual resistance components, 174, 175f Shockley-Reed-Hall (SRH) current, 206, 207–208
NQS, 177, 178f Short-channel effects (SCE)
physical parameters, 176 channel length modulation, 121–122
SEG process, 156 characteristic length model, 100–102
source/drain resistance DIBL effect, 104–105, 122–123
effective channel length, 171–172, 172f gate critical dimension variation, 2, 2f
extracted model parameters, 173, 174t gate oxide thickness, reduction, 2–3, 2f , 3f
gate voltage, 171–173, 172f , 173f geometrical confinement (see Quantum
potential issues, 170 mechanical effect)
spacer thickness, 173, 174f leakage paths, 3, 3f
total channel resistance, 170–171, 171f output resistance model, 120–123
vs. raised source/drain length, 174, 175f random dopant fluctuation, 2, 2f
spreading resistance model, 176 reverse short-channel effect, 105
TCAD simulation (see TCAD simulation) SS degradation, 106, 107f
threshold voltage roll-off, 104
Q velocity saturation model, 114–118
Quantum mechanical effect vertical field mobility degradation, 109
charge centroid, 115–116, 116f , 117f , 119 Shot noise, 198–199
effective oxide thickness/capacitance, 118 Silicon-on-insulator (SOI)
effective width model, 118 drain current vs. gate voltage, 85–87, 86f
threshold voltage, 107–108, 108f low thermal conductivity, 254
measured data validation, 255–258, 256f , 257f
R simulation, 6–7, 7f
Relaxation time approximation model, 147–149, source-to-drain direction, 157–158, 157f
148f SS model, 75f , 163
Reverse short-channel effect, 105 Slope ratio test, 217–218, 218f
292 Index

Spreading resistance (Rsp ) extrinsic noise sources, 35

cross-sectional area, 162 flicker noise, 35, 35f
resistance, 163 induced gate noise, 194, 195f
slope factor, 164f , 165 intrinsic noise sources, 35
source/drain region, 161–162, 162f noise spectral density, 194
test structure, 164–165, 164f parameter NTNOI, 194
Subthreshold slope (SS) degradation, saturation and linear region, 194, 195f
106, 107f spot noise variance vs. gate bias voltage, 32–33,
34f
T tests, 226
TCAD simulation Threshold voltage roll-off, 104, 105f
bird-eye view, 167, 168f Transcapacitance, 144–145, 145f , 146f
end-fin cases, 188, 189f Trap-assisted tunneling (TAT) leakage current,
fin-to-gate capacitance, 186–187, 187f 207–208
four-fin FinFET, 188, 189f
middle-fin cases, 188, 188f U
parameters, 167, 169t Ultrathin body (UTB) silicon
source/drain to gate capacitance, 186–187, advantages, 6
187f , 188f channel doping, 4, 4f
Temperature dependence leakage current, simulation, 6–7, 7f
leakage current nanometers, 6–7, 6f
gate current, 248 random dopant fluctuation, 4, 4f
gate-induced drain/source leakage, 249 temperature bias instability, 4
impact ionization, 249 tunneling leakage, 4
measured data validation, 255–258, 256f , 257f two-dimensional semiconductors, 7
mobility, 247 Unified compact model
nonsaturation effect, 248 channel doping concentration, 84, 84f
parasitic source/drain resistances, 249–250 Cy-GAA FET, 81–83
saturation velocity, 247–248 drain current normalization, 83–84
self-heating effect, 254–255, 254f , 255f long-channel silicon-on-insulator, 85–87,
semiconductor properties 86f , 87f
band gap, 244 rounded trapezoidal shape, 80–81, 81f
density of states, 245 trapezoidal TG FinFET, 84, 85,
intrinsic carrier concentration, 245 85f , 86f
source-drain built-in potential, 245
source/drain diode characteristics
direct current model, 250–252 V
junction capacitances, 252 Velocity saturation model
trap-assisted tunneling saturation current, channel current modeling, 114–118
252–254 impact ionization model, 138–139
threshold voltage temperature dependence, 247–248
body effect, 246 Volume inversion test, 219, 220f
drain induced barrier lowering, 246
subthreshold swing, 246–247 W
validation range, 255 Ward-Dutton partitioning, 143–144, 145,
Thermal noise model 146f , 152
charge-based model, 194 Wentzel-Kramers-Brillouin (WKB) approximation,
common-gate amplifier, 33–35 130