Sequential Design

& Re-usable
components in
VHDL Pt-II
ENEL373: Lecture 7
Steve Weddell & Ciaran Moore

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 Clock Sources
• All sequential logic
designs require a clock
source.
• For most applications
want fclk ≥ 100 MHz, which
is typically divided down.
• Generally, power
https://www.pexels.com/photo/
consumption ∝ fclk wall-clock-at-5-50-707582/

Ciaran Moore
5/03/23 2
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 Clock Sources
• There are two common clock sources on an
FPGA:
System Clock:
• Supplied by an oscillator external to the FPGA.
• Connected as clk100mhz on pin E3 of the
Nexys-4 DDR dev. kits.
• See §6 of the Nexys-4 DDR Reference Manual
and the Nexys-4 DDR constraints file.
Ciaran Moore
5/03/23 3
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 Clock Sources
• Clock sources in VHDL are usually
std_logic type, but they are routed
through special (high current) buffers in
the FPGA.

• Why???

Ciaran Moore
5/03/23 4
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 Clock Skew
clk
i
(many) dV
!
C logic i=C
buffer gates
1
dt

clk amplitude
(normalised)
0.5
• Limited i leads
to finite dV/dt.
0
0 0.5 1
time (clk period)
Ciaran Moore
5/03/23 5
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 Counters
architecture C12_Arch of counter_12 is
signal count : integer range 0 to 12;
• Counter: begin
entity counter_12 is process (RESET, CLK) is
port( CLK, RESET : in std_logic; begin
CO : out std_logic); if RESET = '1' then -- asynch reset
end counter_12; count <= 0; -- note, no single quotes!
elsif (CLK'event and CLK = '1') then
if (count = 12) then

• How does

count <= 0; -- reset counter
else
count <= count + 1; -- increment counter
Vivado 'know' end if;
end if;

what + means? end process;

CO <= '1' when (count = 12) else '0';
end C12_Arch;

library IEEE;
use IEEE.std_logic_1164.all; -- for std_logic values (there are 9).
use IEEE.std_logic_signed.all; -- for math functions on signed.

Note the correction from

Lecture 6!!
Steve Weddell
Ciaran Moore
5/03/23 6
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 library IEEE;

Clock
use IEEE.std_logic_1164.all; -- for std_logic values (there are 9).
use IEEE.std_logic_signed.all; -- for math functions on signed.

entity clk_divider is

Divider
Port (
m_clock : in std_logic; -- single bit input
c_clock : out std_logic); -- single bit output
end clk_divider;

Example architecture MY_CLOCK of clk_divider is

constant clk_limit : std_logic_vector(27 downto 0) :=
X”17D783F"; -- 24,999,999 in decimal

signal clk_ctr : std_logic_vector(27 downto 0);
signal temp_clk : std_logic;

begin
clock: process (m_clock)
begin
if m_clock = '1' and m_clock'Event then
if clk_ctr = clk_limit then -- if counter =
-- (1Hz count)/2
temp_clk <= not temp_clk; -- toggle clock
clk_ctr <= X"0000000"; -- reset counter
else
clk_ctr <= clk_ctr + X"0000001";
end if;
end if;
end process clock;
c_clock <= temp_clk; -- continuously update clock output
Steve Weddell Ciaran
Moore -- since this is a concurrent statement
5/03/23 end MY_CLOCK; 7
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 Shift Registers
entity shift_reg_4 is • Shifts contents of "shifty"
port( CLK, RESET, SI : in std_logic;
Q : out std_logic_vector(3 downto 0); left by 1 bit.
SO : out std_logic);
end shift_reg_4; • Value of "SI" is loaded
architecture SR4_Arch of shift_reg_4 is
into the right MSB.

signal shifty : std_logic_vector(3 downto 0); • n-bit parallel load

registers with
begin
process (RESET, CLK) is synchronous enables are
begin useful to hold operands
if RESET = ‘1’ then -- asynch reset, active hi
shifty <= “0000”; when loading data into
elsif (CLK’event and CLK = ‘1’) then an ALU.
shifty <= shifty(2 downto 0) & SI; -- shift left
end if;
end process;
• Note: '&' concatenates
Q <= shifty; vectors.
SO <= shifty(3);
end SR4_Arch; • Can you draw an RTL
schematic of this code?

Ciaran Moore
5/03/23 8
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 Tristate Signals
entity tri_buf_4 is

port ( clk, enable, reset : in bit;
• If using
d : in std_logic_vector (3 downto 0); IEEE_STD_LOGIC_116
q : out std_logic_vector (3 downto 0));

end entity tri_buf_4; 4 it is possible to
architecture Arch_Tbuf4 of tri_buf_4 is

assign other signal
begin conditions to ports or
t_buf : process (clk, enable, reset) is

begin
 signals.
if enable = ‘0’ then
q <= ‘ZZZZ’; • A timing constraint
elsif reset = ‘1’ then
q <= “0000”; will only be evaluated
elsif clk’event and clk = ‘1’ then

q <= d after 2 ns;

after the Place and
end if;
 Route process as part
end process t_buf;
end Arch_Tbuf_4; of the static timing
requirements.

Ciaran Moore
5/03/23 9
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 Sequential &
Concurrent Operations
entity EXAMPLE is
port( SIGY, SCLK, RD : in std_logic;
SIGZ : out std_logic);
end entity EXAMPLE;

architecture SEQUENTIAL of EXAMPLE is architecture CONCURRENT of EXAMPLE is

signal SIGX : std_logic; signal SIGW : std_logic;
begin begin
ff_behav: process (SCLK) is
begin
if (SCLK = '1' and SCLK'event) then
SIGX <= SIGY; SIGZ <= SIGW when RD = '1' else '0';
SIGZ <= SIGX; SIGW <= SIGY when RD = '1' else '0';
end if;
end process ff_behav;
end SEQUENTIAL; end CONCURRENT;

• Can you sketch the synthesised circuits that these architectures will produce?

Ciaran Moore
5/03/23 10
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 Switching data buses to re-use
(multiplexed) components
through Multiplexers

Steve Weddell
Ciaran Moore
5/03/23 11
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 Exercise
architecture mux41 of mux is Using structural VHDL and the code
begin below, expand this implementation to
process (A, B, C, D, Sel) allow four 4-bit data busses A(3 down 0)
begin etc, to be switched using Sel inputs.
-- your sequential construct code goes here
if Sel = "00" then
X <= A;
elsif Sel = "01" then architecture mux41 of mux is
X <= B; begin
elsif Sel = "10" then process (A, B, C, D, Sel) -- case construct:
X <= C; begin
else -- Sel = "11": -- your sequential construct code goes here
X <= D; case Sel is
end if; when "00" => X <= A;
end process; when "01" => X <= B;
end mux41; when "10" => X <= C;
when "11" => X <= D;
end case; Note: A 2-to-1, 4-bit data version of this Mux
end process; can be used to complete your Milestone by
end mux41; switching two counter results, i.e., “units”
and “tens” (BCD data) through to your
existing, single, seven-segment decoder.
Steve Weddell
Ciaran Moore
5/03/23 12
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 VHDL Templates
Coding e am le fo n he i , ch a Fli Flo :

• Vivado provides
considerable help
with VHDL syntax
via its Language
Templates.
• Tools > Language
Templates.
• See PDF on Learn:
Section 1/Lab
Handouts &
Resources/
Language
Templates in
Vivado.

Ciaran Moore
5/03/23 13
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 Summary
• Despite their inherent concurrency, FPGAs
work best with a clock.
• Attributes extend the range of possibilities
in VHDL.
• We are starting to see lots of different VHDL
examples – too many to recall perfectly
every time. Use Vivado's Language
Templates to jog your memory!

Ciaran Moore
5/03/23 14
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 References
• Mano & Kime, Logic and Computer
Design Fundamentals, 3rd Ed., Prentice
Hall, 2003
• Yalamanchili, VHDL Starter’s Guide,
Prentice Hall Inc., 1998
• Wakerly, Digital Design & Practices, 3rd
Ed., Pearson, 2000
Ciaran Moore
5/03/23 15
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 Homework
• This is the same as shown in your
Lecture 6 lecture notes.
• Some of these examples will be selected
for review in your remaining tutorial
sessions.

Ciaran Moore
5/03/23 16
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