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I2C Pull-Up Resistor Choose Guideline - v1.0

The document provides guidelines for choosing an I2C pull-up resistor and discusses I2C timing requirements. It states that the pull-up resistor should be between Rmin and Rmax and all I2C timing specifications must be met under different temperature conditions. Equations are given for calculating the minimum and maximum pull-up resistor values based on bus capacitance and voltage levels. Tables list the I2C timing parameters that must be met at various temperatures, such as rise and fall times for the SDA and SCL signals. Diagrams illustrate the signal timing definitions and an I2C bus timing sequence.

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Khưu Minh Tấn
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65 views7 pages

I2C Pull-Up Resistor Choose Guideline - v1.0

The document provides guidelines for choosing an I2C pull-up resistor and discusses I2C timing requirements. It states that the pull-up resistor should be between Rmin and Rmax and all I2C timing specifications must be met under different temperature conditions. Equations are given for calculating the minimum and maximum pull-up resistor values based on bus capacitance and voltage levels. Tables list the I2C timing parameters that must be met at various temperatures, such as rise and fall times for the SDA and SCL signals. Diagrams illustrate the signal timing definitions and an I2C bus timing sequence.

Uploaded by

Khưu Minh Tấn
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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I2C Pull-up Resistor Choose

guideline

Semiconductor GC-CAL
• Pull-up resistor chosen should be between Rmin and Rmax
(refer to slide 3);
• All I2C timing should be meet I2C spec requirement under
such different temperature condition like -45°C, + 25°C and
+85°C (refer to slide 4);

CONFIDENTIAL Semiconduc tors GC-CAL 2


Pull-up Resistor calculation

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CONFIDENTIAL Semiconduc tors GC-CAL 3
IIC Timing Requirement:
TIME -45°C /+ 25°C/ +85°C Limits

FSCLH SCLH clock frequency 0<FSCLH<400kHz

tHD;STA Hold time (repeated), START condition > 0.6 s

tLOW Low period of the SCLH clock > 1.3 s

tHIGH High period of the SCLH clock > 0.6 s

tSU:DAT Data set-up time > 100ns

tHD:DAT Data hold time 300ns < tHD:DAT < 900 ns

tRCL Rise time of SCLH signal (20+0.1C) ns < tRCL< 300ns

tFCL Fall time of SCLH signal (20+0.1C) ns < tFCL < 300ns

tRDA Rise time of SDAH signal (20+0.1C) ns < tRDA< 300ns

tFDA Fall time of SDAH signal (20+0.1C) ns < tFDA< 300ns

tSU:STO Set-up time for stop condition > 600 ns

Remark:
C: capacitive load on SDA and SCL, max 400pf;

CONFIDENTIAL Semiconduc tors GC-CAL 4


Trise Definition

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CONFIDENTIAL Semiconduc tors GC-CAL 5


Timing diagram of IIC-bus

CONFIDENTIAL Semiconduc tors GC-CAL 6


CONFIDENTIAL Semiconduc tors GC-CAL 7

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