SCIENCE CHINA

Technological Sciences
• RESEARCH PAPER • May 2010 Vol.53 No.5: 1208–1214
doi: 10.1007/s11431-010-0129-x

A 12-bit multichannel ADC for pixel detectors in particle

physics and nuclear imaging
WEI Wei1,2,3, WANG Zheng1,3 & ZHAO JingWei1,3*
1
Institute of High Energy Physics, Chinese Academy of Sciences, Beijing 100049, China;
2
Graduate University of Chinese Academy of Sciences, Beijing 100049, China;
3
Key Lab of Nuclear Detection Technology and Nuclear Electronics of Chinese Academy of Sciences, Beijing 100049, China

Received September 14, 2009; accepted February 9, 2010; published online April 15, 2010

Modern pixel detectors in nuclear and particle physics experiments and also in nuclear imaging, starve for highly integrated
application specified integrated circuit (ASIC), whereas in China the study of ASIC still stays far away from practical applica-
tion. The lack of ASIC strictly limits the research and development of domestic high energy physics field. A 12-bit multichan-
nel ADC designed for high density readout is introduced as a major candidate for solution. A precise model is discussed and
the simulation fully agrees with the model, which indicates a key principle of design. Design is performed according to the
given rule, and novel layout techniques are carried out. Measurement results in all aspects are also obtained, showing an excel-
lent real performance, which satisfies the practical requirement.

application specified integrated circuit, high density readout, Wilkinson ADC, multi-channel ADC

Citation: Wei W, Wang Z, Zhao J W. A 12-bit multichannel ADC for pixel detectors in particle physics and nuclear imaging. Sci China Tech Sci, 2010, 53:
12081214, doi: 10.1007/s11431-010-0129-x

1 Introduction strictly limits the research and development of domestic

high energy physics field. As in Beijing Spectrometer
Recently, modern pixel detectors in nuclear and particle (BESIII), all the readout electronics were designed by using
physics experiments and also in nuclear imaging, require discrete components. However, if all are realized in ASIC,
enormous electronics channels to obtain enough precision. the total size and cost would be reduced by as much as 25
Application specified integrated circuit (ASIC) makes this percent. This work concentrates on a 12-bit parallel multi-
task possible. It integrates multichannel electronics from channel ADC as the major candidate for high density
front end to back end into a single silicon die smaller than readout. The analysis, modeling, and design details are de-
10 mm2, saving room, power, and cables compared with scribed. Measurement results are also presented in this pa-
traditional discrete electronics, not to mention the large per.
quantity of budget. Without ASIC, novel nuclear detectors The describing chip in this paper is originally designed for
can never be designed because of the growing number of gas electron multiplier [1], which will be used as the key part
channels and limited room, even with no care about budget. for the real-time beam monitoring of Beijing synchrotron ra-
Unfortunately, the study of ASIC in Chinese high energy diation facility [2] and possible future upgrade for nuclear
physics field is just budding whereas the application over- imaging. The real-time imaging requires high position resolu-
seas started more than 20 years ago. The lack of ASIC tion, so pad readout collector instead of strip is more favorable
to further shrink the sensing cell and to eliminate the multi-hit
*Corresponding author (email: [email protected]) effect. As a result, the number of total channels will increase

© Science China Press and Springer-Verlag Berlin Heidelberg 2010 tech.scichina.com www.springerlink.com
 WEI Wei, et al. Sci China Tech Sci May (2010) Vol.53 No.5 1209

at an exponential speed rather than linear, some can even detectors and back end is the analog-to-digital conversion.
reach several ten thousands [3], calling badly for high density Compared with analog, digital transmission is lower in
readout. Due to the non-negligible size, traditional discrete power consuming and less prone to couple noise caused by
electronics can hardly compete for the task. Methods have electromagnetic interference (EMI) and ground disturbance.
been tried in every way to apply discrete components to the Additionally, with a memory and serial interface, as few as
PCB readout array as a temporary substitute of ASIC, includ- three wires can successively transfer data up to Mega bits.
ing directly connected fly wires [2], delay-line readout [4], Thanks to ADC, real-time analog signal can be processed in
multilayer PCB connection with high density socket [5], and time and restored in RAM, thus rewards the advantage of
so on. However, all the prototype experiments expect high digital transmission.
density readout ASICs for future upgrade as in ref. [3]. With Further discussion for GEM and many other pixel detec-
ASIC, a chip in tiny size, embedded with preamplifier, shaper, tors is that, due to the high density collecting pads, room on
peak holder, and even ADC, can be directly bonded to the collecting PCB is so limited that commercial ADCs can
backside of PCB readout array, shrink the interconnecting hardly make room for existence, not to mention that the
length and hence decrease noise and crosstalk. Dozens or up channels of those ADCs are always far from enough. The
to several hundreds of detector channels can be dealt with idea of the introduced ADC came out from the well-known
altogether, but read out through fewer than ten connecting Wilkinson ADC, which can convert all channels at one time
wires, thus effectively enhance the performance and accuracy, but stays small in size, thus dense integration is possible.
and save budget and space. The dotted frame in Figure 1 is the block schematics of
the parallel multichannel ADC, showing the interface be-
tween detector end and digital output. Outputs of preampli-
2 Analysis of structure fiers and shapers feed into ADC. Desired amplitude of
shaper output is then held by a peak holder or sampler. Af-
One critical problem to limit the interconnection between ter peak detecting, the held voltage is sent to the negative

Figure 1 Block schematics of multichannel readout.

1210 WEI Wei, et al. Sci China Tech Sci May (2010) Vol.53 No.5

input of a comparator, which is one per channel. A common Table 1, the large area cost strictly prevents the integration
ramp wave is then ready to start from baseline and sent to with front end in a single chip. Besides, concerning detector
all the positive inputs of comparators. In the meantime, a channels M as many as 128 or even more [7], the mono-
counter also starts to count for the time duration and its ADC will consequently turn the same time every round. As
counting value feeds to all the individual latches. All the a result, the single-run time will increase to MT as a consid-
held amplitude will be compared with the up growing ramp erable amount, whereas the conversion time of the Wil-
voltage. When the running ramp exceeds the held level of a kinson’s scheme always remains the same with no impact of
peak holder, the corresponding comparator will fire and channels. In this case, the mono-ADC actually takes no su-
trigger the latch, which registers the time stamp and be- periority of speed over Wilkinson’s, or even worse if con-
comes the converted value of the held voltage. The ramp cerning about the resolution and complexity. That is why
will keep growing until the conversion of all channels is Wilkinson ADC is the most popular scheme or even the
completed. Finally, the ramp will be reset and wait for the only choice for integrated multichannel A/D conversion,
next event. In this first prototype, only single channel ver- despite that there is rare use in discrete implements.
sion of sample-and-hold module is designed, so that major Thanks to Switched-Capacitor Array (SCA) [8] or say
concern can be focused on ADC, which is the key part for Analog Memory, fast pulse shape can be sampled with ultra
final performance. high frequency and then buffered in this memory. ADC will
Assume the held amplitude is Ai and the slope of ramp is then do the conversion with no time limit and hence become
S = V0/t0, in which V0 and t0 refer to the full-scale and its deadtimeless. With SCA, Wilkinson ADC can even work
conversion time respectively, the crossing-threshold time t for the ultra fast wave digitizer with sampling speed up to
of this channel will be t = Ai/S. Suppose T is the period of giga hertz [8]. As shown in refs. [7–9], Wilkinson ADC has
clock, the digital output will be t/T = Ait0/(V0T). been widely used in various ASICs, making it an ideal start
According to this working flow, total conversion time of for ASIC study. As mentioned above, in order not to in-
this ADC in a single event is proportional to the maximum crease the complexity, SCA is not included in this first pro-
of the held peak, since the ramp is linear. In the worst case, totype but is ready to be included in the next generation.
this will be 2NT whereas in most other types of ADC, the
value is always fixed to one T or several Ts, showing its
inherent disadvantage of speed. On the other hand, as will 3 Modeling and simulation
be discussed later, the final resolution almost depends only
on the linearity of the ramp generator, which makes it easy Since the principle of comparator and gray counter is quite
to achieve an excellent resolution as good as 12 bits. How- straight and classical [10], only the ramp generator will be
ever, for other types of ADC, much greater efforts must be discussed below. Figure 2 shows a more detailed model of
made even with the target of 10 bits. What is more, the in- that, where two reset switches are omitted.
tegration characteristic of ramp offers a natural low-pass To be analyzed in frequency domain, all the stimulant
filter against noise, which is welcome in high energy phys- and response are described by using Laplace Transform.
ics. Finally, the smallest size among commonly used ADCs, Both the current source and the amplifier are modeled with
such as Flash ADC, Pipeline ADC, and Successive Ap- non-ideal effect, including dominant pole and internal re-
proximation ADC (SARADC), gives another crucial priori- sistance shown as Rds, Rin, and Ro. As working in a pulse-
ty to Wilkinson ADC in multichannel application. Table 1 reset way, the input source is modeled as a step to be I(s) =
gives an evaluation of those frequently used ADCs in high Ic/s. According to the figure, the amplifier is described with
energy physics. Some performance is summarized from the its dominant pole in transfer function: As = A0/(1+s/p0).
specification of commercial ADCs [6]. Therefore, the output response is obtained by using Ohm’s
Being widely used in discrete electronics, another com- Law, where no feedback assumption such as virtual ground
petitive scheme for multichannel A/D conversion may be a is made. In this way, the impact caused by the amplifier’s
fast ADC combined with an analog multiplexer. Although finite gain can also be taken into account.
this scheme seems much more time-effective according to

Table 1 Evaluation of different types of ADC

Type Wilkinson SAR Pipeline Flash
Common resolution 12 bits 10 bits 10 bits 8 bits
Linearity excellent good med poor
Speed poor med med/fast fastest
Power ultra low low/med med/high very high
Core area very small large med/large ultra large
Complexity easy complex complex easy Figure 2 Detailed model of the ramp generator.
 WEI Wei, et al. Sci China Tech Sci May (2010) Vol.53 No.5 1211

I A ( R || Rin )  sCRo ( Rds || Rin )

Vout   s ds . (1)
s 1  (1  As )s( Rds || Rin )C  sCRo

If the output resistance Ro is omitted, which is the general

case, eq. (1) can be simplified as
I As ( Rds || Rin )
Vout   , (2)
s 1  (1  As )sC ( Rds || Rin )

then two poles can be found, which are:

ps0 = 1/(1+A0)RdsC and ps1= (1+ A0)p0.
Suppose two poles are far from each other, which means:
ps1  ps 0  p0  A02  1 / ( Rds || Rin )C , (3) Figure 3 Maximum linear error vs. 3 dB bandwidth.

and input resistance is much larger than output's, the output

response can be simplified as
I A0 Rds IA R 1
Vout    0 ds  , (4)
s 1  (1  A0 )sCRds s 1  sRI C

where RI refers to (1+A0)( Rds || Rin).

Since both of those assumptions are easily satisfied, eq. (4)
suggests the general model of ramp generator that, although
much more complex, it eventually equals to an RC integrator,
and the passive time constant is deeply amplified by a factor
of A0.
Thanks to Matlab [11], a more accurate simulation is
performed with no simplification from eq. (1). To obtain a
normalized output response in time domain, the formula is Figure 4 Valid zone for A0 and bandwidth.
first inverse-Laplace transformed and then normalized
within an indicated integration time. The normalized re-
Further discussion can be made from the simulation.
sponse is then subtracted by an ideal normalized ramp wave
According to the requirement of resolution, both INL and
to calculate the linear error. With a peak-searching algo-
DNL need to be less than 0.5 LSB, where an LSB = 1/2N.
rithm, the range of the error can be obtained. According to
Since 12 bits are required, the maximum error should be
the classical definition [10], this gives the INL of ADC,
less than 1/213 = 1.22×104. Under this constraint, a curve
supposing other components are ideal.
can be obtained from Figure 3 formed by all the cross points
In most cases, all the passive components including Rds,
between the series and y = 1.22×104, in other words, min-
Rin, and C, are somewhat non-variable or preset according
imum bandwidth can be found with the corresponding gain.
to the specification. For example, in order that the output
Figure 4 shows the results. From that, a prediction before
ramp wave is within the dynamic range of the amplifier, the
designing the amplifier can be made so that the final resolu-
integrating capacitor is chosen in advance with the integrat-
tion can fulfill the requirement. Some tradeoff can also be
ing current. According to this experience, only the DC gain
made according to Figure 4 between speed and accuracy.
and the dominant pole of the amplifier were chosen as vari-
However, due to the parasitic capacitance introduced by
ables in simulation, others were set as constants with rea-
layout and package, bandwidth can never be precisely sim-
sonable value from experience and CMOS process.
ulated, but a general prediction is always helpful to reduce
Figure 3 shows the series of maximum errors with dif-
the tape out risk.
ferent gains and poles (shown as 3 dB bandwidth), which
From eq. (4), an estimate can also be made by hand fol-
are obtained from the normalized output wave transformed
lowing the same procedure. From inverse-Laplace trans-
from eq. (1).
form, eq. (4) refers to an exponential-rising step, from
It can be clearly seen that with the amplifier’s DC gain
which the normalized error can be obtained as
fixed, INL decreases with higher poles, in other words,
larger bandwidth. However, when the pole goes beyond an 1  e (  t / RIC )
ultra high frequency, there will be hardly any influence. On error(t )  t /T . (5)
1  e (  T / RIC )
the other hand, with higher gain, linearity of the output
ramp can always be improved by an observable value. It is common that Tintegrate<< RI C = A0 RdsC in normal
1212 WEI Wei, et al. Sci China Tech Sci May (2010) Vol.53 No.5

case, therefore eq. (5) can be further simplified by second Figure 5 is the layout of the ASIC, including a ramp
order approximation as shown in eq. (6): generator, a comparator, a track-holder, a gray counter, and
a voltage reference (bandgap). Additional components are
error(t )  (2 RI Ct  t 2 ) / (2 RI CT  T 2 )  t / T . (6) also inside the chip, including a core prober, power-on setup,
Then it is easy to calculate the maximum value. The re- and ESD protection together with bonding pads. The chip
sult shows, exactly at t = 0.5T, the error goes to its maxi- was designed on Chartered 0.35 µm CMOS 2P4M process,
mum value, which is and the area was 1.8 mm×1.1 mm. Since 12 bits are often
more than enough for many experiments, optional resolu-
INL  T / (8RI C  4T )  T / (8 A0 RdsC  4T ) . (7) tion was designed in order to decrease the conversion time.
Adapted for three resolutions of 12-bit, 10-bit, and 8-bit
Eq. (7) shows perfect meet with the simulation, from modes, the slew rate of ramp should also change corre-
which larger A0 always decreases INL. Precondition (3) spondingly to fully utilize the dynamic range.
should also be emphasized. When it cannot satisfy eq. (3), The current source was designed by using a voltage ref-
dominant pole also affects INL. However, after it goes to a erence and a voltage-to-current transformer. Off-chip ze-
high frequency, complex response from eq. (1) degenerates ro-temperature coefficient resistor is required, so that the
to eq. (4) with no influence from bandwidth. Furthermore, zero coefficient achieved by the bandgap reference will not
to satisfy INL < 1.22×104, lower limit of A0 can be deter- lose over internal resistors or MOSFET.
mined by eq. (6), where for an integration time of 81.92 μs Comparator is also carefully designed. Since it should
(12 bits, 50 MHz clock frequency, which is the most typical settle down within one clock period, the comparator actual-
case), the gain should always be larger than 1678. Again, ly requires large bandwidth although the overall ADC
the curve “A0 = 1000” in Figure 3 falls out of the range and seems rather slow. Large gain is also needed for 12-bit res-
shows agreement with the deduction. For longer integration olution. Finally, critical tradeoffs have been made among
time, larger gain is necessary to ensure the accuracy. How- the gain, the speed, and the power consumption.
ever, in fast ramp application such as Time-to-Digital Con- The gray counter is designed as a pure gray scheme
vertor’s ramp as short as 100 ns, bandwidth is more im- without common binary-to-gray decoder. In this way, big
portant than gain. glitch noise generated by simultaneous binary switching
will be eliminated and the internal environment will be
much more quiet.
4 ASIC design and layout The layout is a full mixed-signal task. The floorplan is
well arranged to keep the noisy counter far away from the
An ASIC is designed according to the model and the simu- sensitive analog core. Dual guard rings are also adequately
lation result. General presentation is given in this paper. placed around every module, so as to block the noise charge

Figure 5 Layout of the ASIC prototype.

 WEI Wei, et al. Sci China Tech Sci May (2010) Vol.53 No.5 1213

and reduce the latch-up risk. To further isolate the noise, ing Matlab. Three major measurements were carried out
independent power supplies are planned for different mod- concerning the interest of high energy physics, which are
ules but expected to be connected together on PCB. Besides noise, INL, and DNL measurements. For reference, a con-
those common methods, substrate separating is also used as trol experiment was also performed by an 18-bit ADC
an overall consideration to all the NMOS. The idea is to (AD7678) with good linearity.
introduce an independent power net to the substrate connec- Figure 7 shows a noise measurement result. The input
tion of NMOS, rather than connect it with source end in the was set to a DC level at about mid-scale and over 10000
common way. Although not fully isolated, this method pro- counts were taken. Statistic gives a standard deviation of
vides a shortcut to ground for noise charge, so that substrate 0.78 LSB and a count range of 5 LSBs, where 56.6×0.78
coupling from digital part is suppressed since signal path is agrees for the 99.7% possibility of Gaussian distribution. As
different. will be shown later, with a dynamic range of over 1.4 V, the
root-mean-square (RMS) noise equals to 268 μV.
Linearity measurement was performed by a ramp step
5 Measurement input generated by the 16-bit DAC. In order to minimize the
influence from noise and DNL, repeated conversions were
The measurement environment is based on ALTERA DE2 performed while the DAC output stayed static. Figure 8
development board, where a Cyclone II 2C35 FPGA is in- shows both the linearity and dynamic range.
cluded. A daughter board is also designed with the ADC In Figure 8, the DAC ramp value has already been trans-
under test and a source DAC. lated into voltage, showing a dynamic range from 1.2 V to
Figure 6 shows the block schematics of the test bench. 2.6 V. By least square fitting, the error between ADC
The chip communicates with the FPGA by an 80-pin pro- counts and the best-fit line was calculated. The residual
grammable IO socket and a flat cable. An 18-bit DAC shows an INL less than ±1 LSB (0.024%). Compared with
(DAC8831) and a waveform generator (Agilent 33250A) some reported measurement results [7, 9, 12], this chip
were used to generate the input waveform. Thanks to a Nios achieved a comparable performance of linearity.
II embedded processor in Cyclone II, DAQ interface to a DNL measurement was also performed by using sine-
PC was accomplished without heavy code. Data were first histogram method. The result in Figure 9 shows a typical
read and buffered in a large SDRAM, and then piped out to DNL of ±0.5 LSB.
PC via USB port at a lower speed. Finally, raw data were All the major measurement results are summarized in
post-processed by decoding algorithm programmed by us- Table 2. Two additional resolutions are included. Other tests

Figure 6 Block schematics of the test bench.

1214 WEI Wei, et al. Sci China Tech Sci May (2010) Vol.53 No.5

such as dynamic performance tests with FFT are also car-

ried out, however, only the major concerned performance in
high energy physics is listed. All the results show a reliable
performance of fine linearity. However, the RMS noise of
12-bit mode is relatively larger than common one. The
problem is speculated that the socket of development board
and non-LVDS clock cause a big jitter, thus the aperture
error exceeds the limit and induces an increased noise [10].
With a near-end FPGA and a Phase-Lock Loop, a better
clock can be obtained and thus expected to solve the prob-
lem.

Figure 7 Measured RMS noise for 12-bit resolution. 6 Conclusions

All the measurements show a satisfaction of the require-

ments. As a core for high density readout, this chip is a
good start and ready for the rest parts such as preamplifier
and shaper to be added on. With those convincing results,
the chip is successfully designed as a major candidate for
high density readout for nuclear imaging and pixel detectors,
and also an important milestone in domestic ASIC study in
high energy physics field. Succeeding development is about
to start, and SCA will be embedded and expected to bring
an extraordinary improvement in timing performance.

This work was supported by the National Natural Science Foundation of

China (Grant No. 10735060).

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