DAKSH MEHRA

VHDL
The Abstract:
In this paper, an attempt has been made to review the design of Direct Memory Access (DMA)
Controller using VHDL. Direct Memory Access is a method of transferring data between
peripherals and memory without using the CPU. The 8237A Multimode DMA Controller is a
peripheral interface circuit for microprocessor systems. It is designed to improve system
performance by allowing external devices to directly transfer information from the system
memory. Memory-to memory transfer capability is also provided. The 8237A offers a wide
variety of programmable control features to enhance data throughput and system optimization
and to allow dynamic reconfiguration under program control.

I.INTRODUCTION
Many system-on-chip (SoC) integrated circuits contain embedded cores with different scan
frequencies. To better meet the test requirements for such heterogeneous SoCs, leading tester
companies have recently introduced port-scalable testers, and Many IP core design software
like Xilinx, Leonardo Spectrum, and Modelsim etc. which can used to design IP core like DMA
,Interrupt Controller etc. These IP core can be Power aware an Implement on SoC by choosing
different design technique and various modeling techniques .These all modeling technique and
tolls like Xilinx ISE also provide RTL view which will help to make IP cores to use in any
Processor design .Here in these project we will see an Intel 8237 DMA IP core design which is
using a very different kind of design technique not used up till now. So by this project we will
prove that if we are trying & use various modeling techniques for designing IP cores than it may
be used in various power level requirement circuits & processors & it may also power aware.
These IP cores are ASIC application specific IC so we can control its power, speed, size etc. to
implement before on an embedded circuit. So an IP core design is a part of a Main embedded
circuit and control the working of that circuit or processor.
Today’s SoCs are composed of a wide variety of modules, such as microprocessor cores,
memories, peripherals, and customized blocks directly related to the targeted application. To
effectively perform simulation-based design verification of peripheral cores, it is necessary to
stimulate the description in a broad range of behavior possibilities, checking the produced
results. Different strategies for generating suitable stimuli have been proposed by the research
community to functionally verify these modules and their interconnection when embedded in a
SoC: however, their verification often remains a largely manual and unstructured operation. In
this paper we describe a general approach to develop concise and effective sets of inputs by
modeling the configuration modes of a peripheral with a graph, and creating paths able to cover
all of its nodes: proper stimuli for the device are then directly derived from the paths. The
resulting inputs sequences are aimed at design verification of system peripherals such as DMA
controllers, and can be applied via simulation by means of dedicated test-benches or by setting
up an environment including a processor, which executes a proper test program. In the latter
case, the developed programs can be exploited in later stages for testing, by adding suitable
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observability features. Experimental results demonstrating the method effectiveness are

DMA Controller
Direct memory access (DMA) is a process in which an external device takes over the control of
system bus from the CPU.
DMA is for high-speed data transfer from/to mass storage peripherals, e.g. hard disk drive,
magnetic tape, CD-ROM, and sometimes video controllers. For example, a hard disk may boast
a transfer rate of 5 M bytes per second, i.e.1 byte transmission every 200
ns. To make such data transfer via the CPU is both undesirable and unnecessary.
The basic idea of DMA is to transfer blocks of data directly between memory and peripherals.
The data don’t go through the microprocessor but the data bus is occupied. “Normal” transfer of
one data byte takes up to 29 clock cycles. The DMA transfer requires only 5 clock cycles.
Nowadays, DMA can transfer data as fast as 60 M byte per second. The transfer rate is limited
by the speed of memory and peripheral devices. A DMA controller interfaces with several
peripherals that may request DMA. The controller decides the priority of simultaneous DMA
requests communicates with the peripheral and the CPU, and provides memory addresses for
data transfer. DMA controller commonly used with 8088 is the 8237 programmable device. The
8237 is in fact a special purpose microprocessor.
Normally it appears as part of the system controller chip-sets. The 8237 is a 4-channel device.
Each channel is dedicated to a specific peripheral device and capable of addressing 64 K bytes
section of memory.

DMA 8237 IP Core

DACKi (DMA channel acknowledge): Acknowledges a channel DMA request from a device.
HRQ (Hold request): Requests a DMA transfer.
HLDA (Hold acknowledge): signals the 8237 that the Micro-processor has relinquished control
of the address, data and control buses.

DMA Controller
The mode register (MR) programs the mode of operation for a CHANNAL the request register
(RR) is used to request a DMA transfer via software, which is very useful in memory-to-memory
transfers. The mask register set/reset (MRSR) sets or clears the channel mask to disable or
enable particular DMA channels. The mask register (MSR) clears or sets all of the masks with
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one command instead of individual channels as with the MRSR. The status register (SR) shows
the status of each DMA channel.

VHDL (VHSIC hardware description language) VHSIC: very high-speed integrated circuit is a
hardware description language used in electronic design automation to describe digital and
mixed- signal systems such as field-programmable gate arrays and integrate circuits.
VHDL is a fairly general-purpose language, and it doesn't require a simulator on which to run
the code. There are many VHDL compilers, which build executable binaries. It can read and
write files on the host computer, so a VHDL program can be written that generates another
VHDL program to be incorporated in the design being developed. Because of this general-
purpose nature, it is possible to use VHDL to write a testbench that verifies the functionality of
the design using files on the host computer to define stimuli, interacts with the user, and
compares results with those expected.
It is relatively easy for an inexperienced developer to produce code that simulates successfully
but that cannot be synthesized into a real device, or is too large to be practical. One particular
pitfall is the accidental production of transparent latches rather than D-type flip-flops as storage
elements.
VHDL is not a case sensitive language. One can design hardware in a VHDL IDE (such as
Xilinx or Quartus) to produce the RTL schematic of the desired circuit. After that, the generated
schematic can be verified using simulation software (such as ModelSim) which shows the
waveforms of inputs and outputs of the circuit after generating the appropriate testbench. To
generate an appropriate testbench for a particular circuit or VHDL code, the inputs have to be
defined correctly. For example, for clock input, a loop process or an iterative statement is
required.
The key advantage of VHDL when used for systems design is that it allows the behavior of the
required system to be described (modeled) and verified (simulated) before synthesis tools
translate the design into real hardware (gates and wires). Another benefit is that VHDL allows
the description of a concurrent system (many parts, each with its own sub-behavior, working
together at the same time). VHDL is a
Dataflow language, unlike procedural computing languages such as BASIC, C, and assembly
code, which all run sequentially, one instruction at a time.
A final point is that when a VHDL model is translated into the "gates and wires" that are mapped
onto a programmable logic device such as a CPLD or FPGA, and then it is the actual hardware
being configured, rather than the VHDL code being "executed" as if on some form of a
processor chip. There are various types of Modeling in VHDL Language.

Conclusions
This Project will also provide the knowledge that how to start and design an Processor or IP
This project will provide knowledge about the DMA 8237 and also give knowledge about the IP
core the cost of IP core is very high in today’s Market so the project is beneficial for me as far as
it will use in many industries. This design is also used such kind of modeling style and tool that
the digits is also power aware in generation type DMA’s core.
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References
1. Intel 8237 data sheet
2. Design of Two-Dimension DMA Controller in
Media Multi-Processor SoC files
3. Direct Memory Access and DMA-controlled I/O
4. Modern development of DMA
5. Device Driver and DMA Controller Synthesis
6. Asynchronous System Bus Enhancement by
Interrupt and DMA Technique
7. The research of a parallel DMA control
mechanism in DSP
8. DMA control and transmission signal control
9. System-on-Chip (SoC) for Hand-held Compute-
intensive Embedded Systems
10. DMA-Aware Memory Energy Management.
11. Stepwise Refinement of Behavioral VHDL Specifications by Separation of Synchronization
and functionality.
12. Dr.Arti Vaish (Prof.)