Asic Design

ET 4351
Alexander de Graaf, EEMCS/ME/CAS
5/20/14

Delft
University of
Technology

Challenge the future

Outline.
1.  Design flow
2.  Synthesis
3.  Place & Route

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1.
Design flow

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 Design flowgraph
VHDL Std Cell
Source Lib

•  Tools
Synthesis
•  Synthesis: Synopsys Design Compiler
•  Place & Route: Cadence SOC Encounter
Area Gate
Timing Level
Constraints Netlist •  Process
•  UMC L90 SP

Place&Route
•  Standard cell library
•  Faraday:
•  fsd0a_a_generic_core
Area Gate Layout
Timing Level GDSII •  fod0a_b25_t25_generic_io
Constraints Netlist

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2.
Synthesis

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Synthesis flow

Asic Synthesis Flow Design Compiler Flow

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Synthesis Transformations

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Load Design and Libraries
•  Analyze
•  Reads source code files (Verilog or VHDL RTL)
•  Checks syntax and issues errors/warnings
•  Converts both Verilog and VHDL files into intermediate binary format
files, placed in CWD
•  Can use define_design_lib to redirect the files/directories to a sub-
directory

•  Elaborate
•  Reads the intermediate .pvl files and builds the ‘GTECH’ design in DC
memory (unmapped ddc format)
•  Sets the current design to the specified design
•  Links and auto-loads the specified design
•  Allows specification of parameter values: elaborate MY_TOP -
parameters “N=8, M=3”.
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Area and Timing Constraints

• Static Timing Analysis (STA)

• Modeling clocks

• Constraining input paths

• Constraining output paths

• Environmental attributes
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Static Timing Analysis

•  Main steps of STA

•  Break the design into sets of timing paths
•  Calculate the delay of each path
•  Check all path delays to see if the given timing constraints are met

•  Four types of paths

Combinational logic
PI Reg

Start point

Reg
End point
PO

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Static Timing Analysis

•  Path-based STA
•  Calculate the Arrival Time (AT) by adding cell delay in timing paths
•  Check all path delays to see if the given Required Arrival Time (RAT)
is met

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Static Timing Analysis (Cell delay)

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Static Timing Analysis (Setup Time)
•  To meet the setup time requirement:
•  Trequire >= Tarrival

•  Reg to Reg
•  Tarrival = Tclk1 + TDFF1(clk->Q) + Tpath
•  Trequire = Tclk2 - TDFF2(setup)
•  Tslack = Trequire - Tarrival
Clk_source

clk1
TDDF1+Tpath
Reg
Tarrival
clk2
Reg
Tsetup
clk1 clk2

Trequire Tslack

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Static Timing Analysis (Setup Time)
•  PI to Reg

•  Tarrival = TPI(delay) + Tpath

•  Trequire = Tcycle +Tclk1– TDFF1(setup)
•  Tslack = Trequire - Tarrival
Clk_source
Tcycle
Tarrival

TPI Tpath
PI Reg

clk1

Tsetup
clk1

Trequire Tslack

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Static Timing Analysis (Setup Time)

•  Reg to PO

•  Tarrival = Tclk1 + TDFF1(clk->Q) + Tpath

•  Trequire = Tcycle+Tclk1 - TPO(output delay)
•  Tslack = Trequire - Tarrival
Clk_source

clk1
TDDF1+Tpath
PO
Tarrival
Reg
TPO(output delay)

Tslack
clk1 Trequire
Tcycle

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 Static Timing Analysis (Setup Time)
•  PI to PO

•  Tarrival = TPI(delay) + Tpath

•  Trequire = Tcycle – TPO(output delay)
•  Tslack = Trequire - Tarrival
Clk_source

TPI+Tpath

PI PO
Tarrival

TPO(output delay)
Tslack
Trequire
Tcycle

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Static Timing Analysis (Hold Time)
•  To meet the hold time requirement:
•  Trequire <= Tarrival

•  Reg to Reg
•  Tarrival = Tclk1 + TDFF1(clk->Q) + Tpath
•  Trequire = Tclk2 - TDFF2(hold)
Clk_source
•  Tslack = Tarrival - Trequire
clk1
TDDF1+Tpath

Reg
clk2
Reg
clk2 Thold
Tslack
clk1
Trequire

Tarrival

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Static Timing Analysis (Hold Time)
•  PI to Reg
•  Tarrival = TPI(delay) + Tpath
•  Trequire = Tclk - TDFF(hold)
•  Tslack = Tarrival - Trequire
•  Reg to PO
•  Tarrival = Tclk + TDFF(clk->Q) + Tpath
•  Trequire = - TPO(output delay)
•  Tslack = Tarrival - Trequire
•  PI to PO
•  Tarrival = TPI(delay) + Tpath
•  Trequire = - TPO(output delay)
•  Tslack = Tarrival - Trequire

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Default Clock Behavior

•  Defining the clock in a single-clock design constrains all timing

paths between registers for single-cycle, setup time

•  By default the clock rises at 0ns and has a 50% duty cycle

•  By default DC will not “buffer up” the clock network, even when
connected to many clock/enable pins of flip-flops/latches
•  The clock network is treated as “ideal” - infinite drive capability
•  Zero rise/fall transition times
•  Zero skew
•  Zero insertion delay or latency
•  Estimated skew, latency and transition times can, and should be modeled for
a more accurate representation of clock behavior

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 Defining a Clock
Default clock with
50% duty cycle

Clock with specified create_clock -period 2 –waveform {0 0.6} –name My_CLK

duty cycle [get_ports Clk]

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 Modeling Clock

set_clock_uncertainty –setup TU [get_clocks CLK]

Pre-Layout: clock skew + jitter + margin

reset_design!
create_clock -p 5 -n MCLK Clk!
set_clock_uncertainty 0.5 MCLK!
set_clock_transition 0.08 MCLK!
set_clock_latency -source –max 4
MCLK!
set_clock_latency –max 2 MCLK

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Specifying Setup-Timing Constraints

•  Objective: Define setup timing constraints for all paths

within a sequential design
•  All input logic paths (starting at input ports)
•  The internal (register to register) paths
•  All output paths (ending at output ports)

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 Constraining Input Paths

The user must specify the latest arrival time of the data at input A

What is Tmax for N ?

create_clock –period 2 [get_ports Clk]

set_input_delay –max 0.6 –clock Clk [get_ports A]

The maximum delay for path N = 1.5 ns

create_clock –period 2.5 [get_ports Clk]

set_input_delay –max 0.9 –clock Clk [get_ports A]

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 Constraining Output Paths

The user must specify the latest arrival time of the data at output B

What is Tmax through S ?

create_clock –period 2 [get_ports Clk]

set_output_delay –max 0.8 –clock Clk [get_ports B]

The maximum delay to port B = 0.7 ns

create_clock –period 2 [get_ports Clk]

set_output_delay –max 1.3 –clock Clk [get_ports B]

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Environmental attributes

•  Input drivers and transition times

•  Capacitive output loads
•  Process/Voltage/Temperature
(PVT) operating conditions
•  Interconnect parasitic RCs

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Input drivers and transition times

•  Rise and fall transition times on an input port affect the cell
delay of the input gate

set_input_transition 0.12 [get_ports A]

set_driving_cell –lib_cell OR3B [get_ports A]
set_driving_cell –lib_cell FD1 –pin Qn [get_ports A]

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Capacitive output loads
Capacitive loading on an output port affects the transition time
and thereby the cell delay of the output driver

set_load [expr 30.0/1000] [get_ports B]

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Load budget

Assumptions:
1.  The maximum fanout capacitance of any block’s input port is
limited to the equivalent of 10 “and2a1” gates
2.  Output ports can drive a maximum of 3 other blocks
3.  The driving gate of every output is the cell inv1a1

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Interconnect parasitic RCs
•  A wire load model calculates one parasitic R and one C
for each net, based on the net’s fanout:
•  Models for various design sizes are supplied by your vendor
•  R/C values are average estimates based on data extracted from
similar designs which were fabricated using this process

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Synthesize Design

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Three interfaces to Design Compiler

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Filter Example

Filter Parameters:

FIR filter
128 taps
Sample Frequency: 48 kHz
Pass band: 9.6 kHz
Stop band: 11.0 kHz
Data width: 16 bits
Coefficient bit-width: 16 bits

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 Techmap I/O Cells
Techmap library independent I/O cells
Generic spec: Port spec:
•  Tech: io technology (faraday)
•  Limit: pad/core limited (core) •  Single io
•  Slew: fast/slow slew rate (slow) •  inpad (pad, o)
•  Width: vector width (only for vector IO) •  outpad (pad, i)
•  iopad (pad, i, e, o)
•  toutpad (pad, e, i)
•  Vector io
•  inpadv (pad, o)
•  outpadv (pad, i)
•  iopadv (pad, i, e, o)
•  iopadvv (pad, i, e, o)
•  toutpadv (pad, e, i)
•  toutpadvv (pad, e, i)

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 Memory Macro Cells
•  Macro cells generated by dedicated memory compilers

•  SHAA90_ : single-port static RAM (256-15k, 1-32)

•  SJAA90_ : dual-port static RAM (32-8k, 1-64)
•  SYAA90_ : single-port register-file (8-2k, 1-144)
•  SZAA90_ : two-port register-file (8-2k, 1-144)
•  SPAA90_ : via programmable ROM (512-128k, 1-128)

Examples:
SYAA90_128X16X1CM2
SPAA90_512X16X1BM1A

Words Bits/word Mux

W/L
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3.
Place and Route

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SOC Encounter Place&Route Flow
•  Verilog mapped design file
•  io_spec file Design Import and
•  Timing library files Load Libraries
•  Layout library files
Floorplan

Power Plan

Placement

Clock Tree Synthesis Optimization

Route

Verification

•  Verilog routed design file

Write output files
•  GDS2 Layout file

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 Chip Planning
1872.08 µm

Requirements:
•  Die size choices

1432.48 µm
•  2mm x 2mm (approx. € 5000)

•  4mm x 2mm (approx. € 10000)

•  Number of IO cells
•  Max. 84 (2mm x 2mm)

•  Max. 140 (4mm x 2mm)

•  Libraries Faraday 90 nm
•  Timing: fsd0a_a_generic_core*.lib,

fod0a_b25_t25_generic_io*.lib

•  Layout: fsd0a_a_generic_core*.lef,

fod0a_b25_t25_generic_io*.lef

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Ratio Signal IO/ Power, Ground IO

• Considering 2 effects
•  Electro-Migration
•  Simultaneous Switching outputs

• As a rule of thumb the ratio lies between

4 and 16 depending on clock rate, slew
rate and load capacitance

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 Ratio Signal IO/ Power, Ground IO

• 

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 Concept of Ground Bounce
Quiet Device
Output That
Is Affected

System Input
That is Affected
Load
Capacitance

Inductance of
lead frame, Current flow (red) during a high to
bound wired,
low transition causing “bounce.” This
package pin,
etc. can change the input thresholds to
the device as well as result in output
pulses being transmitted to a receiver.

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Pad/Core limited IO

Depends on the size of the core

•  Pad limited: smal width, large height
•  Core limited: large width, small height

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 Generate IO file
io.spec
N
I DataInReqxSI
I DataInxDI 15
I DataInxDI 14
I GNDIO 0
I VCCIO 0
I DataInxDI 13
I DataInxDI 9
O DataOutReqxSO
W
I DataInxDI 8
O DataInAckxSO

Script to generate iofile:

% genIoFile <#N> <#E> <#S> <#W> [<DW> <DH>] < io.spec > filter_top.io

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Soc Encounter GUI

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 Design Import
Design ⇒ Design Import

•  Verilog technology mapped design file

•  Timing libraries
•  Max: containing worst-case conditions
for setup-time analysis
•  Min: containing best-case conditions for
hold-time analysis
•  IO Assignment File

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 Floorplan (1)

Purpose:
•  Develop early physical layout to ensure
that design objectives can be archived
•  Minimum area for low cost
•  Minimum congestion for design
routable
•  Estimate parasitic for delay How:
calculation •  Specify size of die, core, IO
•  Analysis of power for reliability •  Placement of macro blocks
•  Gain early visibility into implementation •  Fix the areas where
issues standardcell will be placed

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 Floorplan (2)
Floorplan ⇒ Specify Floorplan

Floorplan ⇒ Automatic Floorplan ⇒ Plan Design…

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Floorplan (3)

Alternative placement by hand leads to better performance

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 Floorplan (4)

Module constraint options:

•  None
•  Guide
•  Fence
•  Region
•  Soft Guide

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 Floorplan(5): Edit Halo

A Halo:
•  Keeps standard cells from being
placed to close to macro cells
•  Avoid problems when routing
power lines of standard cells

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Powerplan (1)
Important issues with power nets:

•  IR Drop: voltage drop to resistance in power lines decrease VDD

resulting in slower circuits or may lead to violation of noise
margins
•  Electromigration: Thermally agitated metal ions are washed
away by flowing electrons

•  Create connectivity for power/ground nets not specified in the Verilog

netlist.
•  Add core power/ground rings that distribute power/ground around the
core
•  Add block power/ground rings that distribute power/ground around the
macro blocks (e.g. Memories)
•  Add stripes for better power distribution especially with fast designs
•  Add filler cells to fill the gaps between I/O cells

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 Powerplan(2): Add rings
Power ⇒ Power Planning ⇒ Add Rings…

•  Power ring around

the core
•  Power ring around
macrocells

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 Powerplan: Global Net Connections
Floorplan ⇒ Connect Global Nets…

•  Specify global power

and ground nets

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 Powerplan: Sroute and Add iofill cells
•  Fill the gaps between I/O cells
with filler cells to close the
power rings by abutment.

•  Use script PAR/BIN/fillperi.tcl

Route ⇒ Special Route…

•  Sroute
•  Padpins
•  Blockpins
•  StandardCellPins

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Cell placement (1)
Place ⇒ Standard Cells
•  Prototyping : Runs quickly, but components may not be placed at legal location.

•  Timing Driven:
•  Build timing graph before place.
•  Meeting setup timing
constraints with routability.
•  Limited IPO by upsizing/
downsizing instances.
•  Reorder Scan Connection
•  nets connected to either the
scan-in or scan-out are ignored.
•  Check placement after placed
Place ⇒ Check Placement
Verify ⇒ Geometry

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 Clock Tree Synthesis

Clock problem:

•  Heavy clock net loading

•  Long clock insertion delay
•  Clock skew
•  Skew across clocks
•  Clock to signal coupling effect
•  Clock is power hungry
•  Electromigration on clock net

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Clock Tree Synthesis (2): flow

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 Pre-CTS clock tree tracer

Clock ⇒ Tracer Pre-CTS Clock Tree ....

Things to look for include:

Ø  Clock, reset, or scan-enable connecting to
unexpected input pins.
Ø  Unexpected latches on the clock tree
Ø  Discrepancy between the number of
endpoints of clock, reset and scan trees.

For our example numbers are as follows:

•  clock tree: 443 with 442 flip-flop CK pins + 1 RAM CK pin
•  reset tree: 441 flip-flop RB pins
•  scan tree: 447 with 441 flip-flop SEL pins + 6 mux S pins, to choose
between the functional and test (scan chain) output signal.

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Mapping SDC to CTS spec

Timing Constraints Clock Tree Specs

create_clock AutoCTSRootPin / ClkGroup
create_generated_clock ThroughPin
set_clock_latency Maxdelay
set_clock_uncertainty Maxskew
set_clock_transition BufMaxTran / SinkMaxTran

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Clock Tree Synthesis (2)

CT Synthesis report:
•  Summary report and detail report
•  number of sub trees
•  rise/fall insertion delay
•  trigger edge skew
•  rise/fall skew
•  buffer and clock pin transition time
•  detailed delay ranges for all buffers add to clocks
•  Clock nets
•  Saves the generated clock nets
•  used to guide clock net routing
•  Clock routing guide
•  Saves the clock tree routing data
•  used as preroute guide while running Trial Route

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Clock Tree Display
Clock ⇒ Display Clock
Display By phase delay

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Route Route ⇒ Nanoroute ⇒ Route…

•  Specify eventually
routing features

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Finishing
Verify ⇒ Geometry....
Verify ⇒ Connectivity....

Design ⇒ Save GDS ...

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 Using Scripts

•  toplevel.tcl (The overall Place&Route script, calls all following scripts)

•  start.tcl (Imports design)
•  fplan.tcl (generates a floorplan)
•  pplan.tcl (generates the core, block rings and stripes and routes power)
•  pts.tcl (clock tree synthesis)
•  route.tcl (routes the design)
•  verify (generates verification logs, verilog, gds2 of routed design)

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