Digital Design

Sequential Logic Design -- Controllers

Slides to accompany the textbook Digital Design, First Edition,

by Frank Vahid, John Wiley and Sons Publishers, 2007.
http://www.ddvahid.com

Copyright © 2007 Frank Vahid

Instructors of courses requiring Vahid's Digital Design textbook (published by John Wiley and Sons) have permission to modify and use these slides for customary course-related activities,
Digital
subject to keeping Design
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 3.1
Introduction

• Sequential circuit
1
– Output depends not just on present inputs (as in a 1
combinational circuit), but on past sequence of inputs 0 Combinational F
b digital circuit
• Stores bits, also known as having “state”

– Simple example: a circuit that counts up in binary

1
• In this chapter, we will: a
?
0 Sequential F
– Design a new building block, a flip-flop, that stores one bit b digital circuit

– Combine that block to build multi-bit storage – a register Must know

sequence of
– Describe the sequential behavior using a finite state past inputs to
machine know output

– Convert a finite state machine to a controller – a

sequential circuit having a register and combinational logic

Digital Design
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Frank Vahid Note: Slides with animation are denoted with a small red "a" near the animated items
 3.2
Example Needing Bit Storage

• Flight attendant call button Call

button Bit
Blue light

– Press call: light turns on Cancel Storage

• Stays on after button released button

1. Call button pressed – light turns on

– Press cancel: light turns off
Call Blue light
– Logic gate circuit to implement this? button Bit a
Cancel Storage
button
Call Q
2. Call button released – light stays on
Cancel

Doesn’t work. Q=1 when Call=1, but Call Blue light

button Bit
doesn’t stay 1 when Call returns to 0
Cancel Storage
button

a
Need some form of “feedback” in the circuit
3. Cancel button pressed – light turns off

Digital Design
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Frank Vahid
 Clocks

• Clock period: time interval between pulses Freq Period

– Above signal: period = 20 ns
100 GHz 0.01 ns
10 GHz 0.1 ns
• Clock cycle: one such time interval
– Above signal shows 3.5 clock cycles 1 GHz 1 ns
100 MHz 10 ns
• Clock frequency: 1/period 10 MHz 100 ns
– Above signal: frequency = 1 / 20 ns = 50 MHz
• 1 Hz = 1/s

Digital Design
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 3.3
Finite-State Machines (FSMs) and Controllers

• Want sequential circuit with particular

b Controller
behavior over time x
laser

clk
• Example: Laser timer
patient
– Push button: x=1 for 3 clock cycles

– How? Let’s try three flip-flops

• b=1 gets stored in first D flip-flop

• Then 2nd flip-flop on next cycle, then 3rd flip-

flop on next b
D Q D Q D Q
• OR the three flip-flop outputs, so x should be
1 for three cycles clk
x

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 Need a Better Way to Design Sequential Circuits

• Trial and error is not a good design method

– Will we be able to “guess” a circuit that works for other desired behavior?
• How about counting up from 1 to 9? Pulsing an output for 1 cycle every 10
cycles? Detecting the sequence 1 3 5 in binary on a 3-bit input?

– And, a circuit built by guessing may have undesired behavior

• Laser timer: What if press button again while x=1? x then stays one another 3
cycles. Is that what we want?

• Combinational circuit design process had two important things

1. A formal way to describe desired circuit behavior
• Boolean equation, or truth table

2. A well-defined process to convert that behavior to a circuit

• We need those things for sequence circuit design

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 Describing Behavior of Sequential Circuit: FSM

• Finite-State Machine (FSM) Outputs: x

– A way to describe desired behavior of x=0 clk^ x=1
sequential circuit
• Akin to Boolean equations for
combinational behavior Off On

– List states, and transitions among clk^

states
• Example: Make x change toggle (0 to
1, or 1 to 0) every clock cycle Off On Off On Off On Off On

• Two states: “Off” (x=0), and “On” (x=1) cycle 1 cycle 2 cycle 3 cycle 4
clk
• Transition from Off to On, or On to Off,
on rising clock edge
state Off On Off On

• Arrow with no starting state points to Outputs:

initial state (when circuit first starts)
x

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 FSM Example: 0,1,1,1,repeat

Outputs: x
• Want 0, 1, 1, 1, 0, 1, 1, 1, ...
x=0 clk^ x=1 clk^ x=1 clk^ x=1
– Each value for one clock cycle
Off On1 On2 On3
• Can describe as FSM
– Four states clk^

– Transition on rising clock edge

to next state

clk
State Off On1On2On3 Off On1On2 On3 Off

Outputs:
x

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 Extend FSM to Three-Cycles High Laser Timer
Inputs: b; Outputs: x
• Four states
x=0
clk^
Off b’*clk^
• Wait in “Off” state while b is 0 (b’)
b*clk^
x=1 clk^ x=1 clk^ x=1
• When b is 1 (and rising clock edge),
transition to On1 On1 On2 On3
– Sets x=1

– On next two clock edges, transition to

On2, then On3, which also set x=1 clk

Inputs:
• So x=1 for three cycles after button b
pressed
State Off Off Off Off Off On1 On2 On3 Off

Outputs:
x

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 FSM Simplification: Rising Clock Edges Implicit
Inputs: b; Outputs: x
• Showing rising clock on every x=0
transition: cluttered and clk^
unnecessary Off b’ *clk^

– Make implicit -- assume every edge

b*clk ^
has rising clock, even if not shown.
x=1 clk^ x=1 clk^ x=1
• Eg., it is understood that a transition
out of a state is on a clock edge. On1 On2 On3

– What if we wanted a transition

without a rising edge
Inputs: b; Outputs: x
• We don’t consider such
asynchronous FSMs -- less common, x=0
and advanced topic
Off b’
a
• Only consider synchronous FSMs --
rising edge on every transition b
x=1 x=1 x=1
On1 On2 On3
Note: Transition with no associated condition thus
Digital Design transistions to next state on next clock cycle
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 FSM Definition

• FSM consists of Inputs: b; Outputs: x

– Set of states
• Ex: {Off, On1, On2, On3}
x=0
Off b’
– Set of inputs, set of outputs
• Ex: Inputs: {x}, Outputs: {b} b
x=1 x=1 x=1
– Initial state
• Ex: “Off” On1 On2 On3

– Set of transitions
• Describes next states We often draw FSM graphically,
• Eg: Has 5 transitions known as state diagram

– Set of actions
• Sets outputs while in states Can also use table (state table), or
textual languages
• Eg: x=0, x=1, x=1, and x=1

Digital Design
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 FSM Example: Secure Car Key

• Many new car keys include

tiny computer chip
– When car starts, car’s
computer (under engine hood)
requests identifier from key
Inputs: a; Outputs: r
– Key transmits identifier
• If not, computer shuts off car Wait
r=0 a’
a
• FSM
– Wait until computer requests K1 K2 K3 K4
ID (a=1)
r=1 r=1 r=0 r=1
– Transmit ID (in this case,
1101)

a.k.a., A Sequencer
Digital Design
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 FSM Example: Secure Car Key (cont.)
Inputs: a; Outputs: r

• Nice feature of FSM Wait

– Can evaluate output behavior r=0
a a’
for different input sequence
K1 K2 K3 K4

r=1 r=1 r=0 r=1

– Timing diagrams show states
and output values for different
input waveforms Q: Determine states and r value for given
input waveform:

clk clk
Inputs Inputs
a
a
State Wait Wait K1 K2 K3 K4 Wait Wait State Wait Wait K1 K2 K3 K4 Wait

a
Outputs Output
r r

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 FSM Example: Code Detector

• Unlock door (u=1) only when s

Start
buttons pressed in sequence: u
– start, then red, blue, green, red Red r
Code Door
g detector lock
a Green
• Input from each button: s, r, g, b Blue b
– Also, output a indicates that some a
colored button pressed

• FSM Inputs: s,r,g,b,a;

– Wait for start (s=1) in “Wait” Outputs: u
Wait
– Once started (“Start”) u=0 s
• If see red, go to “Red1” s’ ar’ ab’ ag’ ar’
a

• Then, if see blue, go to “Blue” Start a’

u=0
• Then, if see green, go to “Green” ar
ab ag ar
• Then, if see red, go to “Red2” Red1 Blue Green Red2
– In that state, open the door (u=1) a’ a’ a’
u=0 u=0 u=0
u=1
• Wrong button at any step, return Q: Can you trick this FSM to open the door, without
to “Wait”, without opening door
knowing the code?
a
A: Yes, hold all buttons simultaneously
Digital Design
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 Improve FSM for Code Detector

Inputs: s,r,g,b,a;
Outputs: u
Wait
u=0 s s’ ar’ ab’ ag’ ar’ a

Start
a’
u=0
ar
ab ag ar
Red1 Blue Green Red2
a’ a’ a’
u=0 u=0 u=0 u=1 Note: small problem still
remains; we’ll discuss later

• New transition conditions detect if wrong button pressed, returns to “Wait”

• FSM provides formal, concrete means to accurately define desired behavior

Digital Design
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 Standard Controller Architecture

• How implement FSM as sequential circuit? Inputs: b; Outputs: x

– Use standard architecture x=0
• State register -- to store the present state
Off b’
• Combinational logic -- to compute outputs,
and next state b
x=1 x=1 x=1
• For laser timer FSM
– 2-bit state register, can represent four On1 On2 On3
states

– Input b, output x

outputs
inputs
b x

FSM

FSM
– Known as controller
Combinational n1
logic
inputs

outputs
O
FSM

I FSM n0
Combinational
s1 s0
logic
S clk State register
a
m
m-bit m
clk
state register

Digital Design N
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Frank Vahid General version
 State Diagram Example

Modify the laser pulse generator state diagram (below left), so that the new
FSM will only produce one pulse (3 clk cycles wide) for each actuation of ‘b’
... or stated another way, one pulse out for one pulse in.

Inputs: b; Outputs: x Inputs: b; Outputs: x

x=0
Off
Off b’

b
x=1 x=1 x=1
On1 On2 On3
On1 On2 On3

Digital Design
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 3.4
Controller Design

• Five step controller design process

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 Controller Design: Laser Timer Example

• Step 1: Capture the FSM Inputs: b; Outputs: x

– Already done x=0
00
Off b’
a

• Step 2: Create architecture b

x=1 x=1 x=1
– 2-bit state register (for 4 states)
01 On1 10 On2 11 On3

– Input b, output x

outputs
inputs
b x

FSM

FSM
– Next state signals n1, n0 Combinational n1
logic
n0
• Step 3: Encode the states s1 s0 a

– Any encoding with each state clk State register

unique will work (in blue)

Digital Design
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 Controller Design: Laser Timer Example (cont)

• Step 4: Create state table Inputs: b; Outputs: x

x=0
00
Off b’
a
b
x=1 x=1 x=1
01 On1 10 On2 11 On3

outputs
inputs
x

FSM
b

FSM
Combinational n1
logic
n0
s1 s0
clk State register

Digital Design
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 Controller Design: Laser Timer Example (cont)

• Step 5: Implement

outputs
inputs
x

FSM
b

FSM
combinational logic Combinational n1
logic
n0
a
s1 s0
clk State register

x = s1 + s0 (note from the table that x=1 if s1 = 1 or s0 = 1)

n1 = s1’s0b’ + s1’s0b + s1s0’b’ + s1s0’b

n1 = s1’s0 + s1s0’

n0 = s1’s0’b + s1s0’b’ + s1s0’b

n0 = s1’s0’b + s1s0’

Digital Design
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 Controller Design: Laser Timer Example (cont)

• Step 5: Implement b
Combinational Logic
x

outputs
combinational logic (cont)

inputs
x

FSM
b

FSM
Combinational n1
logic n1 a
n0
s1 s0
clk State register
n0

s1 s0

clk State register

x = s1 + s0
n1 = s1’s0 + s1s0’
n0 = s1’s0’b + s1s0’

Digital Design
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 Understanding the Controller’s Behavior
x=0 x=0 x=0
00 b’ 00 b’ 00 b’
Off Off Off
b b b
x=1 x=1 x=1 x=1 x=1 x=1 x=1 x=1 x=1
01 On1 10 On2 11 On3 01 On1 10 On2 11 On3 01 On1 10 On2 11 On3

b x b x b x
0 0 0
0 0 0 1 0 0 1 1 1
0 0 1
n1 n1 n1
0 0 1
0 0 0 a
0 1 0
n0 n0 n0
0 1 0
0 0 0
s1 s0 s1 s0 s1 s0
clk clk clk
0 0 0 0 0 1
0 0 0 1 1 0

clk state=00 state=00 state=01

Inputs:
b
Outputs:
x

Digital Design
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 Controller Example:
Button Press Synchronizer
cycle1 cycle2 cycle3 cycle4
clk
Inputs:
bi
Button press
bi bo
synchronizer Outputs:
controller
bo

• Want simple sequential circuit that converts button press to single

cycle duration, regardless of length of time that button actually
pressed
– We assumed such an ideal button press signal in earlier example,
like the button in the laser timer controller

Digital Design
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 Controller Example:
Button Press Synchronizer (cont)

outputs
inputs
bi bo Step 2: Create architecture

FSM
FSM
FSM inputs: bi; FSM outputs: bo
Combinational
bi’ logic n1
bi
bi’ n0
A bi B bi C bi’ s1 s0 n1 = s1’s0bi + s1s0bi a
n0 = s1’s0’bi
bo=0 bo=1 bo=0 State register bo = s1’s0bi’ + s1’s0bi = s1s0
clk
Combinational logic
Step 1: FSM bo

Combinational logic bi
Inputs Outputs
s1 s0 bi n1 n0 bo n1
FSM inputs: bi; FSM outputs: bo 0 0 0 0 0 0
A
0 0 1 0 1 0
bi’ 0 1 0 0 0 1 n0
bi B
bi’ 0 1 1 1 0 1
00 bi 01 bi 10 bi’ 1 0 0 0 0 0 s1 s0
C
bo=0 bo=1 bo=0 1 0 1 1 0 0
State register
1 1 0 0 0 0 clk
Step 3: Encode states unused
1 1 1 0 0 0

Step 4: State table Step 5: Create

combinational circuit
Digital Design
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 Controller Example: Sequence Generator
• Want generate sequence 0001, 0011, 1100, 1000, (repeat)
– Each value for one clock cycle

– Common, e.g., to create pattern in 4 lights, or control magnets of a “stepper motor”

w
Inputs: none; Outputs: w,x,y,z x Inputs: none; Outputs: w,x,y,z
y
wxyz=0001 wxyz=1000 Combinational z wxyz=0001 wxyz=1000
logic
A D n1 A D
n0 00 11
s1 s0
State register 01 10
B C clk B C
wxyz=0011 wxyz=1100 wxyz=0011 wxyz=1100
Step 1: Create FSM Step 2: Create architecture Step 3: Encode states
w
x
w = s1
x = s1s0’ y
y = s1’s0 z
z = s1’ a
n1 = s1 xor s0
n0 = s0’
n0 n1
s1 s0
clk State register
Digital Design Step 4: Create state table
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 Controller Example: Secure Car Key
• (from earlier example)
Inputs: a; Outputs: r
Wait
r=0 a a’
Step 1

a
K1 K2 K3 K4
r=1 r=1 r=0 r=1
a r
Combinational
n2
Step 2
logic
n1
n0

s2 s1 s0
clk State register

Inputs: a; Outputs: r

000
r=0 a’
a
Step 3

001 010 011 100

r=1 r=1 r=0 r=1
Digital Design Step 4
Copyright © 2006 27
Frank Vahid We’ll omit Step 5 … circuits from equations is old hat by now.
 Example: Seq. Circuit to FSM (Reverse Engineering)
… a.k.a. Circuit Analysis
What does this y=s1’ A B
circuit do? z = s1s0’
a

states
n1=(s1 xor s0)x D C
x y
n0=(s1’*s0’)x
z Outputs:y, z

A B states
n1 yz=10 yz=10
with
D C outputs
n0 yz=00 yz=01

s1 s0
Inputs: x; Outputs:y, z
State register
clk x
x’ A B yz=10
yz=10 x’ x
Work backwards D x’ C yz=01

yz=00
Pick any state names you want x
states with
outputs and
Digital Design transitions
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 Common Pitfalls Regarding Transition Properties

a
• Only one condition should be b
true ab=11 –
– For all transitions leaving a next state? a

state

– Else, which one? a

a
a’b
a’b what if
• One condition must be true ab=00?
– For all transitions leaving a
state a’b’
a
– Else, where go?
a’b

Digital Design
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 Defining the FSM using VHDL

• Using the model put forth by the author … there will be two process
statements
– Combinational logic (next state logic and output logic combined)
– State register

• Modeling the state register

– Assume cs (current state) and ns (next state) are bit vectors

process (clk)
begin
if (clk’event and clk=‘1’) then
cs <= ns;
end if;
end process;

– This register is built with rising edge triggered D-FF’s.

Digital Design
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 FSM w/ VHDL (cont.)
• For a rising-edge triggered register, with
• For a falling-edge triggered async. reset …
register …
process (clk)
process (clk, reset)
begin
begin
if (clk’event and
if (reset = ‘1’) then
clk=‘0’) then
cs <= “000”;
cs <= ns;
elsif (clk’event and clk=‘1’) then
end if;
cs <= ns;
end process;
end if;
end process;

• For a falling-edge triggered register, with

sync. active-low reset …

process (clk, reset)

begin
if (clk’event and clk=‘0’) then
if (reset = ‘0’) then
cs <= “000”;
else
cs <= ns;
Digital Design end if;
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end process;
 FSM w/ VHDL (cont.)

• If you define enumerate a new type, life will be easier

– Example:
architecture Behavioral of dualEdgeDetect is
type stateType is (init, rising, wait4falling, falling);
signal ns, cs: stateType;
begin
Note the state names in
Modelsim … very handy …
no decoding required.

• Another benefit for using enumerated types for naming states is when designing the
combinatorial logic block
Digital Design
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 FSM w/ VHDL (cont.)
process(i, cs)
begin
• Setup combinatorial logic block in a case cs is
process statement and a case when init =>
statement: if i='0' then ns <= init;
else ns <= rising;
end if;
zr <= ‘0’; zf <= ‘0’;
Inputs: i; Outputs: z = zr,zf when rising =>
if i='0' then ns <=falling;
z = 00 else ns <= wait4falling;
end if;
init i’ zr <= ‘1’; zf <= ‘0’;
when wait4falling =>
i if i='0' then ns <= falling;
z=10 i i' z=01
z=00 else ns <= wait4falling;
end if;
rising wait4falling falling zr <= ‘0’; zf <= ‘0’;
when falling =>
ns <= init;
i zr <= ‘0’; zf <= ‘1’;
when others =>
i' ns <= init;
zr <= ‘0’; zf <= ‘0’;
end case;
end process;
Digital Design
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