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VHDL Command Summary

This document summarizes the key concurrent and sequential statements, specifications, declarations, and library units in VHDL. It includes statements like block, process, if/case, and assignments. It also covers specifications such as configurations and attributes. Declarations like signals, constants, types and subprograms are defined. Finally, it lists the main library units like entities, architectures, packages and configurations.

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59 views3 pages

VHDL Command Summary

This document summarizes the key concurrent and sequential statements, specifications, declarations, and library units in VHDL. It includes statements like block, process, if/case, and assignments. It also covers specifications such as configurations and attributes. Declarations like signals, constants, types and subprograms are defined. Finally, it lists the main library units like entities, architectures, packages and configurations.

Uploaded by

diego_tm
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOC, PDF, TXT or read online on Scribd
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VHDL Command Summary

Concurrent Statements
block_statement
label: block [(guard_expression)] [generic] [ports] [declarations] begin concurrent_statements end block [label];

component_instantiation_statement
label : name [ generic map (map) ] [ port map (signals) ];

concurrent_assertion_statement
assert condition [ report string_expression ] [ severity {NOTE | WARNING | ERROR | FAILURE} ];

concurrent_procedure_call
[ label : ] procedure_name [ (parameters) ];

concurrent_signal_assignment_statement
[ label : ] [ {conditional_assignment | assignment | selected_assignment} ];

generate_statement
label : [{ for specification | if condition }] generate concurrent_statements end generate [label];

process_statement
[label : ] process [ (sensitivity_list) ] [ variable_declaration ] [ type_declaration ] [subprogram_declaration ] [ declarations ] begin sequential_statements -- Cannot contain a wait statement if sensitivity_list is used end process [ label ];

Sequential Statements
assertion_statement
assert condition -- When condition is false [strng_expression] is printed [ report string_expression ] [severity { NOTE | WARNING | ERROR | FAILURE } ];

case_statement
case expression is -- Avoid the use of parenthesis, if possible when choices_1 => sequential_statements . . when choices_n => sequential_statements end case;

exit_statement
exit [ label ] [ when condition ];

if_statement
if condition then sequential_statements { elsif condition then sequential_statements } [ else sequential_statements ] end if;

loop_statement
[ label : ] [ while condition | for loop_specification ] loop sequential_statements end loop [ label ] ;

next_statement

next [ label ] [ when condition ];

null_statement
null;

procedure_call_statement
procedure_name [ (parameters) ] ;

return_statement
return expression; --For use in a Function return; --For use in a Procedure

signal_assignment_statement
target <= expression [ after time_expression ] . . { , expression [ after time_expression ];

variable_assignment_statement
target := expression ;

wait_statement
wait --A Function may not contain a wait_statement [ on signal_name {, signal_name} ] [ until conditional_expression ] [ for time_expression ] ;

Specifications
attribute_specification
attribute attribute_name of entity_name is expression ;

configuration_specifications
for component_name use [ generic_map_part ] [port_map_part] ;

Library & Use Clause


library_clause
LIBRARY names ;

use_clause
USE selected_names ;

Declarations
alias_declaration
alias name1 : type [ (indexes) ] is name2 [ (indexes) ] ;

attribute_declaration
attribute name : type ;

component_declaration
component identifier : [ generic (generic_list) ; ] [ port (port_list) ; ] end component ;

constant_declaration
constant name : type := expression ; constant name : array_type [ (indexes) ] := expression ;

file_declaration
file name : type is [ mode ] logical_name ;

signal_declaration
signal names : type [ constraint ] [ := expression ] ;

port_declaration
port ( names : direction type [ := expression ] [ ; more_signals ] );

subprogram_declaration
{ procedure name [ (parameters) ] | function name [ (parameters) ] return type; }

sub_program_body
is declarations begin

sequential_declarations end [name] ;

subtype_declaration
subtype name is [ resolution_function] type [constraint] ;

type_declaration
type name is definition;

variable_declaration
variable names : type [ constraint ] [ := expression ] ;

Library Units
architecture_body
architecture name of entity_name is [types] [constants] [signals] [subprograms] [other declarations] begin concurrent_statements end [name];

configuration_declaration
configuration name of entity_name is declarative_part block_configuration end [name];

entity_declaration
entity name is [generics] [ports] [declarations] [begin statements] --typically, an entity does not have statements. If it does, the statemnts cannot operate on signals end name;

package_body
package body name is [subprogram] [type] [constant [signal] [declarations] end [name];

package_declaration
package name is [subprogram] [type] [constant] [signal] [file] [alias] [USE clause] [declarations] end [name];

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