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S Karthick et al., International Journal of Emerging

VolumeTrends in Engineering
8. No. 10, OctoberResearch,
2020 8(10), October 2020, 6917 - 6924
International Journal of Emerging Trends in Engineering Research
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https://doi.org/10.30534/ijeter/2020/488102020

Design and Analysis of Braun Multiplier Using CMOS/GDI

Technique for Signal Processing
S Karthick1, K Nehru2, C Kamalanathan3, M Abdullah4, S Ananthakumaran5
1
Department of Electronics and Communication Engineering,
5
Department of Computer Science and Engineering,
Koneru Lakshmaiah Education Foundation, Vaddeswaram, AP, India
2
Department of Electronics and Communication Engineering, Institute of Aeronautical Engineering,
Telangana, India
3
Department of Electrical, Electronics and Communication Engineering, GITAM School of Technology,
GITAM Deemed to be University, Bengaluru Campus
4
Department of Electronics and Communication Engineering, Bannari Amman Institute of Technology, TN,
India
[email protected], [email protected], [email protected],
[email protected], [email protected]

 used to optimize the performance of the logic circuit. As the

ABSTRACT feature size of the CMOS technology continues to scale down,
leakage power has become an ever-increasing important part
Efficient arithmetic circuits are needed for cost effective and of the total power consumption of a chip. A reduction in the
computation intense signal processing applications. transistor count will have a drastic influence in the
Electronic appliances such as pagers, notebook computers performance of the VLSI circuits. The reduction in the
and laptops demands high reliable and portable circuits. With transistor size is much essential to increase the chip density.
the advent of high performance chips, power dissipation has But the scaling of transistor leads to short channel effects [1].
gained its importance for efficient chip design. The need to The dynamic power of the circuit depends on frequency of
explore efficient design techniques has increased to achieve
operation and activity factor [2].The delay reduction can be
high throughput and reduced power dissipation. Addition is
obtained due to less no of interconnections and reduction the
an obligatory and crucial arithmetic operation used in
node capacitance. In GDI technique the voltage drop across
application specific and general purpose systems. This paper
discusses the design of efficient adder and its implementation the N-channel is reduced which in turn reduces the power
in Braun multiplier using different logic styles like Gate consumption of the transistor [3]. The GDI logic helps to the
Diffusion Input (GDI) logic and Complementary Metal Oxide reduce the transistor count and allows to obtain the reduction
Semiconductor (CMOS). The design is implemented in in power consumption.
Cadence Virtuoso tool for 45 nm technological node. The
GDI logic style reduces the delay of Braun multiplier by 2. RELATED WORKS
42.38% with power optimization compared with CMOS logic
style. Multipliers play an important role in today’s digital signal
processing. As the technology improves over a period of time
Key words: Braun Multiplier, Kogge Stone Adder, GDI,
the need of efficient multiplier attract its significance which
CMOS, Digital Filter
offer reduced power consumption with optimized speed for
1. INTRODUCTION VLSI implementation. The transistor count is reduced by 8T
full adder to improve the performance [4]. The adder
Arithmetic circuits are extensively used in Very Large performance has huge impact on the optimization of the
Scale Integration (VLSI), Signal Processing and video multiplier [5]. Braun multiplier is the simplest parallel
processing applications. The current cutting-edge multiplier, with optimized dynamic range and throughput
technologies pay the way for the end user to improve the compare to traditional multipliers [6]. [7] Leakage power
flexibility and make the device portable. Arithmetic circuits increases when scaling is performed to increase the chip
play a vital role since performance metrics like die-area, density. [8] Improves the Area Delay Product (ADP) and
speed of operation and power dissipation depend on the Power Delay Product (PDP) by decreasing the transistor count
efficiency of the data path elements. The CMOS technology is of adder elements. [9] Reduced the sub threshold leakage
current intern reduces the leakage power using 8T cell design.
[10] To optimize the threshold voltage the substrate bias
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voltage of MOS transistor is controlled. [11] Proposed inner planned with (z-1) adders and z2 AND gate as shown in
gate engineered Metal Oxide Semiconductor Field Effect Figure 1. In parallel with AND gate each product term is
Transistor (MOSFET) to reduce the leakage current in turn generated. The partial product at a particular row is added
reduce the power consumption of the transistor. In Sub with previously generated sum of partial products.
micron CMOS technology temperature drift plays the major
role in designing efficient systems [12]. The MOSFET
transistor switches are not able to operate at high voltages
even the it has advantage in terms of speed and transistor size
[13]. The power efficient memory cell is implemented using
GDI logic [14].[15] Designed a CMOS invertor with second
function to reduce the total number of gates.[16] designed and
simulated CMOS logic to obtain high fan out and less delay
circuits. [17] Implemented Braun multiplier using various
full adders with different transistor count to obtain high speed
circuits at the expense of increased in the chip area. [18]
Utilized parallel adders to improve the speed of an arithmetic
circuit. The conventional Braun multiplier will have ripple
carry adder at the final addition stage. It is replaced by Kogge
stone adder with 14T XOR and 12T XOR gate to decreases
the delay [19].The multiplier like Braun multiplier, Vedic
multiplier and Baugh Wooley multiplier using Kogge stone Figure 1: Braun Multiplier
adder is implemented to optimist the delay. The Braun
multiplier outperforms other multipliers in terms of With the generated sum has to be added with one bit shifted
throughput [20]. carry out. The Carry Save Adder performs the carry out
The high speed Kogge stone adder of various bits is shifting operation and final stage addition to obtain the final
designed and simulated using Xilinx ISE tool. The result partial product term is carried by Ripple carry adder (RCA).
shows the Kogge stone adder outperformed the other For less than 16 bits these multiplier optimize the circuit in
conventional adders in terms of speed with increase in die terms of speed, die area and power consumption. The delay
area [21]. The power consumption and transistor count can be depends on the Full Adder and RCA adder in the last stage.
reduced by GDI technique [22].[23] Designed and The power and area can be reduced by using bypassing
implemented Kogge stone adder using CMOS and GDI logic techniques like row bypassing and column bypassing
and simulated using Cadence design suite for 180nm techniques. The modified adder cell in two-dimensional
technology. The results show that the Kogge stone adder bypassing consists of a FA, tri-state buffers, 2-to-1 mux and
designed using GDI logic consumes less no of transistor. [24] AND gate at the carry output of FA as represented in Figure 2.
Compared the performance of CMOS and GDI logic styles.
[25] Designed 64-bit Kogge stone adder and simulated using
Mentor graphics EDA tool in 130nm technological node. Due
to less fan-out and minimum logic depth Kogge stone adder
designed using GDI technique has higher throughput. [26]
Using faster adders like carry select, carry save and Kogge
stone adder designed multiplier to improve the performance.
[27] Designed a full adder circuit based on GDI and
transmission gate technique to optimize the power
dissipation. [28] Optimized the full adder using GDI
technique. The simulation is done using CADENCE tool at
45nm technology reveals an optimization in terms of power
dissipation

3. BRAUN MULTIPLIER

Braun multiplier saves an array of carry to optimize the

speed. The structure comprises of cluster of AND gates and
adders arranged in the iterative way. It is called as
non-additive multipliers. A z*z bit Braun multiplier can be Figure 2: 4*4 Bypassing Braun Multiplier
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4. IMPLEMENTATION OF BRAUN MULTIPLIER 4.3 OR Gate

USING CMOS & GDI TECHNIQUE
The OR gate implements logical disjunction. The OR gate
To verify the performance of the Braun multiplier it is will produce logic low only when the applied all input value is
implemented in Cadence Virtuoso tool for 45 nm technology low. The OR gate will be used to find the logic low value
The GDI logic and CMOS logic for different components are among the applied input values. The number of PMOS and
implemented. NMOS transistor required implementing two inputs OR gate
is 6 and 2 for CMOS and GDI logic respectively. Figure 5
4.1 Inverter represents CMOS and GDI two input OR gate.

The inverter is the fundamental gates in electronics. It

consists of a PMOS and NMOS connected as shown in Figure
3. It produces the output which is exact inverse of input. The
circuitry of inverter while designed using CMOS & GDI
technique is unique. The no of transistor required for
implementation of inverter is 2.

Figure 5: OR Gate Using a) CMOS b) GDI

Figure 3: Inverter
4.4 EXOR Gate
4.2 AND Gate
The Exclusive OR (EXOR) gate produces high output when
The AND gate is a basic digital logic gate that the applied numbers of true inputs are odd. The modulo-2
implements logical conjunction. A logical high output is addition will be performed by EXOR gate. The total no of
generated when the applied inputs are all high value even if PMOS required implementing EXOR gate is 7 for CMOS and
one input value is low logic then it gives logic low output. A 2 for GDI and the NMOS required is 7 and 2 respectively.
two input AND gate is implemented using CMOS and GDI Figure 6 shows the EXOR gate implementation using CMOS
logic. The total number of transistor required to implement and GDI logic.
two input AND gate is 6 using CMOS logic and 2 when
implemented using GDI logic. The Figure 4 shows the logical
diagram for AND gate using CMOS and GDI styles.

Figure 6: EXOR Gate Using a) CMOS b) GDI

4.5 Multiplexer

Figure 4: AND Gate Using a) CMOS b) GDI Multiplexer (MUX) is a device that permits the digital signal
from various sources and routed it onto a single line for
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transmission. A multiplexer of 2n inputs has ⌈n⌉ select lines, summed to get 4 sum bits and 1 final carry out bit. It consists
which decides which input line has to be transmitted to the of pre-processing, carry generation and post processing stage.
output. Figure 7 shows the MUX architecture design. The Figure 9 represents the logical diagram of Kogge stone
MUX can be designed by using 12 MOSFETs in CMOS logic, Adder.
in which 6 PMOS, 6 NMOS are used, whereas GDI logic
requires 1 PMOS and 1 NMOS to implement.

Figure 7: MUX Architecture Using a) CMOS b) GDI

Figure 9: Kogge Stone Adder
4.6 Full Adder Figure 10 shows the output wave form sum and carry bits for
the given input condition. The bits a0, b0, cin are added and the
The full-adder circuit adds two input bits (A, B) with the corresponding sum is obtained. Whereas, the carry out
input carry(C). It outputs two one-bit binary numbers, sum (S) generated is sent to next stage as cin. Similarly for a1, b1, a2, b2,
and carry (C1). The full adder circuit is shown in Figure 8. a3, b3 the similar performance is carried and the final carry is
The full-adder is usually a component in a cascade of adders, taken as cout.
which add 4, 8, 16, 32 bits of binary numbers. The full adder
shown in Figure 8 consist of AND, OR and EXOR gates.
These gates are implemented using CMOS and GDI
technique. When a full adder is implemented using CMOS
logic the total no of transistor required is 46. The number of
transistor need is 14 while implemented in GDI logic.

Figure 10: Kogge Stone Adder Output Waveform

Figure 8: Full Adder Circuit

Table 1 show the transistor count of Kogge stone adder
designed using CMOS and GDI logic. The number of gates
4.7 Kogge Stone Adder required to design a Kogge Stone adder is 14 AND gate + 5
OR gate + 8 EXOR. The transistor count of the Kogge Stone
To obtain the high performance arithmetic circuits Kogge adder is 226 when designed using CMOS logic. While design
stone Adder is used. The Kogge stone adder is a 4-bit adder in the Kogge Stone adder using GDI technique the transistor
which the number of inputs is 8 with a carry bit, which are count is 82.
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Table 1: Transistor Count of Kogge Stone Adder propagation carry bit. If in any cases we get 0 bits in product
of two binary numbers, all those terms are directly bypassed
Using and the product output is generated. Kogge Stone adder is
Using GDI
Gate CMOS used at the final addition stage to optimize the power and
Adder
type Transistor Transistor critical delay. Figure 12 shows the waveforms of the Braun
Count Count multiplier using Kogge stone adder. The circuit is simulated
for an input conditions A = 1101 and B =0110, the final
Kogge AND 84 56
output values are 01001110 as shown in Figure 12. Similarly
stone OR 30 10 random inputs are applied to verify the functionality of the
Adder EXOR 112 16 circuit. The Braun multiplier is designed using CMOS logic
style and GDI logic style and the output is verified.

4.8 Braun Multiplier

In Braun multiplier parallel computation of the partial

products are done and the end result will be obtained by
collection of Carry Save Adders. The completion time is
limited by the depth of the carry save array, and by the carry
propagation in the adder. Figure 11 shows 4*4 Braun
multiplier design. The inputs are applied to the AND gates
and the output of AND gate is applied to the adder cells. The
adder cells gives two outputs sum and carry which are
propagated to next stage as inputs.

Figure 12: Braun multiplier Output waveform

Figure 13 to 16 shows the power and critical delay of the

Braun Multiplier implemented using Kogge stone adder in
CMOS and GDI logic.

Figure 13: Average Power of Braun multiplier designed

Figure 11: 4*4 Braun multiplier using Kogge Stone Adder using CMOS Logic

Here, all the bits from p0 to p6 are obtained by adding the

respective terms in those columns, whereas p7 is the final

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carry adder and Kogge stone adder in CMOS logic due to the
minimization of the switching activity and leakage current
reduction.
.
Table 2: Performance Comparisons of Braun Multiplier

Performance
Metrics Power Delay PDP
(µW) (ps) (µW-ps)
Multiplier Design
Figure 14: Average Power of Braun multiplier designed
Using ripple carry
using GDI Logic 10.33 143.9 1486.487
adder in CMOS

Using 14 transistor
20.01 34.45 689.344
adder in CMOS

Using kogge stone

17.22 114.5 1971.690
adder in CMOS

Using kogge stone

6.716 65.97 443.054
adder in GDI

Figure 15: Dealy of Braun multiplier designed

using CMOS Logic

Figure 17: PDP of 4*4 Braun Multiplier

Figure 16: Dealy of Braun multiplier designed
using GDI Logic
The delay of the Braun multiplier designed by Kogge stone
adder in GDI logic is reduced by 42.38 % compared with
5. SIMULATION RESULTS AND PERFORMANCE
ANALYSIS CMOS logic. This is due to the minimization of the critical
path delay. The reduced power dissipation demonstrates the
The Braun multiplier is implemented in 45nm technology in PDP reduction as shown in Table 2.
Cadence Virtuoso tool. The circuit schematics designed and
are simulated for functional verification. The Braun
multiplier is designed using ripple carry adder, 14 transistor
adder circuit, Kogge stone adder for both CMOS/GDI logic.
The power, delay and Power delay product (PDP) is shown in
the Table 2. From the reports, it is observed that the Braun
multiplier designed using ripple carry adder and 14 transistor
adder consumes power of 10.33 µW and 20.01 µW
respectively. It can observed from the table that power
consumption of the Braun multiplier designed using the
Kogge stone adder in GDI logic is reduced by 34.99% and Figure 18: Direct Form I FIR Filter Structure
61% compared with Braun multiplier designed using ripple
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