10 Chapter 1 and source (and of course between gate and substrate as a result). Figure 1-5(a) then indicates the conditions prevailing with the channel established but no current flowing between source and drain (V,,=0). Now consider the conditions prevailing when current flows in the channel by applying a voltage V,, between drain and source. There must, of course, be a corresponding IR drop = V,,, along the channel. ‘This results in the voltage between gate and channel varying with distance along the channel with the voltage being a maximum of ve ‘at the source end. Since the effective gate voltage is V, = V,,- V, (no current flows when V,, < V,), there will ‘be voltage available to invert the channel at the drain end so fong as V,,-V,> V,,. The limiting condition comes when V,, = V,,~ V,. For all voltages V,< V,, ~ V,, the device is in the non-saturated region of operation which is the condition shown in Figure |-5(b) Consider now what happens when V,, is increased to a level greater than V,, ~ V, In this case, an IR drop = V,, ~ V, takes place over less than the whole length of the channel so that over part of the chapnel, near the drain, there is insufficient electric field available to give rise to an inversion layer to create the channel. The channel is therefore ‘pinched off’, as indicated in Figure 1-S(c). Diffusion current completes the path from source to drain in this case, causing ihe channel to exhibit a high resistance and behave as a constant current source. This region, known as saturation, is characterized by almost constant current for increase of V,, above V,, = V,, - V,. In all cases, the channel will cease to exist and no current will flow when V,, < V,. Typically, for enhancement mode devices, V,= 1 volt for V,,, = 5 volt or, in general terms, V,=().2 V,,. 1.6 Depletion mode transistor action For depletion mode devices the channel is established, because of the implant, even when V,, =0, and to cause the channel to cease to exist a negative voltage V,,must be applied between gate and source. V,, is typically <-0.8 Vp... depending on the imptant and substrate bias, but, threshold voltage differences aside, the action is similar to that of the enhancement mode transistor, Commonly used symbols for nMOS and pMOS transistors are set out in Figure | nMOS fabrication A brief introduction to the general aspects of the polysilicon gate self-aligning AMOS fabrication process will now be given. As well-as being relevant in their own right, the fabrication processes used for nMOS are relevant to CMOS and——— Areview of microelectronics and an introduction to MOS technology 11 sae 4 4 Mos Ms MOS ‘enhancement depieton —_ enhancement Figure 1-6 Transistor circuit symbols BiCMOS which may be viewed as involving additional fabrication steps. Also, it is clear that an appreciation of the fabrication processes will give an insight into the way in which design information must be presented and into the reasons for certain performance characteristics and limitations. An nMOS process is illustrated in Figure 1-7 and may be outlined as follows: 1. Processing is carried out on a thin wafer cut from a single crystal of silicon of high purity into which the required p-impurities are introduced as the crystal is grown. Such wafers are typically 75 to 150 mm in diameter and 0.4 mm thick and are doped with, say, boron to impurity concentrations of 10'%/cm? to 10%/cm?, giving resistivity in the approximate range 25 ohm cm to 2 ohm cm. 2. A layer of silicon dioxide (SiO;), typically { um thick, is grown all over the surface of the wafer to protect the surface, act as a barrier to dopants during processing, and provide a generally insulating substrate onto which other layers may be deposited and patterned. 3. The surface is now covered with a photoresist which is deposited onto the wafer and spun to achieve an even distribution of the required thickness. 4. The photoresist layer is then exposed to ultraviolet light through a mask which defines those regions into which diffusion is to take place together with transistor channels. Assume, for example, that those areas exposed to ultraviolet radiation are polymerized (hardened), but that the areas required for diffusion are shielded by the mask and remain unaffected. 5. These areas are subsequently readily etched away together with the underlying silicon dioxide so that the wafer surface is exposed in the window defined by the mask.Thick oxide (1 ym) Pattermed poly (1-2 um) ‘on thin oxide (800-1000 A) Figure 1-7 nMOs fabrication processA review of microelectronics and an introduction to MOS technology 13 ] SS] © dittusion (1 um deep) Contact holes (cuts) Figure 1-7 continued 6. ‘The remaining photoresist is removed and a thin layer of SiO, (0.1 xm typical) is grown over the entire chip surtace and then polysilicon is deposited on top of this to form the gate structure. The polysilicon layer consists of heavily doped polysilicon deposited by chemical vapor deposition (CVD). In the fabrication of fine pattern devices, precise control of thickness, impurity concentration, and resistivity is necessary, . Further photoresist coating and masking allows the polysilicon to be patterned (as shown in Step 6), and then the thin oxide is removed to expose areas into which n-type impurities are to be diffused to form the source and drain as shown. Diffusion is achieved by heating the wafer to a high temperature and passing a gas containing the desired n-type impurity (for example, phosphorus) over the surface as indicated in Figure 1-8. Note that the polysilicon with underlying thin oxide and the thick oxide act as masks during diffusion — the process is self-aligning. . Thick oxide (SiO,) is grown over all again and is then masked with photoresist and etched to expose selected areas of the polysilicon gate and the drain and Source areas where connections (i.e. contact cuts) are to be made. . The whole chip then has metal (aluminum) deposited over its surface to a thickness typically of 1 um. This metal layer is then masked and etched to form the required interconnection pattern.14° Chapter 1 Figure 1-8 Diffusion process It will be seen that the process revolves around the formation or deposition and patterning of three layers, separated by silicon dioxide insulation. The layers are diffusion within the substrate, polysilicon on oxide on the substrate, and metal insulated again by oxide. To form depletion mode devices it is only necessary to introduce a masked ion implantation step between Steps 5 and 6 in Figure 1-7. Again, the thick oxide acts as a mask and this process stage is also self-aligning, Consideration of the processing steps will reveal that relatively few masks are needed and the self-aligning aspects of the masking processes greatly ease the problems of mask registration. In practice, some extra process steps are necessary, including the overglassing of the whole water, except where contacts to the outside world are required. However, the process is basically straightforward to envisage and circuit design eventually comes down to the business of delineating the masks for each stage of the process. The essence of the process may be reiterated as follows. 1.7.1 Summary of an nMOS process + Processing takes place on ‘a p-doped silicon crystal wafer on which is grown a ‘thick’ layer of SiO,. * Mask | —Pattern SiO, to expose the silicon surface in areas where paths in the diffusion layer or source, drain or gate areas of transistors are required, Deposit thin oxide over all. For this reason, this mask is often known as the ‘thinox’ mask but some texts reer to it as the diffusion mask. * ‘Mask 2— Pattern the ion implantation within the thinox region where depletion mode devices are to be produced — self-aligningA review of microelectronics and an introduction to MOS technology 15 + Mask 3 — Deposit polysilicon over all (1.5 jum thick typically), then pattern using Mask 3. Using the same mask, remove thin oxide layer where it is not covered by polysilicon. * Diffuse n* regions into areas where thin oxide has been removed. Transistor drains and sources are thus self-aligning with respect to the gate structures. * Mask 4 — Grow thick oxide over all and then etch for contact cuts. * Mask 5 — Deposit metal and pattern with Mask 5. ‘ * Mask 6 — Would be required for the overglassing process step. 1’ tao fabrication pe ‘There are a number of approaches to CMOS fabrication, including the p-well, the n-well, the twin-tub, and the silicon-on-insulator processes. In order to introduce the reader to CMOS design we will be concerned mainly with well-based circuits. The p-well process is widely usedin practice and the n-well process is also popular, particularly as it was an easy retrofit to existing nMOS lines. For the lambda-based rules set out later, we will assume a p-well proagss. 1.8.1 The p-well process A brief overview ofthe fabrication steps may be obtained with reference to Figure 1-9, noting that the basic processing steps are of the same nature as those used for nMOS. . In primitive terms, the structure consists of an n-type substrate in which p- devices may be formed by suitable masking and diffusion and, in order to accommodate n-type devices, a deep p-well is diffused into the n-type substrate as shown, This diffusion must be carried out with special care since the p-well doping concentration and depth will affect the threshold voltages as well as the breakdown voltages of the n-transistors. To achieve low threshold voltages (0.6 to 1.0 V), we need either deep well diffusion or high well resistivity. However, deep wells require larger spacing between the n- and p-type transistors and wires because of laterai diffusion and therefore a larger chip area. ‘The p-wells act as substrates for the n-devices within the parent n-substrate, and, provided that voltage polarity restrictions are observed, the two areas are electrically isolated. However, since there are now in effect two substrates, two Substrate connections (V,,,, and Ves) are required, as shown in Figure 1-10.16 Chapter 1 Figure 1-9 CMOS p-well process steps Figure 1-10 CMOS p-well inverter showing Voy and Ves substrate connectionsA review of microelectronics and an introduction 10 MOS technology - In all other respects — masking, patterning, and diffusion — the process is similar to nMOS fabrication. In summary, typical processing steps are: + Mask 1 —defines the areas in which the deep p-well diffusions are to take place. . + Mask 2 — defines the thinox regions, namely those areas where the thick oxide is to be stripped and thin oxide grown to accommodate p- and n-transistors and diffusion wires. * Mask 3 — used to pattern the polysilicon layer which is deposited after the thin oxide, Mask 4—A p-plus mask is now used (to be in effect ‘Anded’ with Mask 2) to define all areas where p-diffusion is to take place. Mask 5 — This is usually performed using the negative form of the p-plus mask and, with Mask.2, defines those areas where n-type diffusion is to take place. + Mask 6 —Contact cuts are now defined. + Mask 7 —The metal layer pattern is defined by this mask. * Mask 8 — An overall passivation (overglass) layer is-now applied and Mask 8 is needed to define the openings for access to bonding pads. 1.8.2, The n-well process As indicated earlier, although the p-well process is widely used, n-well fabrication has also gained wide acceptance, initially as a retrofit to nMOS lines. N-well CMOS circuits are also superior to p-well because of the lower substrate bias effects on transistor threshold voltage and inherently lower parasitic capacitances associated with source and drain regions. Typical n-well fabrication steps are illustrated in Figure 1-11. The first mask defines the n-well regions. This is followed by a low dose phosphorus implant driven in by a high temperature diffusion step to form the n-wells. The well depth is optimized to ensure against p-substrate to p* diffusion breakdown without compromising the n-well to n* mask separation. The next steps are to define the devices and diffusion paths, grow field oxide, deposit and pattern the polysilicon, carry out the diffusions, make contact cuts, and finally metallize as before. Tt will be seen that an n* mask and its complement may be used to define the a- and p-diffusion regions respectively. These same masks also include the Vpp and V,; contacts (respectively). It should be noted that, alternatively, we could have used a p* mask and its complement, since the n* and p* masks are generally complementary. % By way of illustration, Figure 1-12 shows an inverter circuit fabricated by the n-well process, and this may be directly compared with Figure 1-10, .‘Over glass with cuts for bonding padé * Figure 1-11 Main steps in a typical n-well process Figure 1-12 Cross-sectional view of n-well CMOS inverter Owing to differences in charge carrier mobilities, the h-well process creates ‘non-optimum p-channel characteristics. However, in many CMOS designs (such ‘as domino-logic and dynamic-logic structures), this is relatively unimportant since they contain a preponderance of n-channel devices. Thus the n-channel transistors are mainly those used to form logic elements, providing speed and high density of elements,1:9 ‘A reyiew of microelectronics and an introduction to MOS technology 19 Latch-up problems can be considerably reduced by using a fow-resistivity epitaxial p-type substrate as the starting material, which can subsequently act as a very low resistance ground-plane to collect substrate currents. However, a factor of the i-well process is that the performance of the already poorly performing p-transistor is even further degraded. Modern process lines have come to grips with these problems, and’ good device performance may be achieved for both p-well and n-well fabrication. « The design rules which are presented for 1,2 jim and 2 [1m technologies in this text are for Orbif™ n-well processes. 1.8.2.1 The Berkeley n-well process There are a number of p-well and n-well fabrication processes, and, in order to look more closely at typical fabrication steps, we will use the Berkeley n-well process as an example. This précess is illustrated in Figure 1-13. 1.8.3 The twin-tub process A logical extension of the p-well and n-well approaches is the twin-tub fabrication process. Here we start with a substrate of high resistivity n-type material and then create both n-well and p-well regions. Through tis process it is possible to preserve the performance of n-transistors without compromising the p-transistors. Doping control is more readily achieved and some relaxation in manufacturing tolerances results. This is particularly important as far as latch-up is concerned. In general, the twin-tub process allows separate optimization of the n- and p- transistors. The arrangement of an inverter is illustrated in Figure 1-14, which may in turn be compared with Figures 1-10 and 1-12. Thermal aspects of processing The processes involved in making nMOS and CMOS devices have differing high temperature sequences as indicated in Figure 1-15. ‘The CMOS p-well process, for example, has a high temperature p-well diffusion process (1100 to 1250°C), the nMOS process having no such requirement. Because of the simplicity, ease of fabrication, and high density per unit area of nMOS circuits, many of the earlier IC designs, still in current use, have been fabricated using nMOS technology, and it is likely that nMOS and CMOS system designs will continue to coexist for some time to come.