NANDHA COLLEGE OF TECHNOLOGY

Academic Year 2022-23 (Even Semester)

LESSON PLAN
Name of the staff/
Mrs.K.Poornima /AP/E.C.E.
Designation/Dept

Subject Code & Name EC 8095/VLSI DESIGN

Class & Semester III-ECE & VI Semester

No. of Times Already
1
Taken
Lecture : 3 Tutorial : 0 Practical : 0 Credit : 3 Total : 45 Periods

ACTUAL
STAFF HoD
S.No DATE PERIOD TOPICS DATE OF
SIGN SIGN
COMPLETION

UNIT I -INTRODUCTION TO MOS TRANSISTOR

1 1.2.23 6 Introduction.
2 2.2.23 1 MOS transistors.
3 3.2.23 4 CMOS Logic,CMOS Inverter.
4 4.2.23 5 Pass transistor,Transmission gate.
5 6.2.23 7 Layout Design Rules,Gate layouts.
6 7.2.23 2 Stick Diagram.
7 8.2.23 6 Long channel I-V,C-V characteristics.
8 9.2.23 1 Non ideal Effects,DC Transfer characteristics.
9 10.2.23 4 RC delay model,Elmore delay ,Linear Delay model.
10 13.2.23 7 Logical effort,Parasitic Delay,Delay in logic gates.
11 14.2.23 2 Scaling.
UNIT II- COMBINATIONAL MOS LOGIC CIRCUITS

12 15.2.23 6 CircuitFamilies:Static CMOS,Ratioed Circuits.

13 16.2.23 1 Cascode Voltage Switch Logic.
14 17.2.23 4 Dynamic Circuits.
15 18.2.23 5 Pass Transistor Logic.
16 20.2.23 7 Transmission Gates.
17 21.2.23 2 Domino, Dual Rail Domino.
18 22.2.23 6 CPL,DCVSPG.
19 23.2.23 1 DPL, Circuit Pitfalls.
20 24.2.23 4 Dynamic Power.
21 6.3.23 7 Static Power.
22 7.3.23 2 Low Power Architecture.
UNIT III-SEQUENTIAL CIRCUIT DESIGN

23 8.3.23 6 Static latches and Registers.

24 9.3.23 1 Dynamic latches and Registers.
25 10.3.23 4 Pulse Registers.
 26 13.3.23 7 Sense Amplifier Based Register.
27 14.3.23 2 Pipelining.
28 15.3.23 6 Schmitt Trigger.
29 16.3.23 1 Monostable Sequential Circuits.
Astable Sequential
30 17.3.23 4
Circuits.
31 18.3.23 5 Timing Classification Of Digital System.
32 20.3.23 7 Synchronous Design.
UNIT IV- DESIGN OF ARITHMETIC BUILDING BLOCKS AND SUBSYSTEM

ARITHMETIC BUILDING BLOCKS:

33 21.3.23 2
Data Paths, Adders.
34 22.3.23 6 Multipliers.
35 23.3.23 1 Shifters.
36 24.4.23 4 ALUs.
Power and speed tradeoffs.
37 3.4.23 7
38 4.4.23 2 Case Study: Design as a tradeoff.
39 5.4.23 6 Memory Architectures and Building Blocks.
40 6.4.23 1 Memory Core.
41 10.4.23 7 Memory Peripheral Circuitry.
42 11.4.23 2 Revision.
UNIT-V IMPLEMENTATION STRATEGIES AND TESTING

43 12.4.23 6 FPGA Introduction.

44 13.4.23 1 FPGA Building Block Architectures.
45 17.4.23 7 FPGA Interconnect Routing Procedures.
46 18.4.23 2 Design for Testability: Ad Hoc Testing.
47 19.4.23 6 Scan Design.
48 20.4.23 1 BIST.
49 21.4.23 4 IDDQ Testing.
50 2.5.23 7 Design for Manufacturability.
51 3.5.23 2 Boundary Scan.
52 4.5.23 6 Revision.

COURSE OBJECTIVES
1. To Study the fundamentals of CMOS circuits and its characteristics.
2. Understanding and realization of combinational digital circuits.
3. Understanding and realization of sequential digital circuits.
4. Impart Knowledge on Architectural choices and performance tradeoffs involved in designing and realizing the circuits in CMOS technology.
5. Understanding the different FPGA architectures and testability of VLSI circuits.

Staff Signature HOD/ECE Principal

 NANDHA COLLEGE OF TECHNOLOGY
Academic Year 2022-23 (Even Semester)
LESSON PLAN
Name of the staff/
Mrs.K.Poornima /AP/E.C.E.
Designation/Dept

Subject Code & Name EC 8095/VLSI DESIGN

Class & Semester III-ECE & VI Semester

No. of Times Already
1
Taken
Lecture : 3 Tutorial : 0 Practical : 0 Credit : 3 Total : 45 Periods

ACTUAL
STAFF HoD
S.No DATE PERIOD TOPICS DATE OF
SIGN SIGN
COMPLETION

UNIT I -INTRODUCTION TO MOS TRANSISTOR

1 Introduction.
2 MOS transistors.
3 CMOS Logic,CMOS Inverter.
4 Pass transistor,Transmission gate.
5 Layout Design Rules,Gate layouts.
6 Stick Diagram.
7 Long channel I-V,C-V characteristics.
8 Non ideal Effects,DC Transfer characteristics.
9 RC delay model,Elmore delay ,Linear Delay model.
10 Logical effort,Parasitic Delay,Delay in logic gates.
11 Scaling.
UNIT II- COMBINATIONAL MOS LOGIC CIRCUITS

12 CircuitFamilies:Static CMOS,Ratioed Circuits.

13 Cascode Voltage Switch Logic.
14 Dynamic Circuits.Pass Transistor Logic.
15 Pass Transistor Logic.
16 Transmission Gates.
17 Domino, Dual Rail Domino.
18 CPL,DCVSPG.
19 DPL, Circuit Pitfalls.
20 Dynamic Power.Static Power.
21 Static Power.
22 Low Power Architecture.
 UNIT III-SEQUENTIAL CIRCUIT DESIGN

23 Static latches and Registers.

24 Dynamic latches and Registers.
25 Pulse Registers.
26 Sense Amplifier Based Register.
27 Pipelining.
28 Schmitt Trigger.
29 Monostable Sequential Circuits.
Astable Sequential
30
Circuits.
31 Timing Classification Of Digital System.
32 Synchronous Design.
UNIT IV- DESIGN OF ARITHMETIC BUILDING BLOCKS AND SUBSYSTEM

ARITHMETIC BUILDING BLOCKS:

33
Data Paths, Adders.
34 Multipliers.
35 Shifters.
36 ALUs.
Power and speed tradeoffs.
37
38 Case Study: Design as a tradeoff.
39 Memory Architectures and Building Blocks.
40 Memory Core.
41 Memory Peripheral Circuitry.
42 Revision.
UNIT-V IMPLEMENTATION STRATEGIES AND TESTING

43 FPGA Introduction.
44 FPGA Building Block Architectures.
45 FPGA Interconnect Routing Procedures.
46 Design for Testability: Ad Hoc Testing.
47 Scan Design.
48 BIST.
49 IDDQ Testing.
50 Design for Manufacturability.
51 Boundary Scan.
52 Revision.

COURSE OBJECTIVES
1. To Study the fundamentals of CMOS circuits and its characteristics.
2. Understanding and realization of combinational digital circuits.
3. Understanding and realization of sequential digital circuits.
4. Impart Knowledge on Architectural choices and performance tradeoffs involved in designing and realizing the circuits in CMOS technology.
5. Understanding the different FPGA architectures and testability of VLSI circuits.
Staff Signature HOD/ECE Principal
 NANDHA COLLEGE OF TECHNOLOGY
Academic Year 2022-23 (Even Semester)
LESSON PLAN
Name of the staff/
Mrs.K.Poornima /AP/E.C.E.
Designation/Dept

Subject Code & Name EC 8095/VLSI DESIGN

Class & Semester III-ECE & VI Semester

No. of Times Already
1
Taken
Lecture : 3 Tutorial : 0 Practical : 0 Credit : 3 Total : 45 Periods

ACTUAL
STAFF HoD
S.No DATE PERIOD TOPICS DATE OF
SIGN SIGN
COMPLETION

UNIT I -INTRODUCTION TO MOS TRANSISTOR

1 Introduction.
2 MOS transistors.
3 CMOS Logic,CMOS Inverter.
4 Pass transistor,Transmission gate.
5 Layout Design Rules,Gate layouts.
6 Stick Diagram.
7 Long channel I-V,C-V characteristics.
8 Non ideal Effects,DC Transfer characteristics.
9 RC delay model,Elmore delay ,Linear Delay model.
10 Logical effort,Parasitic Delay,Delay in logic gates.
11 Scaling.
UNIT II- COMBINATIONAL MOS LOGIC CIRCUITS

12 CircuitFamilies:Static CMOS,Ratioed Circuits.

13 Cascode Voltage Switch Logic.
14 Dynamic Circuits.
15 Pass Transistor Logic.
16 Transmission Gates.
17 Domino, Dual Rail Domino.
18 CPL,DCVSPG.
19 DPL, Circuit Pitfalls.
20 Dynamic Power.
21 Static Power.
22 Low Power Architecture.
 UNIT III-SEQUENTIAL CIRCUIT DESIGN

23 Static latches and Registers.

24 Dynamic latches and Registers.
25 Pulse Registers.
26 Sense Amplifier Based Register.
27 Pipelining.
28 Schmitt Trigger.
29 Monostable Sequential Circuits.
Astable Sequential
30
Circuits.
31 Timing Classification Of Digital System.
32 Synchronous Design.
UNIT IV- DESIGN OF ARITHMETIC BUILDING BLOCKS AND SUBSYSTEM

ARITHMETIC BUILDING BLOCKS:

33
Data Paths, Adders.
34 Multipliers.
35 Shifters.
36 ALUs.
Power and speed tradeoffs.
37
38 Case Study: Design as a tradeoff.
39 Memory Architectures and Building Blocks.
40 Memory Core.
41 Memory Peripheral Circuitry.
42 Revision.
UNIT-V IMPLEMENTATION STRATEGIES AND TESTING

43 FPGA Introduction.
44 FPGA Building Block Architectures.
45 FPGA Interconnect Routing Procedures.
46 Design for Testability: Ad Hoc Testing.
47 Scan Design.
48 BIST.
49 IDDQ Testing.
50 Design for Manufacturability.
51 Boundary Scan.
52 Revision.

COURSE OBJECTIVES
1. To Study the fundamentals of CMOS circuits and its characteristics.
2. Understanding and realization of combinational digital circuits.
3. Understanding and realization of sequential digital circuits.
4. Impart Knowledge on Architectural choices and performance tradeoffs involved in designing and realizing the circuits in CMOS technology.
5. Understanding the different FPGA architectures and testability of VLSI circuits.
Staff Signature HOD/ECE Principal